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| 32 SH7660 Hardware Manual Renesas 32-Bit RISC Microcomputer HD6417660 Rev.1.00 2004.2.6 Rev. 1.00, 02/04, page ii of xxxviii Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 1.00, 02/04, page iii of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 1.00, 02/04, page iv of xxxviii Configuration of This Manual This manual comprises the following items: General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 1. 2. 3. 4. 5. 6. Rev. 1.00, 02/04, page v of xxxviii Preface The SH7660 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-3/SH-3E/SH3-DSP Programming Manual for a detailed description of the instruction set. Notes on reading this manual: Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification SH7660 Product Code HD6417660 In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions, and electrical characteristics. In order to understand the details of the CPU's functions Read the SH-3/SH-3E/SH3-DSP Programming Manual. Rev. 1.00, 02/04, page vi of xxxviii Rules: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ Register name: Related Manuals: SH7660 manuals: Document Title SH7660 Hardware Manual SH-3/SH-3E/SH3-DSP Programming Manual Document No. This manual ADE-602-096 Users manuals for development tools: Document Title SH Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SH Series Simulator/Debugger (for Windows) User's Manual SH Series Simulator/Debugger (for UNIX) User's Manual High-performance Embedded Workshop User's Manual SH Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial Document No. ADE-702-246 ADE-702-186 ADE-702-203 ADE-702-201 ADE-702-230 Rev. 1.00, 02/04, page vii of xxxviii Abbreviations ALU ASE AUD bps BSC CODEC CPG CPU DAC DMAC DSP ESD FIFO Hi-Z H-UDI INTC LSB MSB PC PFC PLL RAM RF RISC ROM SIOF SCIF SOF TAP T.B.D. TLB UBC USB WDT Arithmetic Logic Unit Adaptive System Evaluator Advanced User Debugger bit per second Bus State Controller Coder-Decoder Clock Pulse Generator Central Processing Unit Digital to Analog Converter Direct Memory Access Controller Digital Signal Processor Electrostatic Discharge First-In First-Out High Impedance User Debugging Interface Interrupt Controller Least Significant Bit Most Significant Bit Program Counter Pin Function Controller Phase Locked Loop Random Access Memory Ratio Frequency Reduced Instruction Set Computer Read Only Memory Serial Input Output with FIFO Serial Communication Interface with FIFO Start Of Frame Test Access Port To Be Determined Translation Lookaside Buffer User Break Controller Universal Serial Bus Watch Dog Timer Rev. 1.00, 02/04, page viii of xxxviii Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 1.4 SH7660 Features............................................................................................................... 1 Block Diagram .................................................................................................................. 8 Pin Assignment ................................................................................................................. 9 Pin Functions .................................................................................................................... 21 Section 2 CPU....................................................................................................29 2.1 Processing States and Processing Modes .......................................................................... 29 2.1.1 Processing States.................................................................................................. 29 2.1.2 Processing Modes (User Mode/Privileged Mode) ............................................... 30 Memory Map .................................................................................................................... 31 2.2.1 Logical Address Space......................................................................................... 31 2.2.2 Physical Address Space ....................................................................................... 33 2.2.3 External Address Space ....................................................................................... 34 Register Descriptions ........................................................................................................ 36 2.3.1 General Registers................................................................................................. 38 2.3.2 System Registers.................................................................................................. 39 2.3.3 Program Counter.................................................................................................. 40 2.3.4 Control Registers ................................................................................................. 41 Data Formats..................................................................................................................... 45 2.4.1 Register Data Format ........................................................................................... 45 2.4.2 Memory Data Formats ......................................................................................... 45 Features of Instructions..................................................................................................... 47 2.5.1 Instruction Execution Method.............................................................................. 47 2.5.2 Addressing Modes ............................................................................................... 49 2.5.3 Instruction Formats .............................................................................................. 53 Instruction Set ................................................................................................................... 56 2.6.1 Instruction Set Based on Functions...................................................................... 56 2.6.2 Operation Code Map............................................................................................ 70 2.2 2.3 2.4 2.5 2.6 Section 3 DSP Operating Unit ...........................................................................73 3.1 3.2 DSP Extended Functions .................................................................................................. 73 DSP Mode Resources ....................................................................................................... 75 3.2.1 Processing Modes ................................................................................................ 75 3.2.2 DSP Mode Memory Map..................................................................................... 75 3.2.3 CPU Register Sets................................................................................................ 76 3.2.4 DSP Registers ...................................................................................................... 80 CPU Extended Instructions............................................................................................... 81 3.3.1 DSP Repeat Control............................................................................................. 81 Rev. 1.00, 02/04, page ix of xxxviii 3.3 3.4 3.5 3.6 3.3.2 Extended Repeat Control Instructions ................................................................. 91 DSP Data Transfer Instructions ........................................................................................ 96 3.4.1 General Registers................................................................................................. 99 3.4.2 DSP Data Addressing .......................................................................................... 101 3.4.3 Modulo Addressing ............................................................................................. 103 3.4.4 Memory Data Formats ......................................................................................... 105 3.4.5 Instruction Formats of Double and Single Data Transfer Instructions ................ 105 DSP Data Operation Instructions...................................................................................... 107 3.5.1 DSP Registers ...................................................................................................... 107 3.5.2 DSP Instruction Set.............................................................................................. 111 3.5.3 DSP-Type Data Formats...................................................................................... 116 3.5.4 ALU Fixed-Point Arithmetic Operations............................................................. 118 3.5.5 ALU Integer Operations ...................................................................................... 123 3.5.6 ALU Logical Operations ..................................................................................... 125 3.5.7 Fixed-Point Multiply Operation........................................................................... 126 3.5.8 Shift Operations ................................................................................................... 129 3.5.9 Most Significant Bit Detection Operation ........................................................... 132 3.5.10 Rounding Operation............................................................................................. 135 3.5.11 Overflow Protection............................................................................................. 136 3.5.12 Local Data Move Instruction ............................................................................... 137 3.5.13 Operand Conflict ................................................................................................. 138 DSP Extended Function Instruction Set............................................................................ 139 3.6.1 CPU Extended Instruction Set ............................................................................. 139 3.6.2 Double-Data Transfer Instruction Set .................................................................. 141 3.6.3 Single-Data Transfer Instruction Set ................................................................... 142 3.6.4 DSP Data Operation Instruction Set .................................................................... 144 3.6.5 Operation Code Map in DSP Mode ..................................................................... 150 Section 4 Exception Handling ........................................................................... 155 4.1 Register Descriptions........................................................................................................ 155 4.1.1 TRAPA Exception Register (TRA) ..................................................................... 156 4.1.2 Exception Event Register (EXPEVT).................................................................. 157 4.1.3 Interrupt Event Register 2 (INTEVT2)................................................................ 157 4.1.4 Exception Address Register (TEA) ..................................................................... 157 Exception Handling Function ........................................................................................... 158 4.2.1 Exception Handling Flow .................................................................................... 158 4.2.2 Exception Vector Addresses................................................................................ 159 4.2.3 Exception Codes .................................................................................................. 159 4.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ........................ 159 4.2.5 Exception Source Acceptance Timing and Priority ............................................. 160 Individual Exception Operations ...................................................................................... 164 4.3.1 Resets................................................................................................................... 164 4.3.2 General Exceptions.............................................................................................. 165 4.2 4.3 Rev. 1.00, 02/04, page x of xxxviii 4.4 4.5 Exception Processing While DSP Extension Function is Valid........................................ 168 4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception ................... 168 4.4.2 CPU Address Error .............................................................................................. 168 4.4.3 Exception in Repeat Control Period..................................................................... 168 Usage Notes ...................................................................................................................... 175 Section 5 Cache .................................................................................................177 5.1 5.2 Features............................................................................................................................. 177 5.1.1 Cache Structure.................................................................................................... 177 Register Descriptions ........................................................................................................ 179 5.2.1 Cache Control Register 1 (CCR1) ....................................................................... 179 5.2.2 Cache Control Register 2 (CCR2) ....................................................................... 180 Operation .......................................................................................................................... 183 5.3.1 Searching the Cache............................................................................................. 183 5.3.2 Read Access......................................................................................................... 184 5.3.3 Prefetch Operation ............................................................................................... 184 5.3.4 Write Access ........................................................................................................ 184 5.3.5 Write-Back Buffer ............................................................................................... 185 5.3.6 Coherency of Cache and External Memory ......................................................... 185 Memory-Mapped Cache ................................................................................................... 186 5.4.1 Address Array ...................................................................................................... 186 5.4.2 Data Array ........................................................................................................... 187 5.4.3 Usage Examples................................................................................................... 189 5.3 5.4 Section 6 X/Y Memory......................................................................................191 6.1 6.2 Features............................................................................................................................. 191 Operation .......................................................................................................................... 192 6.2.1 Access from CPU................................................................................................. 192 6.2.2 Access from DSP ................................................................................................. 192 6.2.3 Access from I Bus Master Module ...................................................................... 193 Usage Notes ...................................................................................................................... 193 6.3.1 Page Conflict ....................................................................................................... 193 6.3.2 Bus Conflict ......................................................................................................... 193 6.3.3 Cache Settings...................................................................................................... 193 6.3.4 Sleep Mode .......................................................................................................... 194 6.3 Section 7 U Memory..........................................................................................195 7.1 7.2 Features............................................................................................................................. 195 Operation .......................................................................................................................... 196 7.2.1 Access from CPU................................................................................................. 196 7.2.2 Access from DSP ................................................................................................. 196 7.2.3 Access from I Bus Master Module ...................................................................... 196 Usage Notes ...................................................................................................................... 197 Rev. 1.00, 02/04, page xi of xxxviii 7.3 7.3.1 7.3.2 7.3.3 7.3.4 Page Conflict ....................................................................................................... 197 Bus Conflict ......................................................................................................... 197 Cache Settings ..................................................................................................... 197 sleep mode ........................................................................................................... 198 Section 8 Interrupt Controller (INTC)............................................................... 199 8.1 8.2 8.3 Features............................................................................................................................. 199 Input/Output Pins.............................................................................................................. 201 Register Descriptions........................................................................................................ 201 8.3.1 Interrupt Priority Registers A to H (IPRA to IPRH)............................................ 202 8.3.2 Interrupt Control Register 0 (ICR0)..................................................................... 204 8.3.3 Interrupt Control Register 1 (ICR1)..................................................................... 205 8.3.4 Interrupt Control Register 2 (ICR2)..................................................................... 207 8.3.5 Interrupt Request Register 0 (IRR0) .................................................................... 208 8.3.6 Interrupt Mask Registers 0, 1, 4 to 6, and 9 (IMR0, IMR1, IMR4 to IMR6, and IMR9) ......................................................... 208 8.3.7 Interrupt Mask Clear Registers 0, 1, 4 to 6, and 9 (IMCR0, IMCR1, IMCR4 to IMCR6, and IMCR9) ............................................ 210 Interrupt Sources............................................................................................................... 211 8.4.1 NMI Interrupt....................................................................................................... 211 8.4.2 IRQ Interrupts...................................................................................................... 211 8.4.3 On-Chip Peripheral Module Interrupts ................................................................ 212 8.4.4 Interrupt Exception Handling and Priority........................................................... 212 Operation .......................................................................................................................... 214 8.5.1 Interrupt Sequence ............................................................................................... 214 8.5.2 Multiple Interrupts ............................................................................................... 216 8.4 8.5 Section 9 Bus State Controller (BSC) ............................................................... 217 9.1 9.2 9.3 Overview........................................................................................................................... 217 9.1.1 Features................................................................................................................ 217 Input/Output Pins.............................................................................................................. 220 Area Overview.................................................................................................................. 221 9.3.1 Area Division....................................................................................................... 221 9.3.2 Shadow Area........................................................................................................ 222 9.3.3 Address Map........................................................................................................ 223 9.3.4 Data Bus Width.................................................................................................... 224 Register Descriptions........................................................................................................ 224 9.4.1 Common Control Register (CMNCR) ................................................................. 225 9.4.2 CSn Space Bus Control Register (CSnBCR) (n=0, 3, 4) ..................................... 227 9.4.3 CSn Space Wait Control Register (CSnWCR) (n=0, 3, 4) .................................. 231 9.4.4 SDRAM Control Register (SDCR)...................................................................... 242 9.4.5 Refresh Timer Control/Status Register (RTCSR)................................................ 245 9.4.6 Refresh Timer Counter (RTCNT)........................................................................ 246 9.4 Rev. 1.00, 02/04, page xii of xxxviii 9.5 9.4.7 Refresh Time Constant Register (RTCOR) ......................................................... 247 9.4.8 Reset Wait Counter (RWTCNT).......................................................................... 247 Operating Description ....................................................................................................... 248 9.5.1 Endian/Access Size and Data Alignment............................................................. 248 9.5.2 Normal Space Interface........................................................................................ 251 9.5.3 Access Wait Control ............................................................................................ 256 9.5.4 CSn Assert Period Expansion .............................................................................. 258 9.5.5 SDRAM Interface ................................................................................................ 259 9.5.6 Burst ROM Interface ........................................................................................... 285 9.5.7 Byte-Selection SRAM Interface .......................................................................... 287 9.5.8 Wait between Access Cycles ............................................................................... 291 9.5.9 Bus Arbitration .................................................................................................... 291 9.5.10 Usage Notes ......................................................................................................... 295 Section 10 Direct Memory Access Controller (DMAC) ...................................297 10.1 Features............................................................................................................................. 297 10.2 Input/Output Pins .............................................................................................................. 299 10.3 Register Descriptions ........................................................................................................ 300 10.3.1 DMA Source Address Register (SAR) ................................................................ 301 10.3.2 DMA Destination Address Register (DAR) ........................................................ 301 10.3.3 DMA Transfer Count Register (DMATCR) ........................................................ 301 10.3.4 DMA Channel Control Register (CHCR) ............................................................ 302 10.3.5 DMA Initial Address Register (IAR)................................................................... 308 10.3.6 DMA Operation Register (DMAOR) .................................................................. 308 10.3.7 DMA Extension Resource Selector 0 and 1 (DMARS0 and DMARS1) ............. 310 10.4 Operation .......................................................................................................................... 313 10.4.1 DMA Transfer Flow ............................................................................................ 313 10.4.2 Repeat Mode Transfer.......................................................................................... 315 10.4.3 DMA Transfer Requests ...................................................................................... 315 10.4.4 Channel Priority................................................................................................... 318 10.4.5 DMA Transfer Types........................................................................................... 321 10.4.6 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 328 10.5 Usage Notes ...................................................................................................................... 332 Section 11 Clock Pulse Generator (CPG)..........................................................333 Features............................................................................................................................. 333 Input/Output Pins .............................................................................................................. 336 Clock Operating Modes .................................................................................................... 337 Register Descriptions ........................................................................................................ 340 11.4.1 Frequency Control Register (FRQCR) ................................................................ 340 11.5 Changing the Frequency ................................................................................................... 343 11.5.1 Changing the Multiplication Rate ........................................................................ 343 11.5.2 Changing the Division Ratio................................................................................ 343 Rev. 1.00, 02/04, page xiii of xxxviii 11.1 11.2 11.3 11.4 11.6 Notes on Board Design ..................................................................................................... 344 Section 12 Watchdog Timer (WDT) ................................................................. 347 12.1 Features............................................................................................................................. 347 12.2 Register Descriptions........................................................................................................ 349 12.2.1 Watchdog Timer Counter (WTCNT)................................................................... 349 12.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 349 12.2.3 Notes on Register Access .................................................................................... 351 12.3 Operation .......................................................................................................................... 352 12.3.1 Canceling Software Standby................................................................................ 352 12.3.2 Changing the Frequency ...................................................................................... 352 12.3.3 Using Watchdog Timer Mode ............................................................................. 353 12.3.4 Using Interval Timer Mode ................................................................................. 353 Section 13 Power-Down Modes........................................................................ 355 13.1 Features............................................................................................................................. 355 13.1.1 Power-Down Modes ............................................................................................ 355 13.1.2 Reset .................................................................................................................... 357 13.1.3 Input/Output Pins................................................................................................. 358 13.2 Register Descriptions........................................................................................................ 359 13.2.1 Standby Control Register (STBCR)..................................................................... 360 13.2.2 Standby Control Register 2 (STBCR2)................................................................ 361 13.2.3 Standby Control Register 3 (STBCR3)................................................................ 362 13.2.4 Standby Control Register 4 (STBCR4)................................................................ 363 13.2.5 Memory Clock Control Register (MCCR)........................................................... 365 13.3 Operation .......................................................................................................................... 366 13.3.1 Sleep Mode .......................................................................................................... 366 13.3.2 Software Standby Mode....................................................................................... 366 13.3.3 Module Standby Function.................................................................................... 368 13.3.4 State Transitions between Modes ........................................................................ 369 13.3.5 Method of turning off the built-in regulator (external VDD used) ....................... 369 13.4 Usage note ........................................................................................................................ 370 13.4.1 Reset by the RESETP pin .................................................................................... 370 Section 14 Timer Unit (TMU)........................................................................... 371 14.1 Features............................................................................................................................. 371 14.2 Register Descriptions........................................................................................................ 373 14.2.1 Timer Start Register (TSTR) ............................................................................... 374 14.2.2 Timer Control Registers (TCR) ........................................................................... 374 14.2.3 Timer Constant Registers (TCOR) ...................................................................... 376 14.2.4 Timer Counters (TCNT) ...................................................................................... 376 14.3 Operation .......................................................................................................................... 377 14.3.1 Counter Operation ............................................................................................... 377 Rev. 1.00, 02/04, page xiv of xxxviii 14.4 Interrupts........................................................................................................................... 379 14.4.1 Status Flag Set Timing......................................................................................... 379 14.4.2 Status Flag Clear Timing ..................................................................................... 379 14.4.3 Interrupt Sources and Priorities ........................................................................... 380 14.5 Usage Notes ...................................................................................................................... 380 Section 15 Serial I/O with FIFO (SIOF)............................................................381 15.1 Features............................................................................................................................. 381 15.2 Input/Output Pins .............................................................................................................. 383 15.3 Register Descriptions ........................................................................................................ 384 15.3.1 Mode Register (SIMDR)...................................................................................... 384 15.3.2 Control Register (SICTR) .................................................................................... 387 15.3.3 Transmit Data Register (SITDR) ......................................................................... 390 15.3.4 Receive Data Register (SIRDR) .......................................................................... 391 15.3.5 Transmit Control Data Register (SITCR) ............................................................ 392 15.3.6 Receive Control Data Register (SIRCR) ............................................................. 393 15.3.7 Status Register (SISTR)....................................................................................... 394 15.3.8 Interrupt Enable Register (SIIER)........................................................................ 399 15.3.9 FIFO Control Register (SIFCTR) ........................................................................ 401 15.3.10 Clock Select Register (SISCR) ............................................................................ 403 15.3.11 Transmit Data Assign Register (SITDAR) .......................................................... 404 15.3.12 Receive Data Assign Register (SIRDAR)............................................................ 405 15.3.13 Control Data Assign Register (SICDAR) ............................................................ 406 15.3.14 SPI Control Register (SPICR) ............................................................................. 408 15.4 Operation .......................................................................................................................... 410 15.4.1 Serial Clocks ........................................................................................................ 410 15.4.2 Serial Timing ....................................................................................................... 411 15.4.3 Transfer Data Format........................................................................................... 412 15.4.4 Register Allocation of Transfer Data ................................................................... 413 15.4.5 Control Data Interface ......................................................................................... 416 15.4.6 FIFO..................................................................................................................... 417 15.4.7 Transmit and Receive Procedures........................................................................ 419 15.4.8 Interrupts.............................................................................................................. 424 15.4.9 Transmit and Receive Timing.............................................................................. 426 15.4.10 SPI Mode ............................................................................................................. 430 15.5 Usage Notes ...................................................................................................................... 433 Section 16 Serial Communication Interface with FIFO (SCIF) ........................435 16.1 Features............................................................................................................................. 435 16.2 Input/Output Pins .............................................................................................................. 438 16.3 Register Descriptions ........................................................................................................ 439 16.3.1 Receive Shift Register (SCRSR).......................................................................... 440 16.3.2 Receive FIFO Data Register (SCFRDR) ............................................................. 440 Rev. 1.00, 02/04, page xv of xxxviii 16.3.3 Transmit Shift Register (SCTSR) ........................................................................ 440 16.3.4 Transmit FIFO Data Register (SCFTDR)............................................................ 441 16.3.5 Serial Mode Register (SCSMR)........................................................................... 442 16.3.6 Serial Control Register (SCSCR)......................................................................... 445 16.3.7 FIFO Error Count Register (SCFER) .................................................................. 449 16.3.8 Serial Status Register (SCSSR) ........................................................................... 450 16.3.9 Bit Rate Register (SCBRR) ................................................................................. 456 16.3.10 FIFO Control Register (SCFCR) ......................................................................... 458 16.3.11 FIFO Data Count Register (SCFDR)................................................................... 461 16.3.12 Transmit Data Stop Register (SCTDSR) ............................................................. 461 16.4 Operation .......................................................................................................................... 462 16.4.1 Overview ............................................................................................................. 462 16.4.2 Asynchronous Mode ............................................................................................ 462 16.4.3 Serial Operation in Asynchronous Mode............................................................. 464 16.4.4 Clock Synchronous Mode.................................................................................... 475 16.4.5 Serial Operation in Clock Synchronous Mode .................................................... 476 16.5 SCIF Interrupt Sources and DMAC.................................................................................. 485 16.6 Notes on Usage ................................................................................................................. 487 Section 17 Boot Function (BOOT).................................................................... 491 Features............................................................................................................................. 491 Input/Output Pin ............................................................................................................... 493 Register Description ......................................................................................................... 493 Operation .......................................................................................................................... 494 17.4.1 Address Space in Boot Mode............................................................................... 494 17.4.2 Procedure for Execution of Boot Processing ....................................................... 495 17.5 Usage Note........................................................................................................................ 498 17.5.1 Endian when Using Boot Function ...................................................................... 498 17.5.2 Clock Frequency and Data Transfer Rate when Using Boot Function ................ 498 17.1 17.2 17.3 17.4 Section 18 USB Pin Multiplex Controller (USBPM)........................................ 499 18.1 Feature .............................................................................................................................. 499 18.2 Input/Output Pins.............................................................................................................. 501 18.3 Register Description ......................................................................................................... 502 18.3.1 EXCPG Control Register (EXCPGCR)............................................................... 502 18.4 Examples of External Circuit............................................................................................ 505 18.4.1 Example of the Connection between USB Function Controller and External Circuit ............................................................................................. 505 18.4.2 Example of the Connection between USB Host Controller and External Circuit ............................................................................................. 507 18.5 Usage Notes ...................................................................................................................... 508 Rev. 1.00, 02/04, page xvi of xxxviii Section 19 USB Host Controller (USBH) .........................................................509 19.1 Features............................................................................................................................. 509 19.2 Input/Output Pins .............................................................................................................. 510 19.3 Register Descriptions ........................................................................................................ 511 19.3.1 HcRevision Register (HREVR) ........................................................................... 512 19.3.2 HcControl Register (HCTLR).............................................................................. 513 19.3.3 HcCommandStatus Register (HCSR) .................................................................. 516 19.3.4 HcInterruptStatus Register (HISR) ...................................................................... 518 19.3.5 HcInterruptEnable Register (HIER)..................................................................... 521 19.3.6 HcInterruptDisable Register (HIDR) ................................................................... 524 19.3.7 HcHCCA Register (HHCCAR) ........................................................................... 526 19.3.8 HcPeriodCurrentED Register (HPCEDR) ........................................................... 527 19.3.9 HcControlHeadED Register (HCHEDR)............................................................. 527 19.3.10 HcControlCurrentED Register (HCCEDR) ......................................................... 527 19.3.11 HcBulkHeadED Register (HBHEDR) ................................................................. 528 19.3.12 HcBulkCurrentED Register (HBCEDR).............................................................. 528 19.3.13 HcDoneHeadED Register (HDHEDR) ................................................................ 528 19.3.14 HcFmInterval Register (HFIR) ............................................................................ 529 19.3.15 HcFmRemaining Register (HFRR)...................................................................... 531 19.3.16 HcFmNumber Register (HFNR).......................................................................... 532 19.3.17 HcPeriodicStart Register (HPSR) ........................................................................ 533 19.3.18 HcLSThreshold Register (HLSTR) ..................................................................... 534 19.3.19 HcRhDescriptorA Register (HRDRA)................................................................. 535 19.3.20 HcRhDescriptorB Register (HRDRB) ................................................................. 537 19.3.21 HcRhStatus Register (HRSR) .............................................................................. 538 19.3.22 HcRhPortStatus Register (HRPSR) ..................................................................... 540 19.4 Data Storage Format of USB Host Controller .................................................................. 546 19.4.1 Storage Format of Transferred Data .................................................................... 546 19.4.2 Storage Format of Descriptor............................................................................... 546 19.5 Usage Restrictions of USB Host Controller...................................................................... 546 19.5.1 Restriction of Reset Control................................................................................. 546 Section 20 USB Function Controller (USBF) ...................................................547 20.1 Features............................................................................................................................. 547 20.2 Input/Output Pins .............................................................................................................. 549 20.3 Register Descriptions ........................................................................................................ 550 20.3.1 Interrupt Flag Register 0 (IFR0) .......................................................................... 551 20.3.2 Interrupt Select Register 0 (ISR0)........................................................................ 558 20.3.3 Interrupt Enable Register 0 (IER0) ...................................................................... 563 20.3.4 EP0i Data Register (EPDR0i).............................................................................. 566 20.3.5 EP0o Data Register (EPDR0o) ............................................................................ 567 20.3.6 EP0s Data Register (EPDR0s) ............................................................................. 567 Rev. 1.00, 02/04, page xvii of xxxviii 20.4 20.5 20.6 20.7 20.8 20.3.7 EP1 Data Register (EPDR1) ................................................................................ 567 20.3.8 EP2i Data Register (EPDR2i).............................................................................. 568 20.3.9 EP2o Data Register (EPDR2o) ............................................................................ 568 20.3.10 EP3i Data Register (EPDR3i).............................................................................. 568 20.3.11 EP3o Data Register (EPDR3o) ............................................................................ 569 20.3.12 EP4 Data Register (EPDR4) ................................................................................ 569 20.3.13 EP5 Data Register (EPDR5) ................................................................................ 569 20.3.14 EP6 Data Register (EPDR6) ................................................................................ 570 20.3.15 EP0o Receive Data Size Register (EPSZ0o) ....................................................... 570 20.3.16 EP2o Receive Data Size Register (EPSZ2o) ....................................................... 570 20.3.17 EP3o Receive Data Size Register (EPSZ3o) ....................................................... 570 20.3.18 EP6 Receive Data Size Register (EPSZ6) ........................................................... 571 20.3.19 Trigger Register (TRG) ....................................................................................... 571 20.3.20 Data Status Register (DASTS)............................................................................. 572 20.3.21 FIFO Clear Register (FCLR) ............................................................................... 572 20.3.22 DMA Transfer Setting Register (DMA) .............................................................. 573 20.3.23 Endpoint Stall Register (EPSTL)......................................................................... 574 20.3.24 Configuration Value Register (CVR) .................................................................. 575 20.3.25 Time Stamp Register (TSR) ................................................................................ 576 20.3.26 Control Register (CLTR) ..................................................................................... 576 20.3.27 Endpoint Information Register (EPIRn0 to EPIRn5)........................................... 578 Operation .......................................................................................................................... 586 20.4.1 Cable Connection................................................................................................. 586 20.4.2 Cable Disconnection ............................................................................................ 587 20.4.3 Control Transfer................................................................................................... 587 20.4.4 EP1, 4 Interrupt-In Transfer................................................................................. 593 20.4.5 EP2i, 5 Bulk-In Transfer (Dual FIFOs) ............................................................... 594 20.4.6 EP2o, 6 Bulk-Out Transfer (Dual FIFOs)............................................................ 595 20.4.7 EP3i Isochronous-In Transfer .............................................................................. 597 20.4.8 EP3o Isochronous Out Transfer........................................................................... 599 Processing of USB Standard Commands and Class/Vendor Commands ......................... 601 20.5.1 Processing of Commands Transmitted by Control Transfer................................ 601 Stall Operations................................................................................................................. 602 20.6.1 Overview ............................................................................................................. 602 20.6.2 Forcible Stall by Application ............................................................................... 602 20.6.3 Automatic Stall by USB Function Module .......................................................... 604 Example of External Circuitry for USB Function Controller ........................................... 605 Usage Notes ...................................................................................................................... 606 20.8.1 Setup Data Reception .......................................................................................... 606 20.8.2 FIFO Clear........................................................................................................... 606 20.8.3 Overreading/Overwriting of Data Register.......................................................... 606 20.8.4 Assigning EP0 Interrupt Sources ......................................................................... 607 20.8.5 FIFO Clear when DMA Transfer is Set ............................................................... 607 Rev. 1.00, 02/04, page xviii of xxxviii 20.8.6 20.8.7 20.8.8 20.8.9 Note on Using TR Interrupt ................................................................................. 607 Note on Clearing and Transition to Software Standby Mode .............................. 609 Main Clock Usage when Using Bus Password Function ..................................... 610 Peripheral clock for USB ..................................................................................... 610 Section 21 Bluetooth Interface (BT)..................................................................611 21.1 21.2 21.3 21.4 21.5 Features............................................................................................................................. 611 Input/Output Pins .............................................................................................................. 613 Register Description.......................................................................................................... 614 RF-IC Interface ................................................................................................................. 614 21.4.1 Connection with RF ICs....................................................................................... 614 Voice Codec IC Interface.................................................................................................. 616 21.5.1 Voice Codec (STLC7550) Interface .................................................................... 616 21.5.2 Voice Codec (MC145483) Interface.................................................................... 617 Low-Frequency Clock Oscillator Interface....................................................................... 618 21.6.1 Using RTCSEL1 Bit to Select Clock Function.................................................... 618 21.6.2 Frequency-Conversion Circuit Operations .......................................................... 619 21.6.3 Note on Connecting External Crystal Resonator ................................................. 620 Power-On Reset/Clock-Resume Control Circuit .............................................................. 621 21.7.1 Power-On Reset ................................................................................................... 621 21.7.2 Clock-Resume Control ........................................................................................ 622 Bluetooth HCI/TCI Commands and API .......................................................................... 622 21.6 21.7 21.8 Section 22 D/A Converter (DAC)......................................................................623 22.1 Features............................................................................................................................. 623 22.2 Input/Output Pins .............................................................................................................. 624 22.3 Register Descriptions ........................................................................................................ 624 22.3.1 D/A Data Registers 0 and 1 (DADR_0, DADR_1) ............................................. 624 22.3.2 D/A Control Register (DACR) ............................................................................ 625 22.4 Operation .......................................................................................................................... 625 Section 23 I/O Ports ...........................................................................................627 23.1 Port A................................................................................................................................ 627 23.1.1 Register Description ............................................................................................ 627 23.1.2 Port A Data Register (PADR).............................................................................. 628 23.2 Port B ................................................................................................................................ 629 23.2.1 Register Description ............................................................................................ 629 23.2.2 Port B Data Register (PBDR) .............................................................................. 629 23.3 Port D................................................................................................................................ 631 23.3.1 Register Description ............................................................................................ 631 23.3.2 Port D Data Register (PDDR).............................................................................. 631 23.4 Port E ................................................................................................................................ 633 23.4.1 Register Description ............................................................................................ 633 Rev. 1.00, 02/04, page xix of xxxviii 23.4.2 Port E Data Register (PEDR)............................................................................... 633 23.5 Port G................................................................................................................................ 635 23.5.1 Register Description ............................................................................................ 635 23.5.2 Port G Data Register (PGDR).............................................................................. 636 23.6 Port H................................................................................................................................ 637 23.6.1 Register Description ............................................................................................ 637 23.6.2 Port H Data Register (PHDR).............................................................................. 637 Section 24 Pin Function Controller (PFC) ........................................................ 639 24.1 Overview........................................................................................................................... 639 24.2 Register Descriptions........................................................................................................ 641 24.2.1 Port A Control Register (PACR) ......................................................................... 641 24.2.2 Port B Control Register (PBCR).......................................................................... 643 24.2.3 Port D Control Register (PDCR) ......................................................................... 644 24.2.4 Port E Control Register (PECR) .......................................................................... 646 24.2.5 Port G Control Register (PGCR) ......................................................................... 647 24.2.6 Port H Control Register (PHCR) ......................................................................... 649 24.2.7 Pin Select Register A (PSELA) ........................................................................... 650 24.2.8 I/O Buffer Hi-Z Control Register A (HIZCRA) .................................................. 652 24.2.9 Noise Canceller Control Register (NCCR).......................................................... 654 Section 25 User Break Controller...................................................................... 655 25.1 Features............................................................................................................................. 655 25.2 Register Descriptions........................................................................................................ 657 25.2.1 Break Address Register A (BARA).................................................................... 657 25.2.2 Break Address Mask Register A (BAMRA)........................................................ 658 25.2.3 Break Bus Cycle Register A (BBRA).................................................................. 658 25.2.4 Break Address Register B (BARB) ..................................................................... 660 25.2.5 Break Address Mask Register B (BAMRB) ........................................................ 661 25.2.6 Break Data Register B (BDRB)........................................................................... 661 25.2.7 Break Data Mask Register B (BDMRB).............................................................. 662 25.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 663 25.2.9 Break Control Register (BRCR) .......................................................................... 664 25.2.10 Execution Times Break Register (BETR)............................................................ 667 25.2.11 Branch Source Register (BRSR).......................................................................... 669 25.2.12 Branch Destination Register (BRDR).................................................................. 670 25.3 Operation .......................................................................................................................... 671 25.3.1 Flow of the User Break Operation ....................................................................... 671 25.3.2 Break on Instruction Fetch Cycle ........................................................................ 672 25.3.3 Break on Data Access Cycle................................................................................ 673 25.3.4 Break on X/Y-Memory Bus Cycle ...................................................................... 674 25.3.5 Sequential Break.................................................................................................. 674 25.3.6 Value of Saved Program Counter ........................................................................ 675 Rev. 1.00, 02/04, page xx of xxxviii 25.3.7 PC Trace .............................................................................................................. 676 25.3.8 Usage Examples................................................................................................... 676 25.4 Usage Notes ...................................................................................................................... 681 Section 26 User Debugging Interface (H-UDI) .................................................683 26.1 Features............................................................................................................................. 683 26.2 Input/Output Pins .............................................................................................................. 684 26.3 Register Descriptions ........................................................................................................ 685 26.3.1 Bypass Register (SDBPR) ................................................................................... 685 26.3.2 Instruction Register (SDIR) ................................................................................. 685 26.3.3 Boundary Scan Register (SDBSR) ...................................................................... 686 26.3.4 ID Register (SDID).............................................................................................. 691 26.4 Operation .......................................................................................................................... 692 26.4.1 TAP Controller .................................................................................................... 692 26.4.2 Reset Configuration ............................................................................................. 693 26.4.3 TDO Output Timing ............................................................................................ 693 26.5 Boundary Scan .................................................................................................................. 694 26.5.1 Supported Instructions ......................................................................................... 694 26.5.2 Cautions ............................................................................................................... 695 26.6 Usage Notes ...................................................................................................................... 696 Section 27 List of Registers ...............................................................................697 27.1 Register Addresses (by functional module, in order of the corresponding section numbers) .......................... 698 27.2 Register Bits...................................................................................................................... 705 27.3 Register States in Each Operating Mode .......................................................................... 722 Section 28 Electrical Characteristics .................................................................729 28.1 Absolute Maximum Ratings ............................................................................................. 729 28.2 DC Characteristics ............................................................................................................ 731 28.3 AC Characteristics ............................................................................................................ 735 28.3.1 Clock Timing ....................................................................................................... 736 28.3.2 Control Signal Timing ......................................................................................... 740 28.3.3 AC Bus Timing.................................................................................................... 743 28.3.4 Basic Timing........................................................................................................ 745 28.3.5 Burst ROM Timing.............................................................................................. 752 28.3.6 Synchronous DRAM Timing............................................................................... 753 28.3.7 Peripheral Module Signal Timing........................................................................ 776 28.3.8 SIOF Module Signal Timing ............................................................................... 777 28.3.9 SCIF Module Signal Timing................................................................................ 781 28.3.10 USB Module Signal Timing ................................................................................ 782 28.3.11 USB Transceiver Timing ..................................................................................... 783 28.3.12 Bluetooth Interface (BT) Timing ......................................................................... 785 Rev. 1.00, 02/04, page xxi of xxxviii 28.3.13 AC Characteristic Test Conditions ...................................................................... 789 28.4 D/A Converter Characteristics .......................................................................................... 790 Appendix A. B. ......................................................................................................... 791 C. Pin States .......................................................................................................................... 791 Usage Notes for Oscillator circuit with External Crystal Resonator................................. 795 B.1 Recommended Oscillator Circuit......................................................................... 795 B.2 Note on PCB design............................................................................................. 796 Package Dimensions ......................................................................................................... 797 Index ......................................................................................................... 799 Rev. 1.00, 02/04, page xxii of xxxviii Figures Section 1 Overview Figure 1.1 Block Diagram of SH7660 ............................................................................................ 8 Figure 1.2 Pin Assignment ............................................................................................................. 9 Section 2 CPU Figure 2.1 Processing State Transitions........................................................................................ 30 Figure 2.2 Logical Address Space ................................................................................................ 32 Figure 2.3 P4 Area........................................................................................................................ 33 Figure 2.4 Physical Address Space............................................................................................... 34 Figure 2.5 External Address Space and Mounted Space (Area 0) ................................................ 35 Figure 2.6 Register Configuration in Each Processing Mode....................................................... 37 Figure 2.7 General Registers ........................................................................................................ 39 Figure 2.8 System Registers and Program Counter ...................................................................... 40 Figure 2.9 Control Register Configuration ................................................................................... 44 Figure 2.10 Data Format on Memory (Big Endian Mode) ........................................................... 46 Figure 2.11 Data Format on Memory (Little Endian Mode) ........................................................ 46 Section 3 DSP Operating Unit Figure 3.1 DSP Instruction Format............................................................................................... 74 Figure 3.2 CPU Registers in DSP Mode....................................................................................... 76 Figure 3.3 DSP Register Configuration ........................................................................................ 80 Figure 3.4 DSP Registers and Bus Connections ........................................................................... 97 Figure 3.5 General Registers (DSP Mode) ................................................................................. 100 Figure 3.6 Sample Parallel DSP Instruction Program................................................................. 113 Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions ....................... 115 Figure 3.8 Data Formats ............................................................................................................. 117 Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow........................................................... 118 Figure 3.10 Operation Sequence Example.................................................................................. 120 Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode ........................................ 121 Figure 3.12 DC Bit Generation Examples in Negative Value Mode .......................................... 121 Figure 3.13 DC Bit Generation Examples in Overflow Mode.................................................... 122 Figure 3.14 ALU Integer Arithmetic Operation Flow ................................................................ 123 Figure 3.15 ALU Logical Operation Flow ................................................................................. 125 Figure 3.16 Fixed-Point Multiply Operation Flow ..................................................................... 127 Figure 3.17 Arithmetic Shift Operation Flow............................................................................. 129 Figure 3.18 Logical Shift Operation Flow.................................................................................. 131 Figure 3.19 PDMSB Operation Flow ......................................................................................... 133 Figure 3.20 Rounding Operation Flow ....................................................................................... 135 Figure 3.21 Definition of Rounding Operation........................................................................... 136 Figure 3.22 Local Data Move Instruction Flow.......................................................................... 137 Rev. 1.00, 02/04, page xxiii of xxxviii Section 4 Exception Handling Figure 4.1 Register Bit Configuration ........................................................................................ 156 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Cache Cache Structure ......................................................................................................... 177 Cache Search Scheme ............................................................................................... 183 Write-Back Buffer Configuration.............................................................................. 185 Specifying Address and Data for Memory-Mapped Cache Access .......................... 188 Section 8 Interrupt Controller (INTC) Figure 8.1 Block Diagram of INTC............................................................................................ 200 Figure 8.2 Interrupt Operation Flowchart................................................................................... 215 Bus State Controller (BSC) BSC Functional Block Diagram................................................................................ 219 Logical Address Space and Physical Address Space ................................................ 221 Normal Space Basic Access Timing (Access Wait 0)............................................... 251 Continuous Access for Normal Space 1 Data Bus Width = 16 bits, Long-Word Access, CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0) ...... 253 Figure 9.5 Continuous Access for Normal Space 2 Data Bus Width = 16 bits, Long-Word Access, CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0) ...... 254 Figure 9.6 Example of 16-Bit Data-Width SRAM Connection.................................................. 255 Figure 9.7 Example of 8-Bit Data-Width SRAM Connection.................................................... 255 Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only) ................................. 256 Figure 9.9 Wait State Timing for Normal Space Access (Wait State Insertion using WAIT Signal) ................................................................ 257 Figure 9.10 CSn Assert Period Expansion.................................................................................. 258 Figure 9.11 Example of 16-Bit Data-Width SDRAM Connection ............................................. 260 Figure 9.12 Burst Read Basic Timing (Auto Pre-charge)........................................................... 268 Figure 9.13 Burst Read Wait Specification Timing (Auto Pre-charge)...................................... 268 Figure 9.14 Single Read Wait Specification Timing (Auto Pre-charge) .................................... 269 Figure 9.15 Basic Timing for Synchronous DRAM Burst Write (Auto Pre-charge).................. 270 Figure 9.16 Single Write Basic Timing (Auto-Precharge) ......................................................... 271 Figure 9.17 Burst Read Timing (No Auto Precharge) ................................................................ 273 Figure 9.18 Burst Read Timing (Bank Active, Same Row Address) ......................................... 273 Figure 9.19 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 274 Figure 9.20 Single Write Timing (No Auto Precharge).............................................................. 275 Figure 9.21 Single Write Timing (Bank Active, Same Row Address)....................................... 276 Figure 9.22 Single Write Timing (Bank Active, Different Row Addresses).............................. 277 Figure 9.23 Auto-Refresh Timing .............................................................................................. 278 Figure 9.24 Self-Refresh Timing ................................................................................................ 280 Figure 9.25 Low-Frequency Mode Access Timing .................................................................... 281 Figure 9.26 Power-Down Mode Access Timing ........................................................................ 282 Figure 9.27 Synchronous DRAM Mode Write Timing (Based on JEDEC)............................... 284 Rev. 1.00, 02/04, page xxiv of xxxviii Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.28 Burst ROM Access (Data Bus Width 8 Bits, 4-byte Transfer (number of burst 4), Access Wait for the 1st time 2, Access Wait for 2nd Time and after 1).................. 286 Figure 9.29 Byte-Selection SRAM Basic Access Timing (BAS = 0)......................................... 288 Figure 9.30 Byte-Selection RAM Basic Access Timing (BAS = 1)........................................... 289 Figure 9.31 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 289 Figure 9.32 Waveform in the Event of a Problem ...................................................................... 290 Figure 9.33 Bus Arbitration Timing (Master Mode) .................................................................. 293 Figure 9.34 Master and Slave Connection Example................................................................... 294 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Direct Memory Access Controller (DMAC) Block Diagram of the DMAC ................................................................................. 298 DMA Transfer Flowchart ........................................................................................ 314 Round-Robin Mode................................................................................................. 319 Changes in Channel Priority in Round-Robin Mode............................................... 320 Data Flow of Dual Address Mode........................................................................... 322 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary memory, Destination: Ordinary memory).................................. 323 Figure 10.7 Data Flow in Single Address Mode......................................................................... 324 Figure 10.8 Example of DMA Transfer Timing in Single Address Mode.................................. 324 Figure 10.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) ......................................................... 325 Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual address, DREQ low level detection) ............................................................ 326 Figure 10.11 DMA Transfer Example in the Burst Mode (Dual Address, DREQ low level detection)........................................................... 326 Figure 10.12 Bus State when Multiple Channels Are Operating................................................ 328 Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 329 Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 329 Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 329 Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 330 Figure 10.17 Example of DMA Transfer End Signal Timing in Cycle Steel Mode Level Detection ............................................................................................................... 330 Figure 10.18 BSC Ordinary Memory Access (No wait, Idle Cycle 1, Longword Access to 16-bit Device)................................. 331 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Clock Pulse Generator (CPG) Block Diagram of Clock Pulse Generator ............................................................... 334 Note on Using a Crystal Resonator ......................................................................... 344 Note on Using a PLL Oscillator Circuit .................................................................. 345 Section 12 Watchdog Timer (WDT) Figure 12.1 Block Diagram of the WDT .................................................................................... 348 Figure 12.2 Writing to WTCNT and WTCSR............................................................................ 352 Rev. 1.00, 02/04, page xxv of xxxviii Section 13 Power-Down Modes Figure 13.1 Canceling Standby Mode with STBCR.STBY........................................................ 368 Figure 13.2 Transitions between Modes..................................................................................... 369 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Timer Unit (TMU) TMU Block Diagram .............................................................................................. 372 Setting Count Operation.......................................................................................... 377 Auto-Reload Count Operation................................................................................. 378 Count Timing when Internal Clock Is Operating .................................................... 378 UNF Set Timing ...................................................................................................... 379 Status Flag Clear Timing......................................................................................... 379 Section 15 Serial I/O with FIFO (SIOF) Figure 15.1 Block Diagram of SIOF .......................................................................................... 382 Figure 15.2 Serial Clock Supply................................................................................................. 410 Figure 15.3 Serial Data Synchronization Timing ....................................................................... 411 Figure 15.4 SIOF Transmit/Receive Timing .............................................................................. 412 Figure 15.5 Transmit/Receive Data Bit Alignment .................................................................... 414 Figure 15.6 Control Data Bit Alignment .................................................................................... 415 Figure 15.7 Control Data Interface (Slot Position)..................................................................... 416 Figure 15.8 Control Data Interface (Secondary FS) ................................................................... 417 Figure 15.9 Example of Transmit Operation in Master Mode.................................................... 419 Figure 15.10 Example of Receive Operation in Master Mode ................................................... 420 Figure 15.11 Example of Transmit Operation in Slave Mode .................................................... 421 Figure 15.12 Example of Receive Operation in Slave Mode ..................................................... 422 Figure 15.13 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 426 Figure 15.14 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 426 Figure 15.15 Transmit and Receive Timing (16-Bit Monaural Data (1))................................... 427 Figure 15.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 427 Figure 15.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 428 Figure 15.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 428 Figure 15.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 429 Figure 15.20 Transmit and Receive Timing (16-Bit Stereo Data).............................................. 429 Figure 15.21 Example of Configuration in SPI Mode ................................................................ 430 Figure 15.22 SPI Data/Clock Timing 1 (CPHA = 0).................................................................. 432 Figure 15.23 SPI Data/Clock Timing 2 (CPHA = 1).................................................................. 432 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Serial Communication Interface with FIFO (SCIF) Block Diagram of SCIF........................................................................................... 437 Sample SCIF Initialization Flowchart ..................................................................... 466 Sample Serial Transmission Flowchart ................................................................... 467 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 469 Figure 16.5 Example of Transmit Data Stop Function ............................................................... 469 Rev. 1.00, 02/04, page xxvi of xxxviii Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9 Transmit Data Stop Function Flowchart ................................................................. 470 Sample Serial Reception Flowchart (1)................................................................... 471 Sample Serial Reception Flowchart (2)................................................................... 472 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 474 Figure 16.10 CTS Control Operation ......................................................................................... 474 Figure 16.11 RTS Control Operation ......................................................................................... 475 Figure 16.12 Data Format in Clock Synchronous Communication ............................................ 476 Figure 16.13 Sample SCIF Initialization Flowchart (1) (Transmission) .................................... 477 Figure 16.13 Sample SCIF Initialization Flowchart (2) (Reception).......................................... 478 Figure 16.13 Sample SCIF Initialization Flowchart (3) (Simultaneous Transmission and Reception) ........................................................ 479 Figure 16.14 Sample Serial Transmission Flowchart (1) (First Transmission after Initialization) ................................................................. 480 Figure 16.14 Sample Serial Transmission Flowchart (2) (Second and Subsequent Transmission) ................................................................ 480 Figure 16.15 Sample Serial Reception Flowchart (1) (First Reception after Initialization) ...................................................................... 481 Figure 16.15 Sample Serial Reception Flowchart (2) (Second and Subsequent Reception) ..................................................................... 482 Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1) (First Transfer after Initialization)......................................................................... 483 Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2) (Second and Subsequent Transfer) ........................................................................ 484 Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode ...................................... 488 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Boot Function (BOOT) Block Diagram of Boot Function ............................................................................ 492 External Memory Space in Boot Mode ................................................................... 494 Procedure for Execution of Boot Processing........................................................... 497 Section 18 USB Pin Multiplex Controller (USBPM) Figure 18.1 Block Diagram of this USB..................................................................................... 500 Figure 18.2 Example 1 of Connection between USB Function Controller and External Circuit................................................................................................. 505 Figure 18.3 Example 2 of Connection between USB Function Controller and External Circuit................................................................................................. 506 Figure 18.4 Example of Connection USB Host Controller and External Circuit ....................... 507 Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 USB Function Controller (USBF) Block Diagram of USB Function Controller ........................................................... 549 Example of Endpoint Configuration (1) .................................................................. 582 Example of Endpoint Configuration (2) .................................................................. 585 Cable Connection Operation ................................................................................... 586 Rev. 1.00, 02/04, page xxvii of xxxviii Figure 20.5 Cable Disconnection Operation............................................................................... 587 Figure 20.6 Transfer Stages in Control Transfer ........................................................................ 587 Figure 20.7 Setup Stage Operation ............................................................................................. 588 Figure 20.8 Data Stage (Control-In) Operation .......................................................................... 589 Figure 20.9 Data Stage (Control-Out) Operation ....................................................................... 590 Figure 20.10 Status Stage (Control-In) Operation...................................................................... 591 Figure 20.11 Status Stage (Control-Out) Operation ................................................................... 592 Figure 20.12 EP1 Interrupt-In Transfer Operation ..................................................................... 593 Figure 20.13 EP2 Bulk-In Transfer Operation ........................................................................... 594 Figure 20.14 EP2o Bulk-Out Transfer Operation....................................................................... 595 Figure 20.15 Operation of Isochronous-In Transfer ................................................................... 597 Figure 20.16 Operation of EP3o Isochronous-Out Transfer....................................................... 599 Figure 20.17 Forcible Stall by Application ................................................................................ 603 Figure 20.18 Automatic Stall by USB Function Module............................................................ 604 Figure 20.19 Example of USB Function Module External Circuitry ......................................... 605 Figure 20.20 Set Timing of TR Interrupt Flag............................................................................ 608 Figure 20.21 Example Flow of Clearing and Transition to Software Standby Mode................. 609 Section 21 Bluetooth Interface (BT) Figure 21.1 Block Diagram of Bluetooth Interface (BT)............................................................ 612 Figure 21.2 Example of Connection to RF IC ............................................................................ 614 Figure 21.3 Example of Connection to Voice Codec (STLC7550) ............................................ 616 Figure 21.4 (1) Example of Connection to Voice Codec (MC145483) ...................................... 617 Figure 21.4 (2) Timing chart for connection to Voice Codec (MC145483) ............................... 617 Figure 21.5 Function of Frequency-Conversion Circuit............................................................. 619 Figure 21.6 Errors in Pseudo-32-kHz Clock Obtained by Conversion from 32.768-kHz Clock........................................................................................... 620 Figure 21.7 Note on Using Crystal Resonator ............................................................................ 621 Figure 21.8 Timing Chart of Reset Signal.................................................................................. 622 Section 22 D/A Converter (DAC) Figure 22.1 Block Diagram of DAC........................................................................................... 623 Figure 22.2 D/A Converter Operation Example ......................................................................... 626 Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Figure 23.5 Figure 23.6 I/O Ports Port A ...................................................................................................................... 627 Port B ...................................................................................................................... 629 Port D ...................................................................................................................... 631 Port E....................................................................................................................... 633 Port G ...................................................................................................................... 635 Port H ...................................................................................................................... 637 Rev. 1.00, 02/04, page xxviii of xxxviii Section 25 User Break Controller Figure 25.1 Block Diagram of User Break Controller................................................................ 656 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 User Debugging Interface (H-UDI) Block Diagram of H-UDI........................................................................................ 683 TAP Controller State Transitions ............................................................................ 692 H-UDI Data Transfer Timing.................................................................................. 693 Example of Connecting Reset Signals without Mutual Interference....................... 696 Section 28 Electrical Characteristics Figure 28.1 EXTAL Clock Input Timing ................................................................................... 737 Figure 28.2 CKIO Clock Input Timing....................................................................................... 737 Figure 28.3 CKIO Clock Output Timing.................................................................................... 737 Figure 28.4 Power-On Oscillation Settling Time ....................................................................... 737 Figure 28.5 Oscillation Settling Time on Return from Standby (Return by Reset) .................... 738 Figure 28.6 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ) ......... 738 Figure 28.7 PLL Synchronization Settling Time at Power-On Reset ......................................... 738 Figure 28.8 PLL Synchronization Settling Time in Case of Reset or NMI Interrupt ................. 739 Figure 28.9 Reset and BOOT-E Input Timing............................................................................ 741 Figure 28.10 Interrupt Signal Input Timing................................................................................ 741 Figure 28.11 IRQOUT Timing ................................................................................................... 741 Figure 28.12 REFOUT Timing................................................................................................... 742 Figure 28.13 Bus Release Timing............................................................................................... 742 Figure 28.14 Pin Drive Timing at Standby................................................................................. 742 Figure 28.15 Basic Bus Cycle in Normal Space (No Wait)........................................................ 745 Figure 28.16 Basic Bus Cycle in Normal Space (Software Wait 1) ........................................... 746 Figure 28.17 Basic Bus Cycle in Normal Space (Asynchronous External Wait 1 Input)........... 747 Figure 28.18 Basic Bus Cycle in Normal Space (Software Wait 1, Asynchronous External Wait Valid (WM Bit = 0), No Idle Cycle)...................................................................... 748 Figure 28.19 CS Extended Bus Cycle in Normal Space (SW = 1 Cycle, HW = 1 Cycle, Asynchronous External Wait 1 Input) ................ 749 Figure 28.20 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, Asynchronous External Wait 1 Input, BAS = 0 (UB and LB in Write Cycle Controlled)) ............................................... 750 Figure 28.21 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, Asynchronous External Wait 1 Input, BAS = 1 (WE in Write Cycle Controlled))............................................................ 751 Figure 28.22 Read Bus Cycle of Burst ROM (Software Wait 1, Asynchronous External Wait 1 Input, Burst Wait 1, Number of Burst 2) ............................................................... 752 Figure 28.23 Single Read Bus Cycle of Synchronous DRAM (Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 1 Cycle) ........ 753 Figure 28.24 Single Read Bus Cycle of Synchronous DRAM (Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycle, TRP = 2 Cycle) ........ 754 Rev. 1.00, 02/04, page xxix of xxxviii Figure 28.25 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 2 Cycle) ........ 755 Figure 28.26 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycle, TRP = 1 Cycle) ........ 756 Figure 28.27 Single Write Bus Cycle of Synchronous DRAM (Auto Precharge Mode, TRWL = 1 Cycle)............................................................ 757 Figure 28.28 Single Write Bus Cycle of Synchronous DRAM (Auto Precharge Mode, TRCD = 3 Cycle, TRWL = 1 Cycle) .............................. 758 Figure 28.29 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) .............................. 759 Figure 28.30 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) .............................. 760 Figure 28.31 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Bank Active Mode: ACTV + READ Command, CAS Latency 2, TRCD = 1 Cycle)................................................................................................... 761 Figure 28.32 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, TRCD = 1 Cycle)................................................................................................... 762 Figure 28.33 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Bank Active Mode: PRE + ACTV + READ Command, Different Row Address, CAS Latency 2, TRCD = 1 Cycle) ........................................................................ 763 Figure 28.34 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................... 764 Figure 28.35 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................... 765 Figure 28.36 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Bank Active Mode: PRE + ACTV + WRIT Command, TRCD = 1 Cycle)......... 766 Figure 28.37 Auto Refresh Timing of Synchronous DRAM (TRP = 2 Cycle) .......................... 767 Figure 28.38 Self Refresh Timing of Synchronous DRAM (TRP = 2 Cycle) ............................ 768 Figure 28.39 Power-On Sequence of Synchronous DRAM (Mode Write Timing, TRP = 2 Cycle)................................................................... 769 Figure 28.40 Access Timing in Low-Frequency Mode of Synchronous DRAM (Auto Precharge Mode, TRWL = 1 Cycle)............................................................ 770 Figure 28.41 Auto Refresh Timing in Low-Frequency Mode of Synchronous DRAM (TRP = 2 Cycle)..................................................................................................... 771 Figure 28.42 Self Refresh Timing in Low-Frequency Mode of Synchronous DRAM (TRP = 2 Cycle)..................................................................................................... 772 Figure 28.43 Power-On Sequence in Low-Frequency Mode of Synchronous DRAM (Mode Write Timing, TRP = 2 Cycle)................................................................... 773 Figure 28.44 Write to Read Bus Cycle in Power-Down Mode of Synchronous DRAM (Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)..... 774 Figure 28.45 Read to Write Bus Cycle in Power-Down Mode of Synchronous DRAM (Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)..... 775 Rev. 1.00, 02/04, page xxx of xxxviii Figure 28.46 Figure 28.47 Figure 28.48 Figure 28.49 Figure 28.50 Figure 28.51 Figure 28.52 Figure 28.53 Figure 28.54 Figure 28.55 Figure 28.56 Figure 28.57 Figure 28.58 Figure 28.59 Figure 28.60 Figure 28.61 Figure 28.62 Figure 28.63 Figure 28.64 Figure 28.65 Figure 28.66 Figure 28.67 Figure 28.68 Figure 28.69 I/O Port Timing ..................................................................................................... 776 DREQ Input Timing (DREQ Low Level is Detected) .......................................... 776 DACK and TEND Output Timing......................................................................... 776 SIOF_MCLK Input Timing................................................................................... 777 SIOF Transmission/Reception Timing (Master Mode 1, Falling Edge Sampling).............................................................. 778 SIOF Transmission/Reception Timing (Master Mode 1, Rising Edge Sampling) .............................................................. 778 SIOF Transmission/Reception Timing (Master Mode 2, Falling Edge Sampling).............................................................. 779 SIOF Transmission/Reception Timing (Master Mode 2, Rising Edge Sampling) .............................................................. 779 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) ................ 780 SIOF Transmission/Reception Timing (SPI Mode, CPHA = 0, SSAST1 and SSAST0 = 01)............................................ 780 SIOF Transmission/Reception Timing (SPI Mode, CPHA = 1, SSAST1 and SSAST0 = 01)............................................ 781 SCIF Input Clock Cycle ........................................................................................ 782 Input/Output Timing in SCIF Synchronous Mode ................................................ 782 USB Clock Timing................................................................................................ 783 USB Transceiver Timing....................................................................................... 784 USB Transceiver Characteristics Testing Circuit (Full-Speed)............................. 784 USB Transceiver Characteristics Testing Circuit (Low-Speed)............................ 784 Bluetooth Module Clock Timing........................................................................... 785 Bluetooth Interface Module Low Power Clock Timing ........................................ 786 Bluetooth Interface (BT) Voice CODEC (STLC7550) Interface Signal Timing ................................................................................................................... 787 Bluetooth Interface (BT) Voice CODEC (MC145483) Interface Signal Timing ................................................................................................................... 787 SPI Interface Signal Timing for Bluetooth Interface (BT) RF .............................. 788 Bluetooth Interface (BT) Receive Data Timing .................................................... 788 Output Load Circuit............................................................................................... 789 Appendix Figure C.1 Package Dimensions (TBP-208A)............................................................................ 797 Rev. 1.00, 02/04, page xxxi of xxxviii Rev. 1.00, 02/04, page xxxii of xxxviii Tables Section 1 Overview Table 1.1 SH7660 Features....................................................................................................... 2 Table 1.2 Pin Functions and Initial Values ............................................................................. 10 Table 1.3 Pin Functions .......................................................................................................... 21 Section 2 CPU Table 2.1 Register Initial Values............................................................................................. 36 Table 2.2 Addressing Modes and Effective Addresses........................................................... 49 Table 2.3 Instruction Formats ................................................................................................. 53 Table 2.4 CPU Instruction Types............................................................................................ 56 Table 2.5 Data Transfer Instructions....................................................................................... 60 Table 2.6 Arithmetic Operation Instructions .......................................................................... 62 Table 2.7 Logic Operation Instructions .................................................................................. 64 Table 2.8 Shift Instructions..................................................................................................... 65 Table 2.9 Branch Instructions ................................................................................................. 66 Table 2.10 System Control Instructions.................................................................................... 67 Table 2.11 Operation Code Map............................................................................................... 70 Section 3 DSP Operating Unit Table 3.1 Virtual Address Space............................................................................................. 75 Table 3.2 Operation of SR Bits in Each Processing Mode ..................................................... 79 Table 3.3 RS and RE Setting Rule.......................................................................................... 85 Table 3.4 Repeat Control Instructions .................................................................................... 85 Table 3.5 Repeat Control Macros ........................................................................................... 86 Table 3.6 DSP Mode Extended System Control Instructions ................................................. 87 Table 3.7 PC Value during Repeat Control (When RC[11:0] 2) ......................................... 90 Table 3.8 Extended Repeat Control Instructions .................................................................... 94 Table 3.9 Extended System Control Instructions in DSP Mode ............................................. 99 Table 3.10 Overview of Data Transfer Instructions................................................................ 101 Table 3.11 Modulo Addressing Control Instructions.............................................................. 103 Table 3.12 Double Data Transfer Instruction Formats ........................................................... 105 Table 3.13 Single Data Transfer Instruction Formats ............................................................. 106 Table 3.14 Destination Register in DSP Instructions.............................................................. 108 Table 3.15 Source Register in DSP Operations ...................................................................... 108 Table 3.16 DSR Register Bits................................................................................................. 109 Table 3.17 DSP Instruction Formats....................................................................................... 112 Table 3.18 Correspondence between DSP Instruction Operands and Registers ..................... 112 Table 3.19 DC Bit Update Definitions.................................................................................... 114 Table 3.20 Examples of NOPX and NOPY Instruction Codes............................................... 116 Table 3.21 Variation of ALU Fixed-Point Operations............................................................ 119 Table 3.22 Correspondence between Operands and Registers................................................ 119 Rev. 1.00, 02/04, page xxxiii of xxxviii Table 3.23 Table 3.24 Table 3.25 Table 3.26 Table 3.27 Table 3.28 Table 3.29 Table 3.30 Table 3.31 Table 3.32 Table 3.33 Table 3.34 Table 3.35 Table 3.36 Table 3.37 Table 3.38 Table 3.39 Table 3.40 Variation of ALU Integer Operations ................................................................... 124 Variation of ALU Logical Operations .................................................................. 125 Variation of Fixed-Point Multiply Operation ....................................................... 127 Correspondence between Operands and Registers ............................................... 127 Variation of Shift Operations................................................................................ 129 Operation Definition of PDMSB .......................................................................... 134 Variation of PDMSB Operation............................................................................ 134 Variation of Rounding Operation ......................................................................... 136 Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 136 Definition of Overflow Protection for Integer Arithmetic Operations.................. 137 Variation of Local Data Move Operations............................................................ 137 Correspondence between Operands and Registers ............................................... 138 DSP Mode Extended System Control Instructions ............................................... 139 Double Data Transfer Instruction ......................................................................... 141 Single Data Transfer Instructions ......................................................................... 142 Correspondence between DSP Data Transfer Operands and Registers ................ 143 DSP Data Operation Instructions.......................................................................... 144 Operation Code Map............................................................................................. 150 Section 4 Exception Handling Table 4.1 Exception Event Vectors ...................................................................................... 162 Table 4.2 Instruction Positions regarding a repeat loop and Restriction Types.................... 169 Table 4.3 SPC Value when a Re-Execution Type Exception Occurs in Repeat Control...... 171 Table 4.4 Restrictions of Exception Acceptance in the Repeat Loop ................................... 173 Table 4.5 Instruction Where a Specific Exception Occurs When a Memory Access Exception Occurs in Repeat Control (SR.RC[11:0] 1) ...................................... 174 Section 5 Cache Table 5.1 LRU and Way Replacement (when Cache Locking Mechanism is Disabled)...... 178 Table 5.2 Way Replacement when a PREF Instruction Misses the Cache ........................... 181 Table 5.3 Way Replacement when Instructions other than the PREF Instruction Miss the Cache .................................................................................................................... 182 Table 5.4 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)................ 182 Table 5.5 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)................ 182 Table 5.6 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)................ 182 Section 6 X/Y Memory Table 6.1 X/Y Memory Virtual Addresses ........................................................................... 191 Table 6.2 Cache Settings ...................................................................................................... 194 Section 7 U Memory Table 7.1 U Memory Virtual Addresses ............................................................................... 195 Table 7.2 Cache Settings ...................................................................................................... 197 Rev. 1.00, 02/04, page xxxiv of xxxviii Section 8 Interrupt Controller (INTC) Table 8.1 Pin Configuration.................................................................................................. 201 Table 8.2 Interrupt Sources and IPRA to IPRH.................................................................... 203 Table 8.3 Correspondence between Interrupt Sources and IMR0 to IMR9/IMCR0 to IMCR9.............................................................................................................. 209 Table 8.4 Interrupt Exception Handling Sources and Priority .............................................. 213 Section 9 Bus State Controller (BSC) Table 9.1 Pin Configuration.................................................................................................. 220 Table 9.2 Address Space Map of External Address Space ................................................... 223 Table 9.3 16-Bit External Device/Big Endian Access and Data Alignment ......................... 248 Table 9.4 8-Bit External Device/Big Endian Access and Data Alignment........................... 249 Table 9.5 16-Bit External Device/Little Endian Access and Data Alignment ...................... 249 Table 9.6 8-Bit External Device/Little Endian Access and Data Alignment ........................ 250 Table 9.7 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (1)-1................................... 261 Table 9.7 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (1)-2................................... 262 Table 9.8 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (2)-1................................... 263 Table 9.8 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (2)-2................................... 264 Table 9.9 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (3)-1................................... 265 Table 9.9 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (3)-2................................... 266 Table 9.10 Relationship between Access Size and Number of Bursts.................................... 267 Table 9.11 Access Address in SDRAM Mode Register Write ............................................... 283 Table 9.12 Relationship between Data Bus Width, Access Size, and Number of Bursts ....... 285 Section 10 Direct Memory Access Controller (DMAC) Table 10.1 Pin Configuration.................................................................................................. 299 Table 10.2 DMARS Settings .................................................................................................. 312 Table 10.3 Selecting External Request Modes with the RS Bits ............................................ 315 Table 10.4 Selecting External Request Detection with DL, DS Bits ...................................... 316 Table 10.5 Selecting External Request Detection with DO Bit .............................................. 316 Table 10.6 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits............................................................................................................ 317 Table 10.7 Supported DMA Transfers.................................................................................... 321 Table 10.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 327 Section 11 Clock Pulse Generator (CPG) Table 11.1 Clock Pulse Generator Pins Configuration ........................................................... 336 Table 11.2 Clock Operating Modes ........................................................................................ 337 Rev. 1.00, 02/04, page xxxv of xxxviii Table 11.3 Possible Combination of Clock Modes and FRQCR Values................................ 338 Section 13 Power-Down Modes Table 13.1 States of Power-Down Modes .............................................................................. 356 Table 13.2 Pin Configuration.................................................................................................. 358 Table 13.3 Register States in Software Standby Mode........................................................... 367 Section 14 Timer Unit (TMU) Table 14.1 TMU Interrupt Sources......................................................................................... 380 Section 15 Serial I/O with FIFO (SIOF) Table 15.1 Pin Configuration.................................................................................................. 383 Table 15.2 Operation in Each Transfer Mode......................................................................... 386 Table 15.3 SIOF Serial Clock Frequency ............................................................................... 410 Table 15.4 Serial Transfer Modes........................................................................................... 412 Table 15.5 Frame Length........................................................................................................ 413 Table 15.6 Audio Mode Specification for Transmit Data....................................................... 414 Table 15.7 Audio Mode Specification for Receive Data ........................................................ 415 Table 15.8 The Number of Channels in Control Data Setting ................................................ 415 Table 15.9 Conditions to Issue Transmit Request .................................................................. 417 Table 15.10 Conditions to Issue Receive Request ................................................................ 418 Table 15.11 Transmit and Receive Reset ............................................................................. 423 Table 15.12 SIOF Interrupt Sources ..................................................................................... 424 Table 15.13 States of Transmit and Receive Operations in SPI Mode ................................. 431 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.1 Pin Configuration.................................................................................................. 438 Table 16.2 SCSMR Settings for Serial Transfer Format Selection......................................... 463 Table 16.3 Serial Transfer Formats ........................................................................................ 464 Table 16.4 SCIF Interrupt Sources ......................................................................................... 486 Section 17 Boot Function (BOOT) Table 17.1 Input/Output Pin ................................................................................................... 493 Table 17.2 Clock frequency and data transfer rate of SCIF when boot function is used ........ 498 Section 18 USB Pin Multiplex Controller (USBPM) Table 18.1 Pin Configuration (Analog Transceiver Signal) ................................................... 501 Table 18.2 Pin Configuration (Power Control signal) ............................................................ 501 Table 18.3 Pin Configuration (Clock Control signal)............................................................. 501 Section 19 USB Host Controller (USBH) Table 19.1 Pin Configuration.................................................................................................. 510 Section 20 USB Function Controller (USBF) Table 20.1 Pin Configuration.................................................................................................. 549 Table 20.2 Restrictions of Settable Values ............................................................................. 581 Table 20.3 Example of Endpoint Configuration (1) ............................................................... 581 Rev. 1.00, 02/04, page xxxvi of xxxviii Table 20.4 Table 20.5 Table 20.6 Table 20.7 Example of Setting of Endpoint Configuration Information (1)........................... 583 Example of Endpoint Configuration (2) ............................................................... 584 Example of Setting of Endpoint Configuration Information (2)........................... 585 Command Decoding on Application Side............................................................. 601 Section 21 Bluetooth Interface (BT) Table 21.1 Input/Output Pins.................................................................................................. 613 Table 21.2 Settings and Functions .......................................................................................... 618 Section 22 D/A Converter (DAC) Table 22.1 Pin Configuration.................................................................................................. 624 Section 23 I/O Ports Table 23.1 Port A Data Register (PADR) Read/Write Operations ......................................... 628 Table 23.2 Port B Data Register (PBDR) Read/Write Operations.......................................... 630 Table 23.3 Port D Data Register (PDDR) Read/Write Operations ......................................... 632 Table 23.4 Port E Data Register (PEDR) Read/Write Operations .......................................... 634 Table 23.5 Port G Data Register (PGDR) Read/Write Operations ......................................... 636 Table 23.6 Port H Data Register (PHDR) Read/Write Operations ......................................... 638 Section 24 Pin Function Controller (PFC) Table 24.1 Multiplex Pins....................................................................................................... 639 Section 25 User Break Controller Table 25.1 Specifying Break Address Register ...................................................................... 660 Table 25.2 Specifying Break Data Register............................................................................ 662 Table 25.3 Data Access Cycle Addresses and Operand Size Comparison Conditions ........... 673 Section 26 User Debugging Interface (H-UDI) Table 26.1 Pin Configuration.................................................................................................. 684 Table 26.2 JTAG Commands ................................................................................................. 686 Table 26.3 Correspondence between Pins of SH7660 and Boundary Scan Register.............. 687 Table 26.4 Reset Configuration .............................................................................................. 693 Section 28 Electrical Characteristics Table 28.1 Absolute Maximum Ratings ................................................................................. 729 Table 28.2 DC Characteristics (1) Common Items ................................................................. 731 Table 28.2 DC Characteristics (2-a) Except DAC and USB Related Pins.............................. 732 Table 28.2 DC Characteristics (2-b) USB Related Pins*........................................................ 733 Table 28.2 DC Characteristics (2-c) USB Transceiver Related Pins* .................................... 734 Table 28.3 Permissible Output Current Values....................................................................... 734 Table 28.4 Operating Frequencies .......................................................................................... 735 Table 28.5 Clock Timing ........................................................................................................ 736 Table 28.6 Control Signal Timing .......................................................................................... 740 Table 28.7 Bus Timing ........................................................................................................... 743 Table 28.8 Peripheral Module Signal Timing......................................................................... 776 Table 28.9 SIOF Module Signal Timing ................................................................................ 777 Rev. 1.00, 02/04, page xxxvii of xxxviii Table 28.10 Table 28.11 Table 28.12 Table 28.13 Table 28.14 Table 28.15 Table 28.16 Table 28.17 Table 28.18 Table 28.19 Table 28.20 Table 28.21 Table 28.22 SCIF Module Signal Timing............................................................................. 781 USB Module Clock Timing .............................................................................. 782 USB Module Clock Timing .............................................................................. 782 USB Transceiver Timing (Full-Speed) ............................................................. 783 USB Transceiver Timing (Low-Speed) ............................................................ 783 Bluetooth Interface Module Clock Timing....................................................... 785 Bluetooth Interface Module Clock Timing....................................................... 785 Bluetooth Interface Module Low Power Clock Timing ................................... 785 Bluetooth Interface Module Low Power Clock Timing ................................... 786 Bluetooth Interface (BT) Voice CODEC Interface Signal Timing................... 786 SPI Interface Signal Timing for Bluetooth Interface (BT) RF.......................... 787 Receive Data Timing ........................................................................................ 788 D/A Converter Characteristics.......................................................................... 790 Appendix Table A.1 ...................................................................................................................................... 791 Rev. 1.00, 02/04, page xxxviii of xxxviii Section 1 Overview 1.1 SH7660 Features This LSI is a RISC (Reduced Instruction Set Computer) microcomputer that integrates a 32-bit RISC-type SuperH architecture CPU and digital signal processing (DSP) extended function as its core, together with 16-kbyte cache memory, 16-kbyte X/Y memory, and 128-kbyte U memory, as well as peripheral functions required for system configuration such as an interrupt controller. High-speed data transfers can be performed by an on-chip direct memory access controller (DMAC) and a direct connection to various memories can be performed by the external memory access support function. Moreover, this LSI also includes powerful peripheral functions that are essential to system configuration, such as the USB (host/function), high-speed (921 kbits/s) asynchronous serial interface circuit, voice/audio CODEC serial interface circuit, and D/A converter. This LSI also supports the BluetoothTM interface as one of peripheral functions and provides the Bluetooth protocol stack function including firmware up to the HCI layer as a standard function. Moreover, this LSI has extra processing power to perform the upper protocol stack and various application profiles to implement the whole Bluetooth baseband functions. The API is also provided to handle the protocol stack function below the HCI layer so that this Bluetooth interface can easily be handled like the conventional peripheral functions. This Bluetooth interface can be connected directly to the RF chip such as the HD157100NP or HD157102NP (manufactured by Renesas Technology). Note: Bluetooth is a registered trademark of Bluetooth SIG, Inc., USA. Renesas Technology uses Bluetooth by entering into licensing agreements. The features of this LSI are listed in table 1.1. Rev. 1.00, 02/04, page 1 of 804 Table 1.1 Item CPU SH7660 Features Features * * * * Renesas Technology Original SuperH architecture Compatible with SH-1, SH-2 and SH-3 at object code level 32-bit internal data bus Supports various registers Sixteen 32-bit general registers (including eight 32-bit bank registers) Five 32-bit control registers Four 32-bit system registers * Supports RISC-type instruction set Instruction length: 16-bit fixed length for improved code efficiency Load/store architecture Delayed branch instructions Instruction set suitable for C language * * * * Supports barrel shift instructions and multiply-and-accumulate instructions Instruction execution time: One instruction/cycle for basic instructions Logical address space: 4 Gbytes Five-stage pipeline Mixture of 16-bit and 32-bit instructions 32-/40-bit internal data bus Employs multiplier, ALU, and barrel shifter 16-bit x 16-bit 32-bit one cycle multiplier Employs large-capacity DSP data register files Six 32-bit data registers * Two 40-bit data registers Extended harvard architecture for DSP data bus Two data buses * * * * * * One instruction bus Maximum four parallel operations: ALU, multiply, and two load or store Two addressing units to generate addresses for two memory access DSP data addressing modes: Increment and indexing (with or without modulo addressing) Zero-overhead repeat loop control Conditional execution instructions User DSP mode and privileged DSP mode DSP unit * * * * * Rev. 1.00, 02/04, page 2 of 804 Item Cache memory Features * * * * * 16-kbyte cache, unified of instructions and data 256 entries, 4-way set associative, and 16-byte block length Write-back, write-through, and LRU replacement algorithm 1-stage write-back buffer Maximum 2 ways can be protected Three independent read/write ports 8-/16-/32-bit access from the CPU Maximum two 16-bit accesses from the DSP 8-/16-/32-bit access from the DMAC 8-/32-bit access from the USBH * * * A total of 16 kbytes (4 kbytes x 4) No interrupt requests No DMA transfer requests (accessible as a transfer source or destination) Two independent read/write ports 8-/16-/32-bit access from the CPU 16-/32-bit access from the DSP 8-/16-/32-bit access from the DMAC 8-/32-bit access from the USBH * * * As large as 128-kbyte memory No interrupt requests No DMA transfer requests (accessible as a transfer source or destination) Five external interrupt pins (NMI, IRQ4 to IRQ2, IRQ0) One interrupt request output pin (IRQOUT) On-chip peripheral interrupt: Priority is independently selected for each module Selection of falling/rising edge sense and high/low level sense X/Y memory * U memory * Interrupt * controller (INTC) * * * Rev. 1.00, 02/04, page 3 of 804 Item Bus state controller (BSC) Features * * Physical address space is divided into three areas: Area 0, area 3, area 4; each a maximum of 16 Mbytes The following features are settable for each area: Bus size (8 or 16 bits); The supported bus size may differ for each area Number of access wait cycles (Numbers of wait-state cycles during reading and writing are independently selectable for some areas.) Setting of idle wait cycles (for the same area or different area) Specifying the memory to be connected to each area allows direct connection to SRAM, SRAM with byte selection, SDRAM, or burst ROM Outputs chip select signals (CS0, CS3, CS4) for corresponding area (Can be turned by the program CSn assert/negate timing.) * * * SDRAM refresh function Auto-refresh and self-refresh modes SDRAM burst access function Big endian or little endian can be set. Four channels (for one channel, external requests can be accepted) Burst mode and cycle-steal mode Intermittent cycle-steal mode Clocks can be input from an external pin (EXTAL or CKIO) or crystal unit Three clocks generated: Internal clock: 120 MHz Bus clock: 60 MHz Peripheral clock: 30 MHz * Supports power-down modes: Software standby mode Sleep mode Module standby mode * * Three clock modes (PLL1 and PLL2 multiplication ratio, clock, and crystal unit can be selected) One frequency-divider mode One-channel watchdog timer Watchdog timer mode and interval timer mode can be selected In interval timer mode, interrupts can be generated Direct memory * access controller * (DMAC) * Clock pulse generator (CPG) * * Watchdog timer (WDT) * * * Rev. 1.00, 02/04, page 4 of 804 Item Features Three channels of 32-bit timer Four input clocks can be selected for each channel counter 32-bit down counter of the auto-reload type On-chip prescaling by P Interrupt requests: Interrupt requests are generated by underflow of 32-bit down counter One channel 16-stage 32-bit FIFOs (independent for reception and transmission) 8-/16-/16-bit stereo-audio input/output supported Synchronization method: Frame synchronized pulse and switching between left and right channels Supports a CODEC control data interface Can be connected to linear, audio, A-Law, or -Law CODEC chip Supports master and slave modes Sampling rate clock can be generated from P or be input from external pin (max. 48 kHz) On-chip prescaler from P Module standby function Capable of interrupt requests and DMAC requests Two channels Supports asynchronous mode and clocked synchronous mode 64-byte transmit/receive FIFOs High-speed UART Supports CTS/RTS On-chip prescaler from P Capable of interrupt requests and DMAC requests Normal mode or boot mode at a power-on reset Automatic fetching of initial write program from SCIF0 Downloading of program to on-chip memory (U memory) * Auto-running function of downloaded program * * * * Timer unit (TMU) * Serial I/O with FIFO (SIOF) * * * * * * * * * * * Serial communication interface with FIFO (SCIF0, SCIF1) * * * * * * * Boot function (BOOT) * * Rev. 1.00, 02/04, page 5 of 804 Item Features Register set conforming to OHCI version 1.0 Conforms to USB 1.1 Supports 127 endpoints Supports control/bulk/interrupt/isochronous modes Bus master controller One-port USB transceiver (sharing with USB function controller) Selectable module input clock: 48-MHz external input or on-chip DLL Capable of issuing interrupt requests Conforms to USB 1.1 One-port USB transceiver (sharing with USB host controller) Supports six endpoints, the number of endpoints is selectable Supports isochronous, totally 2 endpoints Supports control (endpoint 0)/bulk (2 endpoints)/interrupt (1 endpoint) The USB standard commands are supported, and class and vendor commands are handled by firmware On-chip FIFO buffer for endpoints (bulk, isochronous: 128 bytes/endpoint) Selectable module input clock: 48-MHz external input or on-chip DLL Capable of issuing interrupt requests and DMAC requests Supports Bluetooth version 1.1 Supports direct interface with the HD157100NP or HD157102NP (Renesas) RF IC Supports direct interface with the STLC7550 or MC145483 voice CODEC IC Supports four voice CODEC formats (A-law/-law/CVSD/linear PCM) Supports ACL and SCO links (SCI over HCI possible) Frequency hopping within 79 channels as a form of spread-spectrum modulation Use of the 32.768-kHz clock for RTC (Realtime Clock) as the clock for power-down mode Selectable clock for power-down mode: Crystal oscillator mode or external direct input mode Supports three power-down modes: Hold/sniff/park Two channels of 8 bit D/A converters Output range: 0 to AVcc Bitwise selection of input/output USB host * controller (USBH) * * * * * * * USB function * controller (USBF) * * * * * * * * Bluetooth interface (BT) * * * * * * * * * D/A converter (DAC) I/O port/pin function controller (PFC) * * * Rev. 1.00, 02/04, page 6 of 804 Item User break controller (UBC) Features * * * Address, data value, access type, and data size are available for setting as break conditions Supports the sequential break function Two break channels Supports the E10A emulator Realtime branch trace 1-kbyte of on-chip RAM for executing the high-speed emulation program 208-pin BGA (pin pitch: 0.65 mm) I/O: 3.0 to 3.6 V (some parts: 2.7 to 3.0 V) Internal: on-chip regulator provides, or 1.4 to 1.6 V external power supply can be selected. -40C to +85C (except USB) -20C to +85C (for USB only) User debugging * interface (H-UDI) * * Package Power-supply voltage * * * * * Operating temperature range Notes: 1. This LSI does not support the MMU and TLB functions, therefore, the LDTLB instruction provided by the SH-3 CPU is not available. 2. Since the on-chip AUD and ASERAM modules are used for debugging, related descriptions are omitted in this manual. For details, refer to the user's manual related to development tools. Rev. 1.00, 02/04, page 7 of 804 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the SH7660. Y bus XYMEM X bus XYCNT SH3 CPU DSP TMU L bus UMC UMEM BT SIOF SCIF 0 Peripheral bus I bus CCN CACHE UBC AUD SCIF 1 USBF CPG/WDT BOOT BSC INTC DMAC DAC USBH H-UDI ASERAM External bus interface I/O port (PFC) Legend: ASERAM : AUD : BOOT : BSC : BT : CACHE : CCN : CPG/WDT : CPU : DAC : DMAC : DSP: ASE memory Advanced user debugger Boot loader Bus state controller Bluetooth interface Cache memory Cache memory controller Clock pulse generator/watchdog timer Central processing unit D/A converter Direct memory access controller Digital signal processor H-UDI : INTC : PFC : SCIF : SIOF : TMU : UBC : UMC : UMEM : USBH/USBF : XYCNT: XYMEM: User debugging interface Interrupt controller Pin function controller Serial communication interface with FIFO Serial I/O with FIFO 16-bit Timer unit User break controller U memory controller U memory Universal serial bus host/universal serial bus function X/Y memory controller X/Y memory Note: Since the on-chip AUD and ASERAM modules are used for debugging, related descriptions are omitted in this manual. For details, refer to the user's manual related to development tools. Figure 1.1 Block Diagram of SH7660 Rev. 1.00, 02/04, page 8 of 804 1.3 Pin Assignment Figure 1.2 shows the pin assignment. Table 1.2 shows pin functions and initial values. 1 A B C D E F G H J K L M N P R T U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SH7660 BGA-208 (Top View) Figure 1.2 Pin Assignment Rev. 1.00, 02/04, page 9 of 804 Table 1.2 Pin No. A1 Pin Functions and Initial Values Pin Name PTH4/SCIF1_CTS Description Port H/CTS input for SCIF1 Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. A2 A3 NMI PTB1/IRQ2 Nonmaskable interrupt request When this pin is not used, it should be fixed to high. Port B/external interrupt request input Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. A4 A5 A6 A7 A8 A9 A10 RTCSEL0 NC NC AVss (DAC) XTAL EXTAL EXTAL2 Test pin This pin must be fixed to low. Reserved This pin should be open. Reserved This pin should be open. Analog power supply for D/A converter (DAC) (0 V) Crystal unit pin External clock input/crystal unit pin External clock input/crystal unit pin for Bluetooth powerdown state When RTCSEL0 = high, this pin enters the non-active state. A11 A12 A13 A14 A15 A16 A17 RDI_TXTRDATA*1 Vss_28 RDI_REFCLK_IN* RCI_SPI_TXRX* USB_N USB_P AVss (USB) 1 1 Transmit/receive data I/O for RF IC The initial state is output. Power supply for I/O pins with RF IC (0 V) Clock input for data I/O with RF IC This pin is always input. SPI serial data I/O with RF IC The initial state is output. D- I/O for on-chip USB transceiver The initial state is Hi-Z. D+ I/O for on-chip USB transceiver The initial state is Hi-Z. Analog power supply for USB transceiver (0 V) Rev. 1.00, 02/04, page 10 of 804 Pin No. B1 B2 B3 Pin Name NC ASEMD0 PTG0/SCIF0_SCK/IRQ3 Description Reserved This pin should be open. ASE mode control input This pin should be fixed to high in the normal state. Port G/clock I/O for SCIF0/external interrupt request input Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. B4 B5 B6 B7 B8 B9 B10 RREF NC Vss (DLL) DA0 Vcc (I/O) Vss XTAL2 Test pin This pin should be pulled-up. Reserved This pin should be open. Power supply for internal regulator (DLL) (0 V) D/A converter (DAC) output (channel 0) Power supply for I/O (3.3 V) Power supply (0 V) Crystal unit pin for Bluetooth power-down state When RTCSEL0 = high, this pin enters the non-active state. B11 B12 B13 B14 B15 B16 B17 C1 RDI_RXBDW_OUT*1 Vcc_28 RCI_SPI_CLK* NC NC NC NC PTH1/SCIF1_TxD 1 Packet control output for RF IC Power supply for I/O pin with RF IC (2.8 V/3.3 V) SPI interface clock output with RF IC Reserved This pin should be open. Reserved This pin should be open. Reserved This pin should be open. Reserved This pin should be open. Port H/transmit data output for SCIF1 This pin is fixed to input and enters the output Hi-Z state in the initial state. Rev. 1.00, 02/04, page 11 of 804 Pin No. C2 Pin Name PTH2/SCIF1_RxD Description Port H/receive data input for SCIF1 Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. C3 PTH3/SCIF1_RTS Port H/RTS output for SCIF1 Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. C4 PTB0/IRQ0 Port B/external interrupt request input Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 Vss (SREG) VDD (DLL) DA1 Vss NC Vss RDI_CTRL3* Vss_28 RCI_SPI_ENB* AVcc (USB) NC UCLK 1 1 Power supply for internal regulator (sub) (0 V) Power-supply output from internal regulator / power-supply input (DLL) (1.5 V) D/A converter (DAC) output (channel 1) Power supply (0 V) Reserved This pin should be open. Power supply (0 V) Strobe output for enabling RF-IC oscillator Power supply for I/O pin with RF IC (0 V) SPI interface enable output with RF IC Analog power supply for USB transceiver (3.3 V) Reserved This pin should be open. External clock input for USB When initialized, the internal DLL clock is valid and this pin is internally fixed to input. C17 USB_OVR_CRNT/ USB_VBUS Over current detection input for USB/USB-cable connection monitor input Even if this pin is not used, this pin should be driven by an appropriate level. D1 PTG2/SCIF0_RxD Port G/receive data input for SCIF0 Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. Rev. 1.00, 02/04, page 12 of 804 Pin No. D2 Pin Name PTG3/SCIF0_ RTS Description Port G/RTS output for SCIF0 Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. D3 PTG4/SCIF0_ CTS Port G/CTS input for SCIF0 Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. D4 PTH0/SCIF1_SCK/IRQ4 Port H/clock I/O for SCIF1/external interrupt request input Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Vcc (SREG) Vcc (DLL) Vss AVcc (DAC) Vcc (I/O) NC RDI_CTRL4*1 Vcc_28 RESETP USB_PWR_EN/ USB_PULLUP Vcc (PLL) VDD (PLL) Vss (PLL) PTA6/SIOF_SS2 Power supply for internal regulator (sub) (3.3 V) Power supply for internal regulator (DLL) (3.3 V) Power supply (0 V) Analog power supply for D/A converter (DAC) (3.3 V) Power supply for I/O (3.3 V) Reserved This pin should be open. Reset control for RF IC and power-down control output Power supply for I/O pin with RF IC (2.8 V/3.3 V) Power-on reset input USB power-supply application enable control output/pullup control output for USB The initial state is low-level output. Power supply for internal regulator (PLL1/PLL2) (3.3 V) Power supply output from internal regulator/powersupply input (PLL1/PLL2) (1.5 V) Power supply for internal regulator (PLL1/PLL2) (0 V) Port A/SPI mode slave device select for SIOF Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. D15 D16 D17 E1 E2 PTG1/SCIF0_TxD Port G/transmit data output for SCIF0 This pin is fixed to input and enters the output Hi-Z state in the initial state. E3 Vss Power supply (0 V) Rev. 1.00, 02/04, page 13 of 804 Pin No. E4 E14 E15 E16 E17 F1 Pin Name Vcc (I/O) Vcc (internal) VDD Vss CKIO PTA5/SIOF_SS1 Description Power supply for I/O (3.3 V) Power supply for internal regulator (3.3 V) Power-supply output from internal regulator/powersupply input (1.5 V) Power supply (0 V) System clock I/O Port A/SPI mode slave device select for SIOF Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. F2 F3 F4 F14 F15 F16 F17 G1 Vss VDD Vcc (internal) Vcc (I/O) Vss NC MD5 PTA2/SIOF_RXD (MISO) Power supply (0 V) Power-supply output from internal regulator/powersupply input (1.5 V) Power supply for internal regulator (3.3 V) Power supply for I/O (3.3 V) Power supply (0 V) Reserved This pin should be open. Endian set input Port A/receive data input for SIOF Though this pin is fixed to input and enters the output HiZ state in the initial state, the internal pull-up MOS is turned on. G2 PTA3/SIOF_SYNC (SIOF_SS0) Port A/frame synchronization signal output for SIOF (SPI mode slave device select for SIOF) Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. G3 PTA4/SIOF_SCK (SCK) Port A/serial clock I/O for SIOF Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. G4 G14 G15 NC MD2 MD1 Reserved This pin should be open. Clock mode set input Clock mode set input Rev. 1.00, 02/04, page 14 of 804 Pin No. G16 Pin Name PTE6/RDI_CTRL2* /IRQOUT 1 Description Port E/external power amplifier control output for RF IC /IRQOUT Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. G17 PTE0 2 /VCI_CODEC_PWRDWN* /TEND Port E/power-down control output for voice CODEC IC /DMA transfer end flag output Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. Built-in regulator selection pin. The built-in power supply regulator is used when this pin is high, external power input is used when this pin is low for the internal power (VDD=1.5V). Reserved This pin should be open. Port A/master clock input for SIOF Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. H1 TEST_REG H2 H3 NC PTA0/SIOF_MCLK H4 PTA1/SIOF_TXD (MOSI) Port A/transmit data output for SIOF Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. H14 H15 H16 H17 Vcc (internal) VDD Vss 2 Power supply for internal regulator (3.3 V) Power-supply output from internal regulator/powersupply input (1.5 V) Power supply (0 V) PTE1/VCI_SCO_TX* /DACK Port E/transmit data input from voice CODEC IC /DMA transfer request accept Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. J1 TRST H-UDI reset input This pin is internally pulled up. When a boundary scan function is not used in normal mode (ASEMD0 = high), this pin should be fixed to low. J2 J3 ASEBRKAK TDO ASE break acknowledge output H-UDI data output Rev. 1.00, 02/04, page 15 of 804 Pin No. J4 J14 J15 Pin Name TEST Vcc (I/O) PTE2/VCI_SCO_RX* /DREQ 2 Description Test input This pin should always be fixed to high. Power supply for I/O (3.3 V) Port E/receive data output to voice CODEC IC /DMA transfer request input Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. J16 PTE4 /VCI_SCO_SYNC_OUT*2 /BREQ PTE3 /VCI_SCO_CLK_OUT*2 /BACK TDI TCK Vss Vcc (I/O) AUDATA3 AUDSYNC PTE5/VCI_HWC*2 Port E/frame synchronization signal output for voice CODEC IC/bus mastership request input The bus mastership request input is valid in the initial state. Port E/clock output for voice CODEC IC/bus release acknowledge output The bus release acknowledge output is valid in the initial state. H-UDI test data input This pin is internally pulled up. H-UDI clock input This pin is internally pulled up. Power supply (0 V) Power supply for I/O (3.3 V) AUD data bus (bit 3) output AUD synchronization signal output Port E/operating mode select output for voice CODEC IC Though this pin is fixed to input and enters output Hi-Z state in the initial state, the internal pull-up MOS is turned on. J17 K1 K2 K3 K4 K14 K15 K16 K17 L1 L2 L3 L4 L14 Vss TMS Vss VDD Vcc (internal) Vcc (I/O) Power supply (0 V) H-UDI test mode switch This pin is internally pulled up. Power supply (0 V) Power-supply output from internal regulator/Powersupply input (1.5 V) Power supply for internal regulator (3.3 V) Power supply for I/O (3.3 V) Rev. 1.00, 02/04, page 16 of 804 Pin No. L15 L16 L17 M1 M2 M3 M4 M14 Pin Name Vss AUDATA1 AUDATA2 NC BOOT_E CS0 CS3 PTB7/BS Description Power supply (0 V) AUD data bus (bit 1) output AUD data bus (bit 2) output Reserved This pin should be open. Boot mode enable control input This pin is internally pulled up. Chip select 0 signal output Chip select 3 signal output Port B/bus cycle start signal output The bus cycle start signal output is valid in the initial state. M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 RD AUDCK AUDATA0 CS4 D0 D1 D2 Vcc (internal) VDD Vss PTB6/REFOUT Read strobe signal output AUD clock output AUD data bus (bit 0) output Chip select 4 signal output Data bus (bit 0) Data bus (bit 1) Data bus (bit 2) Power supply for internal regulator (3.3 V) Power-supply output from internal regulator/Powersupply input (1.5 V) Power supply (0 V) Port B/bus release request output The bus release request output is valid in the initial state. P1 P2 P3 P4 P5 P6 P7 P8 P9 D3 D4 Vcc (I/O) D5 D13 Vcc (I/O) A3 Vcc (I/O) A8 Data bus (bit 3) Data bus (bit 4) Power supply for I/O (3.3 V) Data bus (bit 5) Data bus (bit 13) Power supply for I/O (3.3 V) Address bus (bit 3) Power supply for I/O (3.3 V) Address bus (bit 8) Rev. 1.00, 02/04, page 17 of 804 Pin No. P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 Pin Name Vcc (I/O) A15 Vcc (I/O) PTD3/A21 PTB4/RAS Vcc (I/O) Vss WAIT Vss REG_PD_MAIN Description Power supply for I/O (3.3 V) Address bus (bit 15) Power supply for I/O (3.3 V) Port D/address bus (bit 21) The A21 output is valid in the initial state. Port B/RAS (SDRAM) output The RAS output is valid in the initial state. Power supply for I/O (3.3 V) Power supply (0 V) Hardware wait request This pin is internally pulled up. Power supply (0 V) This pin should be fixed to high when the external power supply is used for the internal power (VDD=1.5V). This pin should be open when the internal power supply regulator is used. Data bus (bit 10) Power supply for I/O (3.3 V) Data bus (bit 14) Power supply (0 V) Address bus (bit 4) Power supply (0 V) Address bus (bit 11) This pin should be fixed to high when the external power supply is used for the internal power (VDD=1.5V). This pin should be open when the internal power supply regulator is used. Address bus (bit 14) Address bus (bit 18) Port D/address bus (bit 20) The A20 output is valid in the initial state. Power supply for I/O (3.3 V) Port B/clock enable (SDRAM) output The CKE output is valid in the initial state. D7 to D0 select signal/DQM (SDRAM) output D15 to D8 select signal/DQM (SDRAM) output R3 R4 R5 R6 R7 R8 R9 R10 D10 Vcc (I/O) D14 Vss A4 Vss A11 REG_PD_BGR R11 R12 R13 R14 R15 R16 R17 A14 A18 PTD2/A20 Vcc (I/O) PTB2/CKE WE0/DQM0 WE1/DQM1 Rev. 1.00, 02/04, page 18 of 804 Pin No. T1 T2 T3 T4 T5 T6 T7 T8 Pin Name D6 D7 NC D11 D15 A1 A5 REG_PD_VREF Description Data bus (bit 6) Data bus (bit 7) Reserved This pin should be open. Data bus (bit 11) Data bus (bit 15) Address bus (bit 1) Address bus (bit 5) This pin should be fixed to high when the external power supply is used for the internal power (VDD=1.5V). This pin should be open when the internal power supply regulator is used. Address bus (bit 9) Reserved This pin should be open. Address bus (bit 13) Address bus (bit 17) Port D/address bus (bit 19) The A19 output is valid in the initial state. Port D/address bus (bit 23) The A23 output is valid in the initial state. Port B/read/write output The read/write output is valid in the initial state. Test pin This pin should be connected to Vss. Reserved This pin should be open. Data bus (bit 8) Data bus (bit 9) Power supply (0 V) Data bus (bit 12) Port D/address bus (bit 0) The A0 output is valid in the initial state. Address bus (bit 2) Address bus (bit 6) T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 A9 NC A13 A17 PTD1/A19 PTD5/A23 PTB5/RD/WR VBB NC D8 D9 Vss D12 PTD0/A0 A2 A6 Rev. 1.00, 02/04, page 19 of 804 Pin No. U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Pin Name A7 A10 A12 Vss A16 Vss PTD4/A22 Vss PTB3/CAS VBBENB Description Address bus (bit 7) Address bus (bit 10) Address bus (bit 12) Power supply (0 V) Address bus (bit 16) Power supply (0 V) Port D/address bus (bit 22) The A22 output is valid in the initial state. Power supply (0 V) Port B/CAS (SDRAM) output The CAS output is valid in the initial state. Test pin This pin should be connected to Vss. Notes: 1. These pins are connected to the RF IC. For details on the connection, refer to section 21, Bluetooth Interface (BT). 2. These pins are connected to the voice CODEC IC. For details on the connection, refer to section 21, Bluetooth Interface (BT). Rev. 1.00, 02/04, page 20 of 804 1.4 Pin Functions Table 1.3 lists the pin functions. Table 1.3 Pin Functions Symbol VDD* 1 Classification Power supply I/O Output/ Input Name Power supply Function Power output of the built-in regulator, or power input from an external power supply (for internal circuit). A pin function is specified with the TEST_REG pin. Power supply for internal regulator. Connect all Vcc pins to the system power supply. There will be no operation if any pins are open. Power supply for I/O pins. Connect all Vcc pins to the system power supply. There will be no operation if any pins are open. Ground pin. Connect all Vss pins to the system power supply (0 V). There will be no operation if any pins are open. Built-in regulator selection pin. The built-in power supply regulator is used when this pin is high, external power input is used when this pin is low for the internal power (VDD=1.5V). The level of this pin should not be changed during operation Built-in regulator control. This pin should be fixed to high when the external power supply is used for the internal power (VDD=1.5V). This pin should be open when the built-in power supply regulator is used. Built-in regulator control. This pin should be fixed to high when the external power supply is used for the internal power (VDD=1.5V). This pin should be open when the built-in power supply regulator is used. Vcc (internal) Input Power supply Vcc (I/O) Input Power supply Vss Input Ground TEST_REG Input Power supply selection REG_PD_MAIN Input/NC Power supply control REG_PD_ BGR Input/NC Power supply control Rev. 1.00, 02/04, page 21 of 804 Classification Power supply Symbol I/O Name Function Built-in regulator control. This pin should be fixed to high when the external power supply is used for the internal power (VDD=1.5V). This pin should be open when the built-in power supply regulator is used. Power supply for on-chip PLL1/PLL2 oscillator Power output of the built-in regulator for PLL1/PLL2 oscillator, or power input from an external power supply. A pin function is specified with the TEST_REG pin. Ground pin for on-chip PLL1/PLL2 oscillator For connection to the crystal resonator. Also, this pin can input external clocks. For connection to the crystal resonator and connection of the input of external clocks, refer to section 11, Clock Pulse Generator (CPG). REG_PD_VREF Input/NC Power supply control Clock Vcc (PLL) VDD (PLL)*1 Input Output/ Input PLL1/PLL2 power supply Power supply Vss (PLL) EXTAL Input Input PLL1/PLL2 ground Crystal input (clock input) XTAL Output Crystal output For connection to the crystal resonator. For connection to the crystal resonator and connection of the input of external clocks, refer to section 11, Clock Pulse Generator (CPG). CKIO I/O Clock I/O Supplies system clocks to external devices or used for external clock input. Sets the operating mode. The level on these pins should not be changed during operation. MD2 and MD1 set the clock mode and MD5 sets the endian. Operating mode MD5, control MD2, MD1 Input Mode control Rev. 1.00, 02/04, page 22 of 804 Classification System control Symbol RESETP BOOT_E I/O Input Input Name Power-on reset Boot control Function When this pin goes low, the system enters the power-on reset state. Boot mode enable control input. When this pin goes low at a poweron reset, the system enters the boot mode and runs the boot loader after reset processing. When this pin goes high at a power-on reset, the normal reset sequence is executed. BREQ Input Bus mastership This pin is set to low when an request external device requests the bus mastership release. Bus mastership Indicates that bus mastership is request externally released. A device which acknowledge has output the BREQ signal knows that the bus mastership is acquired by receiving the BACK signal. Nonmaskable Nonmaskable interrupt request pin. interrupt request This pin should be fixed to high when not in use. Interrupt requests 4 to 2, 0 Maskable interrupt request pins. Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. BACK Output Interrupts NMI Input IRQ4 to IRQ2, IRQ0 Input IRQOUT Address bus Data bus Bus control A23 to A0 D15 to D0 Output Output I/O Bus mastership Notifies an external device of request interrupt source occurrence. Address bus Data bus Chip select 0, 3, 4 Read Read/write Bus start Outputs addresses. 16-bit bidirectional bus Chip select signal for external memory or devices Indicates reading of data from external devices. Read/write signal pin Bus cycle start signal pin CS0, CS3, CS4 Output RD RD/WR BS WE1 Output Output Output Output Write upper bits Indicates that bits 15 to 8 of the data in the external memory or device are being written. Rev. 1.00, 02/04, page 23 of 804 Classification Bus control Symbol WE0 I/O Output Name Function Write lower bits Indicates that bits 7 to 0 of the data in the external memory or device are being written. Data enable Data enable Clock enable DQ mask DQ mask Bus release request Wait CAS signal of SDRAM RAS signal of SDRAM Clock enable signal pin of SDRAM Indicates that bits 15 to 8 of the data in SDRAM are selected. Indicates that bits 7 to 0 of the data in SDRAM are selected. Indicates that a refresh request has occurred during bus mastership release. Inserts a wait cycle into the bus cycles during access to the external space. Input pin for an external DMA transfer request Output pin for external DMA transfer request acceptance Indicates that DMA transfer ends. Transmit data pin Receive data pin Clock I/O pin Master clock input pin CAS RAS CKE DQM1 DQM0 REFOUT Output Output Output Output Output Output WAIT Input Direct memory DREQ access controller (DMAC) DACK Input Output DMA transfer request DMA transfer request acceptance DMA transfer end Transmit data Receive data Serial clock Master clock TEND Serial I/O with FIFO (SIOF) SIOF_TXD (MOSI) SIOF_RXD (MISO) SIOF_SCK (SCK) SIOF_MCLK SIOF_SYNC (SIOF_SS0) Output Output Input I/O Input I/O Frame Frame synchronization signal pin synchronization (In SPI mode, selects the slave signal device 0.) (slave device 0 select) Slave device 1 select Slave device 2 select In SPI mode, selects the slave device 1. In SPI mode, selects the slave device 2. SIOF_SS1 SIOF_SS2 Output Output Rev. 1.00, 02/04, page 24 of 804 Classification Serial communication interface with FIFO (SCIF0, SCIF1) Symbol SCIF0_TxD, SCIF1_TxD SCIF0_RxD, SCIF1_RxD SCIF0_SCK, SCIF1_SCK SCIF0_RTS, SCIF1_RTS SCIF0_CTS, SCIF1_CTS I/O Name Function Transmit data pin Receive data pin Clock I/O pin Modem control pin Output Transmit data Input I/O Receive data Serial clock Output Transmit request Input Input Transmit enable Modem control pin USB clock USB clock input pin (48-MHz input) Host: USB power supply application enable control Function: USB pull-up control USB UCLK USB_PWR_EN/ Output USB power USB_PULLUP supply control USB_OVR_CR Input NT/USB_VBUS USB_N USB_P AVcc (USB) I/O I/O Input USB power Host: Over current detection supply detection Function: USB-cable connection monitor pin D- I/O D+ I/O Analog power supply for USB transceiver Analog ground for USB transceiver 3.3-V power supply for USB clock multiplication circuit D- I/O for on-chip USB transceiver D+ I/O for on-chip USB transceiver Analog power supply pin for USB transceiver Analog ground pin for USB transceiver Connect to the system ground (Vss). Power supply pin for the 48-MHz clock multiplication circuit of the USB Connect to the system power supply (Vcc). Power output of the built-in regulator for 48MHz clock frequency multiplier circuit of USB, or power input from an external power supply. A pin function is specified with the TEST_REG pin. AVss (USB) Input Vcc (DLL) Input VDD (DLL)*1 Output/ Power supply Input Vss (DLL) Input Ground for USB Ground pin for the 48-MHz clock clock multiplication circuit of the USB multiplication Connect to the system ground (Vss). circuit Rev. 1.00, 02/04, page 25 of 804 Classification Bluetooth interface (BT) Symbol RDI_ TXTRDATA*2 RDI_RXBDW_ OUT*2 RDI_REFCLK_ IN*2 RDI_CTRL2*2 RDI_CTRL3*2 RDI_CTRL4*2 I/O I/O Name Data bus for transmission/ reception Packet control BT clock input RF IC control 2 RF IC control 3 RF IC control 4 SPI clock SPI data SPI enable VCI clock Function Bus for data transmission/reception with the RF IC Signal for notifying the RF IC of the packet processing state of the BT Input the BT operating clock. Used for external power amplifier control when supporting class 1. Strobe signal for enabling the RF IC oscillator Reset control and power-down control output for RF IC Serial interface clock Serial interface data Serial interface enable signal Supplies a clock to the voice CODEC IC. Output Input Output Output Output RCI_SPI_CLK*2 Output RCI_SPI_ TXRX*2 I/O RCI_SPI_ENB*2 Output VCI_SCO_ CLK_OUT*3 VCI_SCO_ SYNC_OUT*3 Output Output VCI Supplies a frame-synchronization synchronization signal to the voice CODEC IC. SCO transmit data SCO receive data Inputs SCO data to be transmitted from the voice CODEC IC. Outputs received SCO data to the voice CODEC IC. VCI_SCO_TX*3 Input VCI_SCO_RX*3 Output VCI_HWC*3 VCI_CODEC_ PWRDWN*3 RTCSEL0 RREF EXTAL2 XTAL2 Output Output Input Input Input Output VCI mode select Selects operating mode of the voice CODEC IC (STLC7550). VCI power down Controls power-down for the voice CODEC IC. Test pin Test pin Crystal resonator connection for low-power clock Test pin This pin should be fixed to low. Test pin This pin should be pulled-up. For connection to a crystal resonator for a low-power clock. When RTCSEL0 = high, these pins are inactive. Rev. 1.00, 02/04, page 26 of 804 Classification Bluetooth interface (BT) Symbol Vcc_28 I/O Input Name Power supply Function Power supply pin for the RF-IC connection pin The same level should be supplied as the RF IC. Vss_28 D/A converter (DAC) DA1, DA0 AVcc (DAC) Input Output Input Ground Analog output pin D/A analog power supply Ground pin for the RF-IC connection pin Analog output pin for the D/A converter Power supply pin for the D/A converter. When the D/A converter is not in use, connect this pin to the port power supply (Vcc). Ground pin for the D/A converter. Connect this pin to the system power supply (Vss). 7-bit general I/O port pin 8-bit general I/O port pin 6-bit general I/O port pin 7-bit general I/O port pin 5-bit general I/O port pin 5-bit general I/O port pin Test-clock input pin Inputs the test-mode select signal. Serial input pin for instructions and data Serial output pin for instructions and data Initialization-signal input pin Destination-address output pin for branch instruction Synchronization clock output pin AVss (DAC) Input D/A analog ground General port General port General port General port General port General port Test clock Test mode select Test data input Test data output Test reset AUD data AUD clock I/O port PTA6 to PTA0 PTB7 to PTB0 PTD5 to PTD0 PTE6 to PTE0 PTG4 to PTG0 PTH4 to PTH0 I/O I/O I/O I/O I/O I/O Input Input Input Output Input Output Output Output User debugging TCK interface (H-UDI) TMS TDI TDO TRST Advanced user debugger (AUD) AUDATA3 to AUDATA0 AUDCK AUDSYNC AUD Data start-position acknowledgesynchronization signal output pin signal Rev. 1.00, 02/04, page 27 of 804 Classification E10A interface Symbol ASEBRKAK I/O Output Name Break mode acknowledge Function Indicates that the E10A emulator has entered its break mode. For the connection with the E10A, refer to the SH7660 E10A Emulator User's Manual (tentative title). ASEMD0 Input ASE mode Sets the ASE mode. Notes: 1. VDD, VDD (PLL), and VDD (DLL) should not connect mutually in the short distance, should separate as much as possible, and give the noise measures. 2. These pins are connected to the RF IC. For details on the connection, refer to section 21, Bluetooth Interface (BT). 3. These pins are connected to the voice CODEC IC. For details on the connection, refer to section 21, Bluetooth Interface (BT). Rev. 1.00, 02/04, page 28 of 804 Section 2 CPU 2.1 2.1.1 Processing States and Processing Modes Processing States This LSI supports four types of processing states: a reset state, an exception handling state, a program execution state, and a power-down state, according to the CPU processing states. Reset State: In the reset state, the CPU is reset. The LSI supports two types of resets: power-on reset and manual reset. For details on resets, refer to section 4, Exception Handling. In a power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In a manual reset, the register contents of a part of the LSI on-chip modules, such as the bus state controller (BSC), are retained. For details, refer to section 27, List of Registers. The CPU internal statuses and registers are initialized both in a power-on reset and manual reset. After initialization, the program branches to address H'A0000000 to pass control to the reset processing program defined by the user to be executed. Exception Handling State: In the exception handling state, the CPU processing flow is changed temporarily by a general exception or interrupt exception processing. The program counter (PC) and status register (SR) are saved in the save program counter (SPC) and save status register (SSR), respectively. The program branches to an address obtained by adding a vector offset to the vector base register (VBR) and passes control to the exception handling program defined by the user to be executed. For details on exception handling states, refer to section 4, Exception Handling. Program Execution State: The CPU executes programs sequentially. Power-Down State: The CPU stops operation to reduce power consumption. The power-down state can be entered by executing the SLEEP instruction. For details on the power-down state, refer to section 13, Power-Down Modes. Figure 2.1 shows a status transition diagram. CPUS3D0S_0100200302000 Rev. 1.00, 02/04, page 29 of 804 (From any states) Power-on reset Manual reset Reset state Reset processing routine starts Program execution state Multiple exceptions Exception handling routine starts An exception is accepted SLEEP instruction Exception handling state An exception is accepted Power-down mode Figure 2.1 Processing State Transitions 2.1.2 Processing Modes (User Mode/Privileged Mode) This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) in the status register (SR). If the MD bit is cleared to 0, user mode is selected. If the MD bit is set to 1, privileged mode is selected. The CPU automatically enters privileged mode by a transition to the reset state or exception handling state. In privileged mode, any registers and resources in address spaces can be accessed. For details on differences of registers and address spaces which can be accessed by the CPU in each processing mode, refer to section 2.2, Memory Map and section 2.3, Register Descriptions. Writing 0 to the MD bit in SR puts the CPU in user mode. In user mode, some of the registers, including SR, and some of the address spaces cannot be accessed by the user program and system control instructions cannot be executed. This function effectively protects the system resources from the user program. To change the processing mode from user to privileged mode, a transition to the exception handling state is required.*1*2 Notes: 1. To call a service routine used in privileged mode from user mode, the LSI supports an unconditional trap instruction (TRAPA). 2. When a transition from user mode to privileged mode occurs, the contents of SR and PC are saved. A program execution in user mode can be resumed by restoring the contents of SR and PC. To return from an exception handling program, the LSI supports an RTE instruction. Rev. 1.00, 02/04, page 30 of 804 2.2 Memory Map The address spaces that can be accessed by the CPU mounted on this LSI differ depending on the processing mode as described above, and the address space handled by the CPU may not match the physical address space. To avoid misunderstandings, the address space which is output by the CPU is referred to as the logical address space while the actual physical address space is referred to as the physical address space. Furthermore, among the physical address space, the space to which this LSI can make external access is referred to as the external address space. These terms are used hereafter in this manual. 2.2.1 Logical Address Space The address space which is output by the CPU is referred to as the logical address space. The CPU of this LSI supports a 32-bit logical address space and accesses system resources using the 4 Gbytes of logical address space. User programs and data are accessed from the logical address space. From the hardware view, the addresses output from the CPU are used on the L bus (see figure 1.1 in section 1, Overview). The logical address space is divided into several areas and managed as shown in figure 2.2. In privileged mode, 4 Gbytes of space from P0 area to P4 area can be accessed. In user mode, 2 Gbytes of space in U0 area can be accessed. When the DSP bit in SR is set to 1, 16 Mbytes of space in Uxy area can be also accessed. If areas other than U0 and Uxy are accessed in user mode, an address error occurs. Rev. 1.00, 02/04, page 31 of 804 H'00000000 P0 area (2 Gbytes) Cacheable U0 area (2 Gbytes) Cacheable H'80000000 P1 area (512 Mbytes) Cacheable H'A0000000 Address error Uxy area* Not cacheable H'A5000000 H'A5FFFFFF P2 area (512 Mbytes) Not cacheable H'C0000000 P3 area (512 Mbytes) Cacheable H'E0000000 Address error P4 area (512 Mbytes) Not cacheable H'FFFFFFFF In privileged mode In user mode Note: * Exists only when the DSP bit in SR is 1. Figure 2.2 Logical Address Space P0/U0 Area: This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user mode. For the P0 and U0 areas, access using the cache is enabled.* P1 Area: The P1 area is defined as a privileged area that is cacheable.* Normally, this area contains programs that operate at high-speed in privileged mode, such as the kernel of the operating system (OS) and the exception handler. P2 Area: The P2 area is defined as a privileged area that is not cacheable. The reset processing program that is initiated when a transition is made to the reset state is written from the start address of the P2 area (H'A0000000). Normally, this area contains programs that are needed to initiate the OS, such as the system initial setting routine. Note that access to several on-chip I/O registers requires the program to be saved in the P2 area. P3 Area: The P3 area is defined as a privileged area that is cacheable.* P4 Area: The P4 area is a control space that is not cacheable and can be accessed only in privileged mode. Figure 2.3 shows the P4 area in detail. Several on-chip I/O registers are assigned to this area. For details on I/O registers which are assigned to this area, see section 27, List of Registers. Rev. 1.00, 02/04, page 32 of 804 H'E0000000 Reserved area (256 Mbytes) H'F0000000 Cache address area (16 Mbytes) H'F1000000 Cache data array area (16 Mbytes) H'F2000000 Reserved area (160 Mbytes) H'FC000000 Control register area (64 Mbytes) H'FFFFFFFF Figure 2.3 P4 Area Uxy Area: The Uxy area that can be used when the DSP bit in SR is set to 1 in user mode is mapped to the on-chip memory of this LSI. Accessing this area when the DSP bit is 0 in user mode will result in an address error. This area cannot be accessed through the cache. For details on the Uxy area, see section 6, X/Y Memory and section 7, U Memory. For details on the DSP bit, see section 3, DSP Operating Unit. Note: * Whether the cache is used or not is determined according to the CE bit in the cache control register (CCR1). 2.2.2 Physical Address Space The physical address space obtained by address translation of addresses output from the CPU is referred to as the physical address space. From the hardware view, the addresses of the physical address space are used on the I bus. Similar to the logical address space, this LSI supports a 32-bit physical address space. However, as shown in figure 2.4, the upper three bits of the 32 bits are masked and handled as a shadow. Therefore, only 29 bits are actually used to access the physical address space and 0.5 Gbytes of physical memory can be accessed. Replacing the upper three bits of an address in this area with 0s makes the address in the corresponding physical address space.* For details on the physical address space, see section 9, Bus State Controller (BSC). Bus masters other than the CPU, e.g. DMAC, are directly connected to the I bus. Therefore, instead of handling the logical address space, they directly handle the physical address space. Note: * Since the on-chip I/O registers can be accessed only if the upper three bits of a logical address are set to 111 (corresponding to the P4 area in privileged mode), the upper three bits are output with the same values of 111 on the I bus. Rev. 1.00, 02/04, page 33 of 804 H'00000000 29-bit (512-Mbyte) physical address space H'20000000 Shadow space for 29-bit physical address space H'40000000 Shadow space for 29-bit physical address space H'60000000 Shadow space for 29-bit physical address space H'80000000 Shadow space for 29-bit physical address space Shadow space for 29-bit physical address space H'A0000000 H'C0000000 Shadow space for 29-bit physical address space H'E0000000 On-chip I/O area H'FFFFFFFF Figure 2.4 Physical Address Space 2.2.3 External Address Space The physical address space is divided into eight areas as shown in figure 2.5. Area 1 is used as the on-chip I/O space, and most of the on-chip registers of this LSI are mapped to this area*. In this LSI, areas 2 and 5 to 7 are reserved areas. The remaining three areas, areas 0, 3, and 4, are used as the external address space. Each area of the external address space can be connected to different types of memory (for details, see section 9, Bus State Controller (BSC)). The upper three bits of a logical address are normally masked from the CPU and treated as a shadow. In privileged mode, for example, logical addresses H'00000100 in the P0 area, H'80000100 in the P1 area, H'A0000100 in the P2 area, and H'C0000100 in the P3 area are all mapped to the same external address H'00000100 in area 0. However, since addresses cannot be mapped to the P4 area, the external address space cannot be accessed by an access to the P4 area. The three areas (areas 0, 3, and 4) to which the external memory can be connected are each a 64Mbyte external address space. Since this LSI has 24 address pins, a maximum of 16 Mbytes of memory can be mounted for each area. Figure 2.5 shows the mounted space corresponding to area 0. Note: * To access an on-chip I/O register mapped to area 1 of the external address space, make an access from the P2 area of the logical address space that is not cacheable. Rev. 1.00, 02/04, page 34 of 804 External address space 29-bit (512-Mbyte) physical address space H'00000000 H'00000000 Area 0 H'04000000 Area 1 (On-chip registers and memories) H'01000000 Mounted space (Max. 16 Mbytes) H'08000000 Area 2 (Reserved area) H'0C000000 Area 3 H'10000000 H'02000000 Area 4 H'14000000 Area 5 (Reserved area) H'03000000 H'18000000 Area 6 (Reserved area) H'1C000000 Area 7 (Reserved area) H'1FFFFFFF H'03FFFFFF Figure 2.5 External Address Space and Mounted Space (Area 0) Rev. 1.00, 02/04, page 35 of 804 2.3 Register Descriptions The CPU of this LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. General Registers: This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15. R0 to R7 are banked. The processing mode and the register bank (RB) bit in the status register (SR) determine which set of banked registers (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers. System Registers: This LSI incorporates the multiply and accumulate registers (MACH/MACL) and procedure register (PR) as system registers. These registers can be accessed regardless of the processing mode. Program Counter: The program counter (PC) stores the value obtained by adding 4 to the current instruction address. Control Registers: This LSI incorporates the status register (SR), global base register (GBR), save status register (SSR), save program counter (SPC), and vector base register (VBR) as control registers. Only GBR can be accessed in user mode. Control registers other than GBR can be accessed only in privileged mode. Table 2.1 shows the register values after a reset. Figure 2.6 shows the register configurations in each processing mode. Table 2.1 Register Initial Values Registers Initial Values* Undefined Register Type General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 System registers Program counter Control registers MACH, MACL, PR PC SR Undefined H'A0000000 MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0 bits = B'1111 (H'F), DSP bit = 0, reserved bits = all 0, other bits = undefined Undefined H'00000000 GBR, SSR, SPC VBR Note: * Initialized by a power-on reset or manual reset. Rev. 1.00, 02/04, page 36 of 804 31 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 0 31 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 0 GBR MACH MACL PR PC (a) User mode register configuration (b) Privileged mode register configuration (RB = 1) (c) Privileged mode register configuration (RB = 0) Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode. 2. Bank register 3. Bank register Accessed as a general register when the RB bit is set to 1 in SR. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Bank register Accessed as a general register when the RB bit is cleared to 0 in SR. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.6 Register Configuration in Each Processing Mode Rev. 1.00, 02/04, page 37 of 804 2.3.1 General Registers There are twenty-four general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15. Figure 2.7 shows the general register configuration. R0 to R7 are banked. The processing mode and the register bank (RB) bit in the status register (SR) determine which set of banked registers (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers. R0 to R7 registers in the selected bank are accessed as R0 to R7. R0 to R7 in the non-selected bank is accessed as R0_BANK to R7_BANK by the control register load instruction (LDC) and control register store instruction (STC). In user mode, bank 0 is selected regardless of the RB bit value. Sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. R0_BANK1 to R7_BANK1 registers in bank 1 cannot be accessed. In privileged mode that is entered by a transition to the exception handling state, the RB bit is set to 1 to select bank 1. In this case, sixteen registers: R0_BANK1 to R7_BANK1 in bank 1 and R8 to R15 are accessed as general registers R0 to R15. A bank is switched automatically when an exception handling state is entered, registers R0 to R7 need not be saved by the exception handling routine. R0_BANK0 to R7_BANK0 in bank 0 can be accessed as R0_BANK to R7_BANK by the LDC or STC instructions. In privileged mode, bank 0 can also be used as general registers by clearing the RB bit to 0. In this case, sixteen registers: R0_BANK0 to R7_BANK0 in bank 0 and R8 to R15 are accessed as general registers R0 to R15. R0_BANK1 to R7_BANK1 in bank 1 can be accessed as R0_BANK to R7_BANK by the LDC or STC instructions. The general registers R0 to R15 are used as equivalent registers for almost all instructions. In some instructions, R0 is implicitly used or only R0 may be used as source or destination registers. Rev. 1.00, 02/04, page 38 of 804 31 R0*1,*2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 General Registers: Undefined after reset Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source or destination register. 2. R0 to R7 are banked registers. In privileged mode, either R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1 is selected by the RB bit in SR. Figure 2.7 General Registers 2.3.2 System Registers The system registers which are the following two registers can be accessed by the LDS or STS instructions. Figure 2.8 shows the system register configuration. Multiply and Accumulate Registers: The multiply and accumulate registers store the results of multiplication and accumulation instructions or multiplication instructions. These registers also store additional values for the multiplication and accumulation instructions. After a reset, these registers are undefined. The multiply and accumulate registers consist of the multiply and accumulate high register (MACH) which stores the upper 32 bits and multiply and accumulate low register (MACL) which stores lower 32 bits. Procedure Register: The procedure register (PR) stores the return address for a subroutine call using the BSR, BSRF, or JSR instruction. The return address stored in PR is restored to the program counter (PC) by the RTS (return from the subroutine) instruction. After a reset, this register is undefined. Rev. 1.00, 02/04, page 39 of 804 2.3.3 Program Counter The program counter (PC) stores the value obtained by adding 4 to the current instruction address. Figure 2.8 shows the PC configuration. There is no instruction to read PC directly. Before an exception handling state is entered, the PC is saved in the save program counter (SPC). Before a subroutine call is executed, PC is saved in the procedure register (PR). In addition, PC can be used for PC relative addressing mode. Multiply and accumulate registers (MAC) 31 MACH MACL Procedure register (PR) 31 PR Program counter (PC) 31 PC 0 0 0 Figure 2.8 System Registers and Program Counter Rev. 1.00, 02/04, page 40 of 804 2.3.4 Control Registers The control registers can be accessed by the LDC or STC instruction in privileged mode. The global base register (GBR) can also be accessed in user mode. The control registers are the following five registers. Status Register (SR): SR stores various information which indicates the system status. SR can be accessed only in privileged mode. Rev. 1.00, 02/04, page 41 of 804 Bit 31 Bit Name Initial Value R/W Description 0 R Reserved This bit is always read as 0. The write value should always be 0. When 1 is written to this bit, operation cannot be guaranteed. 30 MD 1 R/W Processing Mode Indicates the CPU processing mode. 0: User mode 1: Privileged mode The MD bit is set to 1 after a reset or in an exception handling state. 29 RB 1 R/W Register Bank The general registers R0 to R7 are banked registers. The RB bit selects a bank used in privileged mode. 0: Selects bank 0 registers. In this case, R0_BANK0 to R7_BANK0 and R8 to R15 are used as general registers. R0_BANK1 to R7_BANK1 can be accessed by the LDC or STC instruction. 1: Selects bank 1 registers. In this case, R0_BANK1 to R7_BANK1 and R8 to R15 are used as general registers. R0_BANK0 to R7_BANK0 can be accessed by the LDC or STC instruction. The RB bit is set to 1 after a reset or in an exception handling state. 28 BL 1 R/W Block 0: Enables an interrupt or user break. 1: Disables an interrupt or user break. The BL bit is set to 1 after a reset or in an exception handling state. 27 to 10 All 0 R Reserved*2 These bits are always read as 0. The write value should always be 0. When 1 is written to these bits, operation cannot be guaranteed. Rev. 1.00, 02/04, page 42 of 804 Bit 9 8 Bit Name M Q Initial Value R/W Description 1 R/W M Bit*1 R/W Q Bit* These bits are used by the DIV0S, DIV0U, and DIV1 instructions. These bits can be changed even in user mode by executing these instructions. These bits are undefined at a reset. These bits do not change in an exception handling state. 7 6 5 4 3, 2 I3 I2 I1 I0 1 1 1 1 All 0 R/W Interrupt Mask Bits R/W The 4-bit data indicates the interrupt mask level. These bits R/W do not change even if an interrupt occurs. At a reset, these bits are initialized to B'1111. These bits are not affected in R/W an exception handling state. R Reserved*2 These bits are always read as 0. The write value should always be 0. When 1 is written to these bits, operation cannot be guaranteed. 1 S R/W Saturation Mode*1 Specifies saturation mode for multiply instructions or multiply and accumulate instructions. This bit can be specified by the SETS and CLRS instructions in user mode. At a reset, this bit is undefined. This bit is not affected in an exception handling state. 0 T R/W T Bit*1 Indicates true or false for compare instructions or carry or borrow occurrence for an operation instruction with carry or borrow. This bit can be specified by the SETT and CLRT instructions in user mode. At a reset, this bit is undefined. This bit is not affected in an exception handling state. Notes: 1. The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits can be read or written in privileged mode. 2. When DSP is used, this bit is extended. Refer to section 3.2.3, CPU Register Sets. Save Status Register (SSR): The save status register (SSR) can be accessed only in privileged mode. Before entering the exception handling state, the contents of SR are saved. At a reset, the SSR initial value is undefined. Save Program Counter (SPC): The save program counter (SPC) can be accessed only in privileged mode. Before entering the exception handling state, the contents of PC are saved. At a reset, the SPC initial value is undefined. Rev. 1.00, 02/04, page 43 of 804 Global Base Register (GBR): The global base register (GBR) is referenced as a base register in GBR indirect addressing mode. At a reset, the GBR initial value is undefined. Vector Base Register (VBR): The vector base register (VBR) can be accessed only in privileged mode. If a transition from a state other than a reset state to exception handling state occurs, this register is referenced as a base address of the branch destination. For details, refer to section 4, Exception Handling. At a reset, VBR is initialized to H'00000000. Figure 2.9 shows the control register configuration. Save status register (SSR) 31 SSR Save program counter (SPC) 31 SPC 0 0 Global base register (GBR) 31 GBR Vector base register (VBR) 31 VBR 0 0 Status register (SR) 31 0 MD RB BL 0 0 0 M Q I3 I2 I1 I0 0 0 S T Figure 2.9 Control Register Configuration Rev. 1.00, 02/04, page 44 of 804 2.4 2.4.1 Data Formats Register Data Format Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 Longword 0 2.4.2 Memory Data Formats Memory data formats are classified into byte, word, and longword. Memory can be accessed in bytes, words, and longwords. When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Word operand must be accessed from word boundary (even address in two bytes: address 2n) and longword operand must be accessed from longword boundary (even address in four bytes: address 4n). Otherwise, an address error will occur and an exception handling state will be entered. Byte operand can be accessed from any address. When a word or longword operand is accessed, the byte positions on the memory corresponding to the word or longword data on the register is determined according to the specified endian mode (big endian or little endian). Figure 2.10 shows a byte correspondence in big endian mode. In big endian mode, the MSB byte in the register corresponds to the lowest address in the memory, and the LSB byte in the register corresponds to the highest address. For example, if the contents of the general register R0 is stored at an address indicated by the general register R1 in longwords, the MSB byte in R0 is stored at the address indicated by the R1 and the LSB byte in R0 is stored at the address indicated by the (R1 + 3). The on-chip device registers assigned to memory are accessed in big endian mode. Note that the available access size (byte, word, or longword) differs in each register. Note: The CPU instruction codes of this LSI must be stored in words. In big endian mode, the instruction code must be stored from upper byte to lower byte in this order from the word boundary on the memory. Rev. 1.00, 02/04, page 45 of 804 31 Byte position in R0 23 15 7 [7:0] 0 [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] Byte position in memory [7:0] @(R1+0) @(R1+1) @(R1+2) @(R1+3) (a) Byte access Example: MOV.B R0, @R1 (R1 = Address 4n) [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] @(R1+0) @(R1+1) @(R1+2) @(R1+3) (b) Word access Example: MOV.W R0, @R1 (R1 = Address 4n) @(R1+0) @(R1+1) @(R1+2) @(R1+3) (c) Longword access Example: MOV.L R0, @R1 (R1 = Address 4n) Figure 2.10 Data Format on Memory (Big Endian Mode) The little endian mode can also be specified as data format. Either big endian or little endian mode should be selected according to the external pin (MD5 pin) at a power-on reset. When the MD5 pin goes low, the processor operates in big endian mode. When the MD5 pin goes high, the processor operates in little endian mode. The endian mode cannot be changed dynamically. In little endian mode, the MSB byte in the register corresponds to the highest address in the memory, and the LSB byte in the register corresponds to the lowest address (figure 2.11). For example, if the contents of the general register R0 is stored at an address indicated by the general register R1 in longwords, the MSB byte of R0 is stored at the address indicated by the (R1 + 3) and the LSB byte of R0 is stored at the address indicated by R1. If little endian mode is selected, the on-chip memory of this LSI is accessed in little endian mode. However, the on-chip device registers assigned to memory are accessed in big endian mode. Note that the available access size (byte, word, or longword) differs in each register. Note: The CPU instruction codes of this LSI must be stored in words. In little endian mode, the instruction code must be stored from lower byte to upper byte in this order from the word boundary on the memory. 31 Byte position in R0 23 15 7 [7:0] 0 [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] Byte position in memory [7:0] @(R1+3) @(R1+2) @(R1+1) @(R1+0) (a) Byte access Example: MOV.B R0, @R1 (R1 = Address 4n) [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] @(R1+3) @(R1+2) @(R1+1) @(R1+0) (b) Word access Example: MOV.W R0, @R1 (R1 = Address 4n) @(R1+3) @(R1+2) @(R1+1) @(R1+0) (c) Longword access Example: MOV.L R0, @R1 (R1 = Address 4n) Figure 2.11 Data Format on Memory (Little Endian Mode) Rev. 1.00, 02/04, page 46 of 804 2.5 2.5.1 Features of Instructions Instruction Execution Method Instruction Length: All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one cycle. All data are handled in longwords (32 bits). Memory can be accessed in bytes, words, or longwords. In this case, byte or word data is sign-extended and handled as longword data. Immediate data is sign-extended to longword size for arithmetic operations (MOV, ADD, and CMP/EQ instructions) or zero-extended to longword size for logical operations (TST, AND, OR, and XOR instructions). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly on memory. Delayed Branching: Unconditional branch instructions are executed as delayed branches. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. An example is shown below. This LSI supports two types of conditional branch instructions: delayed branch instruction and normal branch instruction. BRA ADD TRGET R1, R0 ; ADD instruction is executed before branching to the TRGET. T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. An example of using the T bit is shown below. ADD ADD CMP/EQ BT set #0, R0 #1, R0 ; The T bit cannot be modified by the instruction. ; The T bit is set to 1 if R0 is 0. TRGET ; Branch to the TRGET if the T bit is to 1 (R0 = 0). Rev. 1.00, 02/04, page 47 of 804 Literal Constant: Byte literal constant is placed inside the instruction code as immediate data. Since the instruction length is fixed to 16 bits, word or longword literal constant is not placed inside the instruction code, but stored as a table in main memory. The table in memory is referenced with a MOV instruction using PC-relative addressing mode with displacement. An example is shown below. MOV.W @(disp, PC), R0 Absolute Addresses: The absolute address value should be placed in a table in main memory as well as word or longword literal constant. This value is transferred to a register and the operand access is specified using indexed register indirect addressing mode. The absolute address value is stored in a register during execution of an instruction. This is also applied to the word or longword immediate data. 16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. As well as the absolute addresses, this value is transferred to a register and the operand access is specified using indexed register indirect addressing mode. The displacement value is stored in a register during execution of an instruction. This is also applied to the word or longword immediate data. Rev. 1.00, 02/04, page 48 of 804 2.5.2 Addressing Modes Table 2.2 shows addressing modes and effective address calculation methods. Table 2.2 Addressing Mode Register direct Register indirect Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Method Rn @Rn Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Calculation Formula -- Rn Register @Rn+ indirect with post-increment Effective address is register Rn contents. A Rn constant is added to Rn after instruction After instruction execution: 1 for a byte operand, 2 for a word execution operand, or 4 for a longword operand. Rn Rn + 1/2/4 + 1/2/4 Rn Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Register @-Rn indirect with pre-decrement Effective address is register Rn contents, Byte: Rn - 1 Rn decremented by a constant beforehand: 1 Word: Rn - 2 Rn for a byte operand, 2 for a word operand, or Longword: Rn - 4 Rn 4 for a longword operand. Rn Rn - 1/2/4 Rn 1/2/4 1/2/4 (Instruction executed with Rn after calculation) Rev. 1.00, 02/04, page 49 of 804 Addressing Mode Register indirect with displacement Instruction Format @(disp:4, Rn) Effective Address Calculation Method Calculation Formula Effective address is register Rn Byte: Rn + disp contents with Word: Rn + disp x 2 4-bit displacement disp added. After disp is zero-extended, it is multiplied by Longword: Rn + disp x 4 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) x + Rn + disp x 1/2/4 1/2/4 Indexed @(R0, Rn) register indirect Effective address is sum of register Rn Rn + R0 and R0 contents. Rn + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR Byte: GBR + disp contents with 8-bit displacement disp Word: GBR + disp x 2 added. After disp is zero-extended, it is Longword: GBR + disp x 4 multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) + GBR + disp x 1/2/4 x 1/2/4 Rev. 1.00, 02/04, page 50 of 804 Addressing Instruction Mode Format Indexed GBR @(R0, GBR) indirect Effective Address Calculation Method Calculation Formula Effective address is sum of register GBR and GBR + R0 R0 contents. GBR + R0 GBR + R0 PC-relative @(disp:8, PC) Effective address is register PC with 8-bit with displacement disp added. After disp is zerodisplacement extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC & H'FFFFFFFC * PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 Word: PC + disp x 2 Longword: PC&H'FFFFFFFC + disp x 4 + disp (zero-extended) x 2/4 * : With longword operand PC-relative disp:8 Effective address is register PC with 8-bit displacement disp added after being signextended and multiplied by 2. PC PC + disp x 2 disp (sign-extended) x 2 + PC + disp x 2 Rev. 1.00, 02/04, page 51 of 804 Addressing Mode PC-relative Instruction Format Effective Address Calculation Method disp:12 Effective address is register PC with 12-bit displacement disp added after being signextended and multiplied by 2. PC Calculation Formula PC + disp x 2 disp (sign-extended) x 2 + PC + disp x 2 Rn Effective address is sum of register PC and Rn contents. PC + Rn PC + Rn PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. -- -- -- Note: For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x 2, or x 4) according to the operand size to clarify the LSI operation. For details on actual assembler description, refer to the description rules in each assembler. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC relative with displacement disp:8, disp:12 ; PC relative Rev. 1.00, 02/04, page 52 of 804 2.5.3 Instruction Formats Table 2.3 shows the instruction formats and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: iiii: dddd: Table 2.3 Destination register Immediate data Displacement Instruction Formats Source Operand -- Destination Operand -- Sample Instruction NOP Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx -- nnnn: register direct MOVT Rn STS MACH,Rn SR,@-Rn Control register or nnnn: register system register direct Control register or nnnn: preSTC.L system register decrement register indirect m type 15 0 xxxx mmmm xxxx xxxx mmmm: register direct Control register or LDC system register Rm,SR @Rm+,SR mmmm: postControl register or LDC.L increment register system register indirect mmmm: register indirect mmmm: PCrelative using Rm -- -- JMP BRAF @Rm Rm Rev. 1.00, 02/04, page 53 of 804 Instruction Format nm type 15 0 xxxx nnnn mmmm xxxx Source Operand mmmm: register direct mmmm: register direct Destination Operand nnnn: register direct nnnn: register indirect Sample Instruction ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) nnnn: *postincrement register indirect (multiplyand-accumulate operation) mmmm: postnnnn: register increment register direct indirect mmmm: register direct mmmm: register direct md type 15 0 xxxx xxxx mmmm dddd MOV.L @Rm+,Rn nnnn: preMOV.L Rm,@-Rn decrement register indirect nnnn: indexed register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: register indirect with displacement R0 (register direct) MOV.B @(disp,Rm),R0 nd4 type 15 0 xxxx xxxx nnnn dddd R0 (register direct) nnnndddd: register indirect with displacement mmmm: register direct mmmmdddd: register indirect with displacement nnnndddd: register indirect with displacement nnnn: register direct MOV.B R0,@(disp,Rn) nmd type 15 0 xxxx nnnn mmmm dddd MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Rev. 1.00, 02/04, page 54 of 804 Instruction Format d type 15 0 xxxx xxxx dddd dddd Source Operand dddddddd: GBR indirect with displacement Destination Operand Sample Instruction R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement dddddddd: PC-relative with displacement dddddddd: PC-relative d12 type 15 0 xxxx dddd dddd dddd MOV.L R0,@(disp,GBR) R0 (register direct) MOVA @(disp,PC),R0 -- -- BF BRA label label (label=disp+PC) dddddddddddd: PC-relative dddddddd: PCrelative with displacement iiiiiiii: immediate nd8 type 15 0 xxxx nnnn dddd dddd nnnn: register direct Indexed GBR indirect MOV.L @(disp,PC),Rn i type 15 xxxx xxxx 0 iiii iiii AND.B #imm,@(R0,GBR) #imm,R0 iiiiiiii: immediate iiiiiiii: immediate R0 (register direct) AND -- nnnn: register direct TRAPA #imm ADD #imm,Rn ni type 15 xxxx nnnn i i i i 0 iiii iiiiiiii: immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 1.00, 02/04, page 55 of 804 2.6 2.6.1 Instruction Set Instruction Set Based on Functions Table 2.4 lists the instruction types based on functions. Table 2.4 Type Data transfer instructions CPU Instruction Types Kinds of Instruction Op Code 5 MOV MOVA MOVT SWAP XTRCT Function Data transfer Effective address transfer T bit transfer Upper/lower swap Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, doubleprecision multiply-and-accumulate Double-precision multiplication (32 x 32 bits) 33 Number of Instructions 39 Arithmetic operation instructions 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL Rev. 1.00, 02/04, page 56 of 804 Type Arithmetic operation instructions Kinds of Instruction 21 Op Code MULS MULU NEG NEGC SUB SUBC SUBV Function Signed multiplication (16 x 16 bits) Unsigned multiplication (16 x 16 bits) Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Logical AND Bit inversion Logical OR Memory test and bit setting Logical AND and T bit setting Exclusive logical OR 1-bit left rotate with T bit 1-bit right rotate with T bit 1-bit left rotate 1-bit right rotate Arithmetic dynamic shift Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical dynamic shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift Number of Instructions 33 Logic operation instructions 6 AND NOT OR TAS TST XOR 14 Shift instructions 12 ROTCL ROTCR ROTL ROTR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn 16 Rev. 1.00, 02/04, page 57 of 804 Type Branch instructions Kinds of Instruction 9 Op Code BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Number of Instructions Conditional branch, delayed conditional 11 branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 74 System control instructions 14 CLRMAC MAC register clear CLRS CLRT LDC LDS NOP PREF RTE SETS SETT SLEEP STC STS TRAPA S bit clear T bit clear Load into control register Load into system register No operation Data prefetch to cache Return from exception handling S bit setting T bit setting Transition to power-down mode Store from control register Store from system register Trap exception handling Total: 67 187 The instruction code, operation, and number of execution states of the CPU instructions are shown in tables 2.5 to 2.10, classified by instruction type, using the format shown below. Rev. 1.00, 02/04, page 58 of 804 Instruction Indicated by mnemonic. Instruction Code Indicated in MSB LSB order. Operation Indicates summary of operation. Privilege Indicates a privileged instruction. Execution States Value when no wait states are inserted*1 T Bit Value of T bit after instruction is executed Legend --: No change Legend OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Rn: Source register Destination register Legend mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: dddd: Immediate data Displacement*2 Legend , : (xx): Transfer direction Memory operand M/Q/T: Flag bits in SR &: |: ^: ~: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit imm: Immediate data disp: Displacement < Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory register) is also used by the following instruction 2. Scaled (x 1, x 2, or x 4) according to the instruction operand size, etc. Rev. 1.00, 02/04, page 59 of 804 Table 2.5 Instruction MOV Data Transfer Instructions Instruction Code Operation 1110nnnniiiiiiii 1001nnnndddddddd Privileged Mode Cycles T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #imm,Rn imm Sign extension Rn (disp x 2+PC)Sign extension Rn (disp x 4+PC)Rn RmRn Rm(Rn) Rm(Rn) Rm(Rn) (Rm)Sign extensionRn (Rm)Sign extensionRn (Rm)Rn Rn-1Rn, Rm(Rn) Rn-2Rn, Rm(Rn) Rn-4Rn, Rm(Rn) (Rm)Sign extensionRn, Rm+1Rm (Rm)Sign extensionRn, Rm+2Rm (Rm)Rn, Rm+4Rm R0(disp+Rn) R0(disp x 2+Rn) Rm(disp x 4+Rn) MOV.W @(disp,PC),Rn MOV.L MOV @(disp,PC),Rn Rm,Rn 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@-Rn MOV.W Rm,@-Rn MOV.L Rm,@-Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn (disp+Rm)Sign extensionR0 (disp x 2+Rm)Sign extensionR0 (disp x 4+Rm)Rn Rm(R0+Rn) Rm(R0+Rn) Rm(R0+Rn) 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) Rev. 1.00, 02/04, page 60 of 804 Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code Operation 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 Privileged Mode Cycles T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (R0+Rm)Sign extensionRn (R0+Rm)Sign extensionRn (R0+Rm)Rn R0(disp+GBR) R0(disp x 2+GBR) R0(disp x 4+GBR) (disp+GBR)Sign extensionR0 (disp x 2+GBR)Sign extensionR0 (disp x 4+GBR)R0 disp x 4+PCR0 TRn RmSwap lowest two bytesRn RmSwap two consecutive wordsRn Rm: Middle 32 bits of Rn Rn R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 Rn 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 SWAP.B Rm,Rn SWAP. W XTRCT Rm,Rn Rm,Rn 0110nnnnmmmm1001 0010nnnnmmmm1101 Rev. 1.00, 02/04, page 61 of 804 Table 2.6 Instruction ADD ADD ADDC ADDV Arithmetic Operation Instructions Instruction Code Operation 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii Privileged Mode Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit Carry Overflow Comparison result Rm,Rn #imm,Rn Rm,Rn Rm,Rn Rn+RmRn Rn+immRn Rn+Rm+TRn, CarryT Rn+RmRn, OverflowT If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn 0011nnnnmmmm0000 Comparison result 0011nnnnmmmm0010 Comparison result Comparison result Comparison result Comparison result Comparison result CMP/GE Rm,Rn CMP/HI CMP/GT CMP/PL CMP/PZ CMP/ST R DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn Rm,Rn Rn Rn Rm,Rn Rm,Rn Rm,Rn 0011nnnnmmmm0011 If Rn Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T 0011nnnnmmmm0110 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 T If Rn > 0, 1 T If Rn 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, if Rn = 0, 1 T, else 0 T 0100nnnn00010101 0100nnnn00010001 Comparison result 0010nnnnmmmm1100 Comparison result 0011nnnnmmmm0100 Calculation result Calculation result 0 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 2 (to 5)* DMULU.L Rm,Rn 0011nnnnmmmm0101 2 (to 5)* DT Rn 0100nnnn00010000 1 Comparison result Rev. 1.00, 02/04, page 62 of 804 Instruction EXTS.B Rm,Rn Instruction Code Operation 0110nnnnmmmm1110 Privileged Mode Cycles T Bit 1 1 1 1 A byte in Rm is sign-extended Rn A word in Rm is signextended Rn EXTS.W Rm,Rn EXTU.B Rm,Rn 0110nnnnmmmm1111 0110nnnnmmmm1100 A byte in Rm is zero-extended Rn A word in Rm is zeroextended Rn Signed operation of (Rn) x (Rm) + MAC MAC, Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) + MAC MAC, Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits Rn x Rm MACL 32 x 32 32 bits Signed operation of Rn x Rm MACL 16 x 16 32 bits Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 0-RmRn 0-Rm-TRn, BorrowT Rn-RmRn Rn-Rm-TRn, Borrow T Rn-RmRn, UnderflowT EXTU.W Rm,Rn MAC.L 0110nnnnmmmm1101 @Rm+, @Rn+ 0000nnnnmmmm1111 2 (to 5)* MAC.W @Rm+, @Rn+ 0100nnnnmmmm1111 2 (to 5)* MUL.L Rm,Rn 0000nnnnmmmm0111 2 (to 5)* 1 (to 3)* MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 1 (to 3)* NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 1 1 1 1 1 Borrow Borrow Underflow Note: * The number of execution cycles indicated within the parentheses ( ) are required when the operation result is read from the MACH/MACL register immediately after the instruction. Rev. 1.00, 02/04, page 63 of 804 Table 2.7 Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Logic Operation Instructions Instruction Code Operation 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii Privileged Mode Cycles T Bit 1 1 3 1 1 1 3 4 1 1 3 1 1 3 Test result Test result Test result Test result Rm,Rn #imm,R0 #imm, @(R0, GBR) Rm,Rn Rm,Rn #imm,R0 #imm, @(R0, GBR) @Rn Rm,Rn #imm,R0 #imm, @(R0, GBR) Rm,Rn #imm,R0 #imm, @(R0, GBR) Rn & Rm Rn R0 & imm R0 (R0+GBR) & imm (R0+GBR) 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii Rm Rn RnRm Rn R0imm R0 (R0+GBR)imm (R0+GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn) Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0+GBR) ^ imm (R0+GBR) 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Rev. 1.00, 02/04, page 64 of 804 Table 2.8 Instruction ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Shift Instructions Instruction Code Operation 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Privileged Mode Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit MSB LSB MSB LSB MSB LSB MSB LSB TRnMSB LSBRnT TRnT TRnT Rm, Rn Rn Rn Rm, Rn Rn Rn Rn Rn Rn Rn Rn Rn Rm 0: Rn << Rm Rn Rm < 0: Rn >> Rm [MSB Rn] TRn0 MSBRnT Rm 0: Rn << Rm Rn Rm < 0: Rn >> Rm [0 Rn] TRn0 0RnT Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Rev. 1.00, 02/04, page 65 of 804 Table 2.9 Instruction BF BF/S disp disp Branch Instructions Instruction Code Operation 10001011dddddddd Privileged Mode Cycles 3/1* 2/1* T Bit If T = 0, branch to disp x 2 + PC if T = 1, nop Delayed branch, if T = 0, branch to disp x 2 + PC if T = 1, nop If T = 1, branch to disp x 2 + PC if T = 0, nop Delayed branch, if T = 1, branch to disp x 2 + PC if T = 0, nop 10001111dddddddd BT BT/S disp disp 10001001dddddddd 3/1* 2/1* 10001101dddddddd BRA BRAF BSR disp Rm disp 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd Delayed branch, branch to disp x 2 + PC Delayed branch, branch to Rm + PC Delayed branch, reload next instruction address after delayed slot instruction to PR, and branch to disp x 2 + PC Delayed branch, reload next instruction address after delayed slot instruction to PR, and branch to Rm + PC Delayed branch, branch to Rm Delayed branch, reload next instruction address after delayed slot instruction to PR, and branch to Rm Delayed branch, branch to PR 2 2 2 BSRF Rm 0000mmmm00000011 2 JMP JSR @Rm @Rm 0100mmmm00101011 0100mmmm00001011 2 2 RTS 0000000000001011 2 Note: * One cycle when the branch is not executed. Rev. 1.00, 02/04, page 66 of 804 Table 2.10 System Control Instructions Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SSR @Rm+,SPC @Rm+, R0_BANK @Rm+, R1_BANK @Rm+, R2_BANK @Rm+, R3_BANK @Rm+, R4_BANK @Rm+, R5_BANK Instruction Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 Operation 0MACH,MACL 0S 0T RmSR RmGBR RmVBR RmSSR RmSPC RmR0_BANK RmR1_BANK RmR2_BANK RmR3_BANK RmR4_BANK RmR5_BANK RmR6_BANK RmR7_BANK (Rm)SR, Rm+4Rm (Rm)GBR, Rm+4Rm (Rm)VBR, Rm+4Rm (Rm)SSR,Rm+4Rm (Rm)SPC,Rm+4Rm Privileged Mode Cycles 1 1 1 6 4 4 4 4 4 4 4 4 4 4 4 4 8 4 4 4 4 4 4 4 4 4 4 T Bit 0 LSB LSB (Rm)R0_BANK,Rm+4Rm (Rm)R1_BANK,Rm+4Rm (Rm)R2_BANK,Rm+4Rm (Rm)R3_BANK, Rm+4Rm (Rm)R4_BANK, Rm+4Rm (Rm)R5_BANK, Rm+4Rm 0100mmmm10010111 0100mmmm10100111 0100mmmm10110111 0100mmmm11000111 0100mmmm11010111 Rev. 1.00, 02/04, page 67 of 804 Instruction LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP PREF RTE SETS SETT SLEEP STC STC STC STC STC STC STC STC STC STC STC STC STC STC.L STC.L STC.L SR,Rn GBR,Rn VBR,Rn SSR, Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn @Rm @Rm+, R6_BANK @Rm+, R7_BANK Rm,MACH Rm,MACL Rm,PR Instruction Code Operation 0100mmmm11100111 Privileged Mode Cycles 4 4 1 1 1 1 1 1 1 1 5 1 1 4* 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit 1 (Rm)R6_BANK, Rm+4Rm (Rm)R7_BANK, Rm+4Rm RmMACH RmMACL RmPR (Rm)MACH, Rm+4Rm (Rm)MACL, Rm+4Rm (Rm)PR, Rm+4Rm No operation (Rm) cache Delayed branch, SSR SR, branch to SPC 1S 1T Sleep SRRn GBRRn VBRRn SSRRn SPCRn R0_BANKRn R1_BANKRn R2_BANKRn R3_BANKRn R4_BANKRn R5_BANKRn R6_BANKRn R7_BANKRn Rn-4Rn, SR(Rn) Rn-4Rn, GBR(Rn) Rn-4Rn, VBR(Rn) 0100mmmm11110111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 @Rm+,MACH 0100mmmm00000110 @Rm+,MACL @Rm+,PR 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000mmmm10000011 0000000000101011 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 Rev. 1.00, 02/04, page 68 of 804 Instruction STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L SSR,@-Rn SPC,@-Rn Instruction Code Operation 0100nnnn00110011 0100nnnn01000011 Privileged Mode Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 T Bit Rn-4Rn, SSR(Rn) Rn-4Rn, SPC(Rn) R0_BANK,@-Rn 0100nnnn10000011 R1_BANK,@-Rn 0100nnnn10010011 R2_BANK,@-Rn 0100nnnn10100011 R3_BANK,@-Rn 0100nnnn10110011 R4_BANK,@-Rn 0100nnnn11000011 R5_BANK,@-Rn 0100nnnn11010011 R6_BANK,@-Rn 0100nnnn11100011 R7_BANK,@-Rn 0100nnnn11110011 MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Rn-4Rn, R0_BANK(Rn) Rn-4Rn, R1_BANK(Rn) Rn-4Rn, R2_BANK(Rn) Rn-4Rn, R3_BANK(Rn) Rn-4Rn, R4_BANK(Rn) Rn-4Rn, R5_BANK(Rn) Rn-4Rn, R6_BANK(Rn) Rn-4Rn, R7_BANK(Rn) MACHRn MACLRn PRRn Rn-4Rn, MACH(Rn) Rn-4Rn, MACL(Rn) Rn-4Rn, PR(Rn) Unconditional trap exception 2 occurs* TRAPA #imm Notes: *1 Minimum number of cycles before the chip enters the sleep state. *2 For details, refer to section 4, Exception Handling. 1. The table shows the minimum number of cycles required for execution. In practice, the number of execution cycles will be increased in the following conditions. a. If there is a conflict between an instruction fetch and a data access b. If the destination register of a load instruction (memory register) is also used by the following instruction. 2. For addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x 2, or x 4) according to the operand size to clarify the LSI operation. For details on assembler description, refer to the description rules in each assembler. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC relative with displacement disp:8, disp:12; PC relative Rev. 1.00, 02/04, page 69 of 804 2.6.2 Operation Code Map Table 2.11 shows the operation code map. Table 2.11 Operation Code Map Instruction Code MSB 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rm 0000 Rm 0000 Rn Fx Fx Fx: 0000 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 LSB MD: 00 0000 0001 STC STC STC STC SR, Rn SPC, Rn R0_BANK, Rn R4_BANK, Rn 00MD 0010 01MD 0010 10MD 0010 11MD 0010 00MD 0011 10MD 0011 Rm STC GBR, Rn STC VBR, Rn STC SSR, Rn STC R1_BANK, Rn STC R5_BANK, Rn STC R2_BANK, Rn STC R6_BANK, Rn BRAF Rm STC R3_BANK, Rn STC R7_BANK, Rn BSRF Rm PREF @Rm 01MD MOV.B Rm, @(R0, Rn) MOV.W Rm, @(R0, Rn) MOV.L Rm, @(R0, Rn) MUL.L Rm, Rn CLRT CLRS NOP SETT SETS DIV0U CLRMAC LDTLB 0000 0000 00MD 1000 0000 0000 01MD 1000 0000 0000 Fx 0000 0000 Fx 0000 0000 Fx 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0001 Rn 0010 Rn 0010 Rn 0010 Rn 0010 Rn 0011 Rn Fx Fx Fx Fx Rm Rm Rm Rm Rm Rm Rm 1001 1010 1011 1000 1001 1010 1011 RTS SLEEP RTE MOVT STS MACH, Rn STS MACL, Rn STS Rn PR, Rn 11MD MOV.B @(R0, Rm), Rn MOV.W @(R0, Rm), Rn MOV.L @(R0, Rm), Rn MAC.L @Rm+,@Rn+ disp MOV.L Rm, @(disp:4, Rn) Rm, @Rn Rm, @-Rn Rm, Rn MOV.W MOV.W AND XTRCT Rm, @Rn Rm, @-Rn Rm, Rn Rm, Rn MOV.L MOV.L XOR Rm, @Rn Rm, @-Rn Rm, Rn DIV0S OR Rm, Rn Rm, Rn 00MD MOV.B 01MD MOV.B 10MD TST 11MD CMP/STR Rm, Rn 00MD CMP/EQ Rm, Rn MULU.W Rm, Rn CMP/HS Rm, Rn MULSW Rm, Rn CMP/GE Rm, Rn Rev. 1.00, 02/04, page 70 of 804 Instruction Code MSB 0011 Rn 0011 Rn 0011 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn 0100 Rn Rm Rm Rm Fx Fx Fx Fx: 0000 Fx: 0001 MD: 01 Fx: 0010 MD: 10 CMP/HI SUBC Rm, Rn Rm, Rn Rm, Rn Rn Rn PR, @-Rn VBR, @-Rn Fx: 0011 to 1111 MD: 11 CMP/GT SUBV ADDV Rm, Rn Rm, Rn Rm, Rn LSB MD: 00 01MD DIV1 10MD SUB 11MD ADD 0000 0001 0010 SHLL SHLR STS.L STC.L STC.L STC.L R0_BANK, @-Rn Rm, Rn Rm, Rn Rm, Rn Rn Rn MACH, @-Rn SR, @-Rn SPC, @-Rn DMULU.L Rm,Rn DMULS.L Rm,Rn DT CMP/PZ STS.L STC.L Rn Rn MACL, @-Rn GBR, @-Rn ADDC SHAL SHAR STS.L STC.L 00MD 0011 01MD 0011 10MD 0011 STC.L SSR, @-Rn STC.L R1_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R6_BANK, @-Rn ROTCL Rn Rn @Rm+, PR STC.L R3_BANK, @-Rn STC.L R7_BANK, @-Rn 0100 Rn 11MD 0011 STC.L R4_BANK, @-Rn 0100 Rn 0100 Rn 0100 Rm Fx Fx Fx 0100 0101 0110 ROTL ROTR LDS.L Rn Rn CMP/PL Rn @Rm+, ROTCR LDS.L @Rm+, MACH LDS.L MACL 0100 Rm 0100 Rm 0100 Rm 00MD 0111 01MD 0111 10MD 0111 LDC.L LDC.L LDC.L @Rm+, SR @Rm+, SPC LDC.L @Rm+, GBR LDC.L @Rm+, VBR LDC.L @Rm+, SSR LDC.L @Rm+, R1_BANK LDC.L @Rm+, R5_BANK SHLL8 SHLR8 LDS TAS.B Rn Rn Rm, MACL @Rn LDC.L @Rm+, R2_BANK LDC.L @Rm+, R6_BANK SHLL16 SHLR16 LDS JMP Rn Rn Rm, PR @Rm LDC.L @Rm+, R3_BANK LDC.L @Rm+, R7_BANK @Rm+, R0_BANK 0100 Rm 11MD 0111 LDC.L @Rm+, R4_BANK 0100 Rn 0100 Rn 0100 Rm Fx Fx Fx 1000 1001 1010 1011 SHLL2 SHLR2 LDS JSR Rn Rn Rm, MACH @Rm 0100 Rm/ Fx Rn Rev. 1.00, 02/04, page 71 of 804 Instruction Code MSB 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm 0100 Rm 0100 Rn 0101 Rn 0110 Rn 0110 Rn 0110 Rn 0110 Rn 0111 Rn Rm Rm Fx: 0000 MD: 00 SHAD SHLD LDC LDC LDC LDC MAC.W MOV.L Rm, Rn Rm, Rn Rm, SR Rm, SPC Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 LSB 1100 1101 00MD 1110 01MD 1110 10MD 1110 11MD 1110 Rm Rm Rm Rm Rm Rm imm disp 1111 disp LDC Rm, GBR LDC Rm, VBR LDC Rm, SSR Rm, R0_BANK LDC Rm, R1_BANK Rm, R4_BANK LDC Rm, R5_BANK @Rm+, @Rn+ @(disp:4, Rm), Rn @Rm, Rn @Rm+, Rn MOV.W @Rm, Rn MOV.W @Rm+, Rn SWAP.W Rm, Rn EXTU.W Rm, Rn LDC Rm, R2_BANK LDC Rm, R6_BANK LDC Rm, R3_BANK LDC Rm, R7_BANK 00MD MOV.B 01MD MOV.B MOV.L MOV.L NEGC @Rm, Rn @Rm+, Rn Rm, Rn MOV NOT NEG Rm, Rn Rm, Rn Rm, Rn 10MD SWAP.B Rm, Rn 11MD EXTU.B Rm, Rn ADD MOV. B R0, @(disp: 4, Rn) # imm : 8, Rn EXTS.B Rm, Rn EXTS.W Rm, Rn 1000 00MD Rn MOV. W R0, @(disp: 4, Rn) MOV.W @(disp: 4, Rm), R0 disp: 8 disp: 8 BF BF/S disp: 8 disp: 8 1000 01MD Rm disp MOV.B @(disp:4, Rm), R0 1000 10MD imm/disp 1000 11MD imm/disp 1001 Rn 1010 disp 1011 disp 1100 00MD imm/disp disp CMP/EQ #imm:8, R0 BT BT/S MOV.W BRA BSR MOV.B @(disp: 8, PC), Rn disp: 12 disp: 12 MOV.W R0, @(disp: 8, GBR) MOV.W @(disp: 8, GBR), R0 MOV.L R0, @(disp: 8, GBR) MOV.L @(disp: 8, GBR), R0 MOVA @(disp: 8, PC), R0 #imm: 8, R0 TRAPA #imm: 8 R0, @(disp: 8, GBR) 1100 01MD disp MOV.B @(disp: 8, GBR), R0 1100 10MD imm 1100 11MD imm TST TST.B #imm: 8, @(R0, GBR) 1101 Rn 1110 Rn disp imm MOV.L MOV #imm: 8, R0 AND AND.B #imm: 8, R0 XOR XOR.B #imm: 8, R0 OR OR.B #imm: 8, @(R0, GBR) #imm: 8, @(R0, GBR) #imm: 8, @(R0, GBR) @(disp: 8, PC), Rn #imm:8, Rn 1111 ************ Note: For details, refer to the SH-3/SH-3E/SH3-DSP Programming Manual. Rev. 1.00, 02/04, page 72 of 804 Section 3 DSP Operating Unit 3.1 DSP Extended Functions This LSI incorporates a DSP unit and XY memory directly connected to the DSP unit. This LSI supports the DSP extended function instruction sets needed to control the DSP unit and XY memory. The DSP extended function instructions are classified into four groups (figure 3.1). Extended System Control Instructions for the CPU: If the DSP extended function is enabled, the following extended system control instructions can be used for the CPU. * Repeat loop control instructions and repeat loop control register access instructions are added. Looped programs can be executed efficiently by using the zero-overhead repeat control unit. For details, refer to section 3.3, CPU Extended Instructions. * Modulo addressing control instructions and control register access instructions are added. Function allows access to data with a circular structure. For details, refer to section 3.4, DSP Data Transfer Instructions. * DSP unit register access instructions are added. Some of the DSP unit registers can be used in the same way as the CPU system registers. For details, refer to section 3.4, DSP Data Transfer Instructions. Data Transfer Instructions for Data Transfers between DSP Unit and On-Chip XY Memory: Data transfer instructions for data transfers between the DSP unit and on-chip XY memory are called double-data transfer instructions. Instruction codes for these double-transfer instructions are 16-bit codes as well as CPU instruction codes. These data transfer instructions perform data transfers between the DSP unit and on-chip XY memory that is directly connected to the DSP unit. These data transfer instructions can be described in combination with other DSP unit operation instructions. For details, refer to section 3.4, DSP Data Transfer Instructions. Data Transfer Instructions for Data Transfers between DSP Unit Registers and All Virtual Address Spaces: Data transfer instructions for data transfers between DSP unit registers and all virtual address spaces are called single-data transfer instructions. Instruction codes for the doubletransfer instructions are 16-bit codes as well as CPU instruction codes. These data transfer instructions performs data transfers between the DSP unit registers and all virtual address spaces. For details, refer to section 3.4, DSP Data Transfer Instructions. DSP Unit Operation Instructions: DSP unit operation instructions are called DSP operation instructions. These instructions are provided to execute digital signal processing operations at high speed using the DSP. Instruction codes for these instructions are 32 bits. The DSP operation instruction fields consist of two fields: field A and field B. In field A, a function for double data transfer instructions can be descried. In field B, ALU operation instructions and multiply instructions can be described. The instructions described in fields A and B can be executed in parallel. A maximum of four instructions (ALU operation, multiply, and two data DSPS301S_010020030200 Rev. 1.00, 02/04, page 73 of 804 transfers) can be executed in parallel. For details, refer to section 3.5, DSP Data Operation Instructions. Notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes. Accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit instruction codes must be stored in memory, upper word and lower word, in this order, in word units. 2. In little endian, the upper and lower words must be stored in memory as data to be accessed in word units. 15 0000 CPU core instruction 12 11 0 * 1110 15 10 9 111100 0 A Field Double-data transfer instruction 15 Single-data transfer instruction 10 9 111101 A Field 0 31 DSP data operation instruction 26 25 111110 A Field 16 15 B Field 0 Figure 3.1 DSP Instruction Format Rev. 1.00, 02/04, page 74 of 804 3.2 3.2.1 DSP Mode Resources Processing Modes The CPU processing modes can be extended using the mode bit (MD) and DSP bit (DSP) of the status register (SR), as shown below. Description Access of Resources Protected in Privileged Mode or Privileged Instruction Execution Prohibited Prohibited Allowed MD Bit 0 0 1 1 DSP Bit 0 1 0 1 Processing Mode User mode User DSP mode Privileged mode DSP Extended Functions Invalid Valid Invalid Valid Privileged DSP mode Allowed As shown above, the extension of the DSP function by the DSP bit can be specified independently of the control by the MD bit. Note, however, that the DSP bit can be modified only in privileged mode. Before the DSP bit is modified, a transition to privileged mode or privileged DSP mode is necessary. 3.2.2 DSP Mode Memory Map In DSP mode, a part of the P2 area in the virtual address space can be accessed in user DSP mode (H'A5000000 to H'A5FFFFFF of H'A0000000 to H'BFFFFFFF can be accessed) as shown in figure 3.1. When this area is accessed in user DSP mode, this area is referred to as a Uxy area. X/Y memory is then assigned to this Uxy area. Accordingly, X/Y memory can also be accessed in user DSP mode. Table 3.1 Virtual Address Space Name P2/Uxy Protection Description Address Range H'A5000000 to H'A5FFFFFF Privileged mode 16-Mbyte physical address space, or DSP mode non-cacheable Can be accessed in privileged mode and DSP modes (privileged DSP mode and user DSP mode) Rev. 1.00, 02/04, page 75 of 804 3.2.3 CPU Register Sets In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three control registers: a repeat start register (SR), repeat end register (RE), and modulo register are added as control registers (figure 3.2). 31 0 31 30 29 28 27 RC[11:0] 16 15 0 14 0 13 12 11 10 9 8 Q 7 I3 6 I2 5 I1 4 I0 3 2 1 0 T MD RB BL 0 DSP DMY DMX M 0 RF1 RF0 S Status Register (SR) RS 31 0 Repeat Start register (RS) RE 31 16 15 0 Repeat End register (RE) ME MS MODulo register (MOD) Figure 3.2 CPU Registers in DSP Mode Rev. 1.00, 02/04, page 76 of 804 Extension of Status Register (SR): In DSP mode, the following control bits are added to the status register (SR). These added bits are called DSP extended bits. These DSP extended bits are valid only in DSP mode. Bit Bit Name Initial Value R/W R/W Description For details, refer to section 2, CPU. Repeat Counter Holds the number of repeat times in order to perform loop control, and can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, this bit is initialized to 0. This bit is not affected in the exception handling state. 15 to 13 12 DSP 0 R/W For details, refer to section 2, CPU. DSP Enables or disables the DSP extended functions. If this bit is set to 1, the DSP extended functions are enabled. This bit can be modified in privileged mode and privileged DSP mode; not in user DSP mode. At reset, this bit is initialized to 0. This bit is not affected in the exception handling state. 11 10 DMY DMX 0 0 R/W R/W Modulo Control Enable or disable modulo addressing for X/Y memory access. These bits can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, these bits are initialized to 0. These bits are not affected in the exception handling state. For details, refer to section 2, CPU. Repeat Flag Used by repeat control instructions. These bits can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, these bits are initialized to 0. These bits are not affected in the exception handling state. For details, refer to section 2, CPU. 31 to 28 27 to 16 RC11 to RC0 All 0 9 to 4 3 2 FR1 FR0 0 0 R/W R/W 1 to 0 Note: When data is written to the SR register, 0 should be written to reserved bits (bits 31, 15 to 13). Rev. 1.00, 02/04, page 77 of 804 Repeat Start Register (RS): RS holds the start address of the repeat loop that is controlled by the zero overhead repeat control function. This register can be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is not affected in the exception handling state. Repeat End Register (RE): RE holds the address for detecting the execution of the end instruction of repeat loop that is controlled by the zero overhead repeat control function. This register can be accessed in DSP mode. At reset, this register is initialized to 0. This register is not affected in the exception handling state. Modulo Register (MOD): MOD stores the modulo end address and modulo start address for modulo addressing in upper and lower 16 bits. The upper and lower 16 bits of the MOD register are referred to as the ME register and MS register, respectively. This register can be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is not affected in the exception handling state. The above registers can be accessed by the control register load instruction (LDC) and store instruction (STC). Note that the LDC and STC instructions for the RS, RE, and MOD registers can be used only in privileged DSP mode and user DSP mode. The LDC and STC instruction for the SR register can be executed only when the MD bit is set to 1 or in user DSP mode. Note, however, that the LDC and STC instructions can modify only the RC11 to RC0, RF1 to RF0, DMX, and DMY bits in the SR, as described below. * In user mode, if the LCD and STC instructions are used for the SR, an illegal instruction exception occurs. * In privileged and privileged DSP modes, all SR bits can be modified. * In user DSP mode, the SR can be read by the STC instruction. In user DSP mode, the LDC instruction can be issued to the SR but only the DSP extension bits can be modified. Rev. 1.00, 02/04, page 78 of 804 Table 3.2 Operation of SR Bits in Each Processing Mode Privileged Mode Privileged DSP Mode MD = 1 & DSP = 1 S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK User DSP Mode MD = 0 & DSP = 1 S: OK, L: NG S: OK, L: NG S: OK, L: NG R: OK, L: OK S: OK, L: NG R: OK, L: OK R: OK, L: OK S: OK, L: NG S: OK, L: NG S: OK, L: NG R: OK, L: OK S: OK, L: NG S: OK, L: NG SETRC instruction SETRC instruction Access to DSP-Related Bit with Dedicated Instruction User Mode MD = 0 & DSP = 0 S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction S, L: Illegal instruction Bit MD RB BL RC [11:0] DSP DMY DMX Q M I[3:0] RF[1:0] S T MD = 1 & DSP = 0 S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK S: OK, L: OK Initial Value after Reset 1 1 1 B'000000000000 0 0 0 x x B'1111 x x x Legend S: STC instruction L: LDC instruction OK: STC/LDC operation is enabled. Invalid instruction: Exception occurs when an illegal instruction is executed. NG: Previous value is retained. No change. x: Undefined Before entering the exception handling state, all bits including the DSP extended bits of the SR registers are saved in the SSR. Before returning from the exception handling, all bits including the DSP extended bits of the SR must be restored. If the repeat control must be recovered before entering the exception handling state, the RS and RE registers must be recovered to the value that existed before exception handling. In addition, if it is necessary to recover modulo control before entering the exception handling state, the MOD register must be recovered to the value that existed before exception handling. Rev. 1.00, 02/04, page 79 of 804 3.2.4 DSP Registers The DSP unit incorporates eight data registers (A0, A1, X0, X1, Y0, Y1, M0, and M1) and a status register (DSR). Figure 3.3 shows the DSP register configuration. These are 32-bit width registers with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits. The DSR register stores the DSP data operation result (zero, negative, others). The DSP register has a DC bit whose function is similar to the T bit of the CPU register. For details on DSR bits, refer to section 3.5, DSP Data Operation Instructions. 39 32 31 A0G A1G 0 A0 A1 M0 M1 X0 X1 Y0 Y1 (a) DSP data registers 31 12 11 ................ ................ ................ TS[2:0] Initial value DSR : All 0 Others: Undefined 9 8 7 6 Z 5 N 4 V 3 1 0 DC TC GT CS[2:0] (b) DSP status register (DSR) Figure 3.3 DSP Register Configuration Rev. 1.00, 02/04, page 80 of 804 3.3 3.3.1 CPU Extended Instructions DSP Repeat Control In DSP mode, a specific function, zero overhead repeat control function, is provided to execute repeat loops efficiently. By using this function, loop programs can be executed without overhead caused by the compare and branch instructions. When describing the repeat loop, the repeat control instructions in table 3.4, the repeat control macro instructions in table 3.5, and the DSP mode extended system control instructions in table 3.6 are used. Examples of Repeat Loop Programs: Examples of repeat loop programs are shown below. * Example 1: Repeat loop consisting of 4 or more instructions LDRS RptStart ; Sets repeat start instruction address to the RS register ; Sets (repeat detection instruction address + 4) to the RE register LDRE RptStart +4 SETRC #4 Instr0 ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from SETRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; ; [Repeat start instruction] Three instruction prior to the repeat end instruction is regarded as repeat detection instruction ; ; ; [Repeat end instruction] RptStart: instr1 ... ... ... ... RptDtct: instr(N-3) RptEnd2: RptEnd1: RptEnd: instr(N-2) instr(N-1) instrN In the above program example, instructions from the RptStart address (instr1 instruction) to the RptEnd address (instrN instruction) are repeated four times. These repeated instructions in the program are called repeat loop. The start and end instructions of the repeat loop are called the repeat start instruction and repeat end instruction, respectively. The CPU sequentially executes instructions and starts repeat loop control if the CPU detects the completion of a specific instruction. This specific instruction is called the repeat detection instruction. In a repeat loop consisting of four or more instructions, an instruction three instructions prior to the repeat end instruction is regarded as the repeat detection instruction. In a repeat loop consisting of four or Rev. 1.00, 02/04, page 81 of 804 more instructions, the same instruction is regarded as the RptStart instruction and RptDtct instruction. To control the repeat loop, the DSP extended control registers, such as the RE register and RS register and the RC[11:0] and RF[1:0] bits of the SR register, are used. These registers can be specified by the LDRE, LDRS, and SETRC instructions. * Repeat end register (RE) The RE register is specified by the LDRE instruction. The RE register specifies (repeat detection instruction address +4). In a repeat loop consisting of 4 or more instructions, an instruction three instructions prior to the repeat end instruction is regarded as the repeat detection instruction. A repeat loop consisting of three or less instructions is described later. * Repeat start register (RS) The RE register is specified by the LDRS instruction. In a repeat loop consisting of 4 or more instructions, the RS register specifies the repeat start instruction address. In a repeat loop consisting of three or less instructions, a specific address is specified in the RS. This is described later. * Repeat counter (RC[11:0] bits of the SR) The repeat counter is specifies the number of repetitions by the SETRC instruction. During repeat loop execution, the RC holds the remaining number of repetitions. * Repeat flags (RF[1:0] bits of the SR) The repeat flags are automatically specified according to the RS and RE register values during SETRC instruction execution. The repeat flags store information on the number of instructions included in the repeat loop. Normally, the user cannot modify the repeat flag values. The CPU always executes instructions by comparing the RE register to program counter values. Because the PC stores (the current instruction address +4), if the RE matches the PC during repeat instruction detection execution, a repeat detection instruction can be detected. If a repeat detection instruction is executed without branching and if RC[11:0] > 0, then repeat control is performed. If RC[11:0] 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and then control is passed to the address specified by the RS register. Examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two instructions, and one instruction, respectively. In these examples, an instruction immediately prior to the repeat start instruction is regarded as a repeat detection instruction. The RS register specifies the specific value that indicates the number of repeat instructions. Rev. 1.00, 02/04, page 82 of 804 * Example 2: Repeat loop consisting of three instructions LDRS RptStart +4 LDRE RptStart +4 SETRC #4 ; Sets (repeat detection instruction address + 4) to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; If RE-RS==0 during SETRC instruction execution, the repeat loop is regarded as three-instruction repeat. RptDtct: instr0 ; [Repeat start instruction] An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; [Repeat end instruction] RptStart: instr1 Instr2 RptEnd: instr3 * Example 3: Repeat loop consisting of two instructions LDRS RptStart +6 LDRE RptStart +4 SETRC #4 ; Sets (repeat detection instruction address + 6) to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; If RE-RS==-2 during SETRC instruction execution, the repeat loop is regarded as two-instruction repeat. RptDtct: instr0 ; [Repeat start instruction] An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; [Repeat end instruction] RptStart: instr1 RptEnd: instr2 Rev. 1.00, 02/04, page 83 of 804 * Example 4: Repeat loop consisting of one instruction LDRS RptStart +8 LDRE RptStart +4 SETRC #4 ; Sets (repeat detection instruction address + 8) to the RS register ; Sets (repeat detection instruction address + 4) to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; If RE-RS==-4 during SETRC instruction execution, the repeat loop is regarded as one-instruction repeat. RptDtct: instr0 ; [Repeat start instruction] An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. At least one instruction is required from LDRC instruction to [Repeat start instruction] RptStart: RptEnd: instr1 ; [Repeat start instruction] == [Repeat end instruction] In repeat loops consisting of three instructions, two instructions and one instruction, specific addresses are specified in the RS register. RE - RS is calculated during SETRC instruction execution, and the number of instructions included in the repeat loop is determined according to the result. A value of 0, -2,and -4 in the result correspond to 3 instructions, two instructions, and one instruction, respectively. If repeat instruction execution is completed without branching and if RC[11:0] > 0, an instruction following the repeat detection instruction is regarded as a repeat start instruction and instruction execution is repeated for the number of times corresponding to the recognized number of instructions. If RC[11:0] 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and then control is passed to the address specified by the RS register. If RC[11:0] ==1(or 0) when the repeat end instruction is completed, the RC[11:0] is cleared to 0 and then the control is passed to the next instruction following the repeat end instruction. Note: If RE - RS is a positive value, the CPU regards the repeat loop as a four-instruction repeat loop. (In a repeat loop consisting of four or more instructions, RE - RS is always a positive value. For details, refer to example 1 above.) If RE - RS is positive, or a value other than 0, -2,and -4, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 84 of 804 The rule is shown in table 3.3. Table 3.3 RS and RE Setting Rule Number of Instructions in Repeat Loop Register 1 RS RE RptStart0 + 8 RptStart0 + 4 2 RptStart0 + 6 RptStart0 + 4 3 RptStart0 + 4 RptStart0 + 4 4 RptStart RptEnd3 + 4 Note: The terms used above in table 3.3, are defined as follows. RptStart: Address of the repeat start instruction RptStart0: Address of the instruction one instruction prior to the repeat start instruction RptEnd3: Address of the instruction three instructions prior to the repeat end instruction Repeat Control Instructions and Repeat Control Macros: To describe a repeat loop, the RS and RE registers must be specified appropriately by the LDRS and LDRE instructions and then the number of repetitions must be specified by the SERTC instruction. An 8-bit immediate data or a general register can be used as an operand of the SETRC instruction. To specify the RC as a value greater than 256, use SETRC Rm type instructions. Table 3.4 Repeat Control Instructions Number of Execution States 1 1 Instruction LDRS @(disp,PC) LDRE @(disp,PC) SETRC #imm Operation Calculates (disp x 2 + PC) and stores the result to the RS register Calculates (disp x 2 + PC) and stores the result to the RE register Sets 8-bit immediate data imm to the RC[11:0] bits of the SR 1 register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 255. Sets the[11:0] bits of the Rm register to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 4095. 1 SETRC Rm The RS and RE registers must be specified appropriately according to the rules shown in table 3.3. The SH assembler supports control macros (REPEAT) as shown in table 3.5 to solve problems. Rev. 1.00, 02/04, page 85 of 804 Table 3.5 Instruction Repeat Control Macros Operation Number of Execution States REPEAT RptStart, RptEnd, #imm Specifies RptStart as repeat start instruction, 3 RptEnd as repeat end instruction, and 8-bit immediate data #imm as number of repetitions. This macro is extended to three instructions: LDRS, LDRE, and SETRC which are converted correctly. Specifies RptStart as repeat start instruction, RptEnd as repeat end instruction, and the [11:0] bits of Rm as number of repetitions. This macro is extended to three instructions: LDRS, LDRE, and SETRC which are converted correctly. 3 REPEAT RptStart, RptEnd, Rm Using the repeat macros shown in table 3.5, examples 1 to 4 shown above can be simplified to examples 5 to 8 as shown below. * Example 5: Repeat loop consisting of 4 or more instructions (extended to the instruction stream shown in example 1, above) REPEAT RptStart, RptEnd, #4 Instr0 RptStart: instr1 ... ... ... ... instr (N-3) instr (N-2) instr (N-1) RptEnd: instrN ; ; [Repeat start instruction] ; ; ; [Repeat detection instruction] ; ; ; [Repeat end instruction] * Example 6: Repeat loop consisting of three instructions (extended to the instruction stream shown in example 2, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: instr1 Instr2 RptEnd: instr3 ; [Repeat detection instruction] ; [Repeat start instruction] ; ; [Repeat end instruction] Rev. 1.00, 02/04, page 86 of 804 * Example 7: Repeat loop consisting of two instructions (extended to the instruction stream shown in example 3, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: instr1 RptEnd: instr2 ; [Repeat detection instruction] ; [Repeat start instruction] ; [Repeat end instruction] * Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction stream shown in example 3, above) REPEAT RptStart, RptEnd, #4 instr0 RptStart: RptEnd: instr1 ; [Repeat start instruction] == [Repeat end instruction] ; [Repeat detection instruction] In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC and STC instructions for the SR register. These instructions should be used if an exception is enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception handling and by restoring the stored values after exception handling. However, note that there are some restrictions on exception acceptance during repeat loop execution. For details refer to section 3.3.1 (3), Restrictions on Repeat Loop Control and section 4, Exception Handling. Table 3.6 Instruction STC RS, Rn STC RE, Rn STC.L RS, @-Rn STC.L RE, @-Rn LDC.L @Rn+, RS LDC.L @Rn+, RE LDC Rn,RS LDC Rn, RE DSP Mode Extended System Control Instructions Operation RSRn RERn Rn-4Rn, RS(Rn) Rn-4Rn, RE(Rn) (Rn)RS, Rn+4Rn (Rn)RE, Rn+4Rn RnRS RnRE Number of Execution States 1 1 1 1 4 4 4 4 Rev. 1.00, 02/04, page 87 of 804 Restrictions on Repeat Loop Control 1. Repeat control instruction assignment The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In addition, note that at least one instruction is required between the SETRC instruction and a repeat start instruction. 2. Illegal instruction one or more instructions following the repeat detection instruction If one of the following instructions is executed between an instruction following a repeat detection instruction to a repeat end instruction, an illegal instruction exception occurs. Branch instructions BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA Repeat control instructions SETRC, LDRS, LDRE Load instructions for SR, RS, and RE registers LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS Note: This restriction applies to all instructions for a repeat loop consisting of one to three instructions and to three instructions including a repeat end instruction. 3. Instructions prohibited during repeat loop (In a repeat loop consisting of four or more instructions) The following instructions must not be placed between the repeat start instruction and repeat detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the correct operation cannot be guaranteed. Repeat control instructions SETRC, LDRS, LDRE Load instructions for SR, RS, and RE registers LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control instructions, and the external loop by other instructions such as DT or BF/S. 4. Branching to an instruction following the repeat detection instruction and restriction on an exception acceptance Execution of a repeat detection instruction must be completed without any branch so that the CPU can recognize the repeat loop. Therefore, when the execution branches to an instruction following the repeat detection instruction, the control will not be passed to a repeat start instruction after executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this case, the RC[11:0] bits of the SR register will not be changed. If a conditional branch instruction is used in the repeat loop, an instruction before a repeat detection instruction must be specified as a branch destination. Rev. 1.00, 02/04, page 88 of 804 If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call instruction must be placed before a repeat detection instruction. Here, a branch includes a return from an exception handling routine. If an exception whose return address is placed in an instruction following the repeat detection instruction occurs, the repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a transition to an exception occurs but a program cannot be returned to the previous execution state correctly. For details, refer to section 4, Exception Handling. Notes: 1. If a TRAPA instruction is used as a repeat detection instruction, an instruction following the repeat detection instruction is regarded as a return address. In this case, a control cannot be returned to the repeat control correctly. In a TRAPA instruction, an address of an instruction following the repeat detection address is regarded as return address. Accordingly, to return to the repeat control correctly, place a return address prior to the repeat detection instruction. 2. If a SLEEP instruction is placed following a repeat detection instruction, a transition to the power-down state or an exception acceptance such as interrupts can be performed correctly. In this case, however, the repeat control cannot be returned correctly. To return to the repeat control correctly, the SLEEP instruction must be placed prior to the repeat detection instruction. 5. Branch from a repeat detection instruction If a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a branch instruction, a repeat loop can be acknowledged when a branch does not occur in a branch instruction. If a branch occurs in a branch instruction, a repeat control is not performed and a branch destination instruction is executed. 6. Program counter during repeat control If RC[11:0] 2, the program counter (PC) value is not correct for instructions two instructions following a repeat detection instruction. In a repeat loop consisting of one to three instructions, the PC indicates the correct value (instruction address + 4) for an instruction (repeat start instruction) following a repeat detect ion instruction but the PC continues to indicate the same address (repeat start instruction address) from the subsequent instruction to a repeat end instruction. In a repeat loop consisting of four or more instructions, the PC indicates the correct value (instruction address + 4) for an instruction following a repeat detect ion instruction, but PC indicates the RS and (RS +2) for instructions two and three instructions following the repeat detection instruction. The correct operation cannot be guaranteed for the incorrect PC values. Accordingly, PC relative addressing instructions placed two or more instructions following the repeat detection instruction cannot be executed correctly and the correct results cannot be obtained. Rev. 1.00, 02/04, page 89 of 804 PC relative addressing instructions MOV.A @(disp, PC), Rn MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn (Including the case when the MOV #imm,Rn is extended to MOV.W @(disp, PC), Rn or MOV.L @(disp, PC), Rn) Table 3.7 PC Value during Repeat Control (When RC[11:0] 2) Number of Instructions in Repeat Loop 1 RptDtct RptDtct + 4 2 RptDtct + 4 RptDtct1+ 4 RptDtct1+ 4 3 RptDtct + 4 RptDtct1 + 4 RptDtct1 + 4 RptDtct1 + 4 4 RptDtct +4 RptDtct1 + 4 RS RS + 2 RptDtct1 RptDtct1 + 4 RptDtct2 RptDtct3 Note: In table 3.7, the following symbols are used. RptDtct: An address of the repeat detection instruction RptDtct1: An address of the instruction one instruction following the repeat start instruction (In a repeat loop consisting of one to three instructions, RptStart is a repeat start instruction) RptDtct2: An address of the instruction two instruction following the repeat start instruction RptDtct3: An address of the instruction three instruction following the repeat start instruction 7. Repeat counter and repeat control The CPU always executes a program with comparing the repeat end register (RE) and the program counter (PC). If the PC matches the RE while the RC[11:0] bits of the SR register are other than 0, the repeat control function is initiated. If RC 2, a control is passed to a repeat start instruction after a repeat end instruction has been executed. The RC is decremented by 1 at the completion of the repeat end instruction. In this case, restrictions (a) to (f) are also applied. If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and a control is passed to the subsequent instruction. In this case, restrictions (a) to (f) are also applied. If RC == 0, the repeat control function is not initiated even if a repeat detection instruction is executed. The repeat loop is executed once as normal instructions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed. Rev. 1.00, 02/04, page 90 of 804 3.3.2 Extended Repeat Control Instructions In the repeat control function described in section 3.3.1, Repeat Control Instructions, there are some restrictions. To reduce these restrictions, this LSI supports the extended repeat instructions to extend the repeat control function that are shown in table 3.8. These extended repeat control instructions were not supported in the conventional SH-DSP. To keep compatibility with the conventional SH-DSP, use the conventional repeat control instructions called compatible repeat control instructions. Program Examples Using the Extended Repeat Control Instructions: Examples of repeat loop programs using the extended repeat control instructions are shown below. * Example 1: Repeat loop consisting of 4 or more instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; ; [Repeat detection instruction] An instruction three instructions prior to the repeat end instruction is regarded as a repeat detection instruction. ; ; ; [Repeat end instruction] RptStart: instr1 ... ... ... ... instr(N-3) instr(N-2) instr(N-1) RptEnd: instrN Rev. 1.00, 02/04, page 91 of 804 * Example 2: Repeat loop consisting of three instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; [Repeat detection instruction] An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; ; [Repeat end instruction] RptStart: instr1 instr2 RptEnd: instr3 * Example 3: Repeat loop consisting of two instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; [Repeat detection instruction] An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction] ; [Repeat end instruction] RptStart: instr1 RptEnd: instr2 Rev. 1.00, 02/04, page 92 of 804 * Example 4: Repeat loop consisting of two instructions LDRS RptStart LDRE RptEnd LDRC #4 instr0 ; Sets repeat start instruction address to the RS register ; Sets repeat end instruction address to the RE register ; Sets the number of repetitions (4) to the RC[11:0] bits of the SR register ; [Repeat detection instruction] An instruction prior to the Repeat start instruction is regarded as a repeat detection instruction. At least one instruction is required from LDRC instruction to [Repeat start instruction] ; [Repeat start instruction]== [Repeat end instruction] RptStart: RptEnd: instr1 In extended repeat control instructions, a repeat start instruction address and a repeat end instruction address are stored in the RS register and RE register, respectively, regardless of the number of repeat instructions. In addition, the extended repeat control can be performed by using the LDRC instruction instead of the SETRC instruction. During the extended repeat control, a repeat loop can be recognized by executing a repeat end instruction. Therefore, there is no restriction on branches or exceptions. Extended Repeat Control Instructions: To describe the extended repeat loop, the repeat start and end addresses must be specified to the RS and RE registers by the LDRS and LDRE instructions, respectively. For the LDRS and LDRE instructions of the extended repeat control instructions, the LDRS and LDRE instructions of the compatible repeat control instructions are used. The number of repetitions are specified by the LDRC instruction. An 8-bit immediate data or the general register values can be used as an operand of the LDRC instruction. If 256 or greater value is specified to the RC, use the LDRC Rm type instructions. Rev. 1.00, 02/04, page 93 of 804 Table 3.8 Instruction Extended Repeat Control Instructions Operation Calculates (disp x 2 + PC) and stores the result to the RS register Calculates (disp x 2 + PC) and stores the result to the RE register Sets 8-bit immediate data imm to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 255. During extended repeat control, bit 0 of the RE register is set to 1. Number of Execution States 1 1 1 LDRS @(disp,PC) LDRE @(disp,PC) LDRC #imm LDRC Rm Sets the[11:0] bits of the Rm register to the RC[11:0] bits of the SR register and sets the information related to the number of repetitions to the RF[1:0] bits of the SR. RC[11:0] can be specified as 0 to 4095. During extended repeat control, bit 0 of the RE register is set to 1. 1 By executing the LDRC instruction, the CPU performs the extended repeat control function. To indicate that the CPU is being in extended repeat control, bit 0 of the RE register is set to 1 by executing the LDRC instruction. To change the RE register value by a process such as an exception handling, bit 0 of the RE register must be saved and restored correctly. By saving and restoring the RC[11:0] bits, DSP bit, and RF[1:0] bits of the SR register, RE register, and RS register correctly, a control is returned to the extended repeat function correctly after processing such as exception handling. Rev. 1.00, 02/04, page 94 of 804 Restrictions on Extended Repeat Loop Control: 1. Extended repeat control instruction assignment The LDRC instruction must be executed after executing the LDRS and LDRE instructions. In addition, note that at least one instruction is required between the LDRC instruction and a repeat start instruction. 2. Illegal instruction one or more instructions following the repeat end instruction If one of the following instructions is executed as a repeat end instruction, an illegal instruction exception occurs. Delayed branch instructions BRA, BSR, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP Repeat control instructions SETRC, LDRS, LDRE, LDRC Load instructions for SR, RS, and RE registers LCD Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS Note: A branch instruction without delay (BT, BF, TRAPA) can be placed as a repeat end instruction. A delay stop of a delayed branch instruction can also be placed as a repeat end instruction. In this case, the RC[11:0] value is decremented by 1 regardless of branch occurrence. If no branch occurs, a control returns to a repeat start instruction. If a branch occurs, a control is passed to a branch destination. 3. Repeat counter and repeat control The CPU always execute a program with comparing the repeat end register (RE) and the (PC - 4) (current instruction address). If the (PC - 4) [31:1] matches the RE [31:1] while bit 0 of RE register is set to 1, the extended repeat control function is initiated. If RC 2, a control is passed to a repeat start instruction after a repeat end instruction has been executed. The RC is decremented by 1 at the completion of the repeat end instruction. If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and a control is passed to the subsequent instruction. If RC == 0, the repeat control function is not initiated even if a repeat detection instruction is executed. The repeat loop is executed once as normal instructions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed. Rev. 1.00, 02/04, page 95 of 804 3.4 DSP Data Transfer Instructions In DSP mode, data transfer instructions are added for the DSP unit registers. The newly added instructions are classified into the following three groups. 1. Double data transfer instructions The DSP unit is connected to the X memory and Y memory via the specific buses called X bus and Y bus. By using the data transfer instructions using the X and Y buses, two data items can be transferred between the DSP unit and X/Y memories simultaneously. These instructions are called double data transfer instructions. These double data transfer instructions can be described in combination with the DSP operation instructions to execute data transfer and data operation in parallel. 2. Single data transfer instructions The DSP unit is also connected to the L bus that is used by the CPU. The DSP registers other than the DSR can access any virtual addresses generated by the CPU. In this case, the single data transfer instructions are used. The single data transfer instructions cannot be used in combination with the DSP operation instructions and can access only one data item at a time. 3. System control instructions Some of the DSP unit registers are handled as the CPU system registers. To control these system registers, the system control registers are supported. The DSP registers are connected to the CPU general registers via the data transfer bus (C bus). In any DSP data transfer instructions, an address to be accessed is generated and output by the CPU. For DSP data transfer instructions, some of the CPU general registers are used for address generation and specific addressing modes are used. Rev. 1.00, 02/04, page 96 of 804 CPU LAB [31:0] XAB [15:0] YAB [15:0] DSP unit XDB [15:0] YDB [15:0] CDB [31:0] DSR A0G A0 A1G A1 M0 M1 X0 X1 Y0 Y1 LDB [31:0] X memory Y memory Legend XAB : X bus (address) XDB : X bus (data) YAB : Y bus (address) YDB : Y bus (data) LAB : L bus (address) LDB : L bus (data) CDB : C bus (data) Figure 3.4 DSP Registers and Bus Connections Double data transfer instructions (MOVX.W, MOVY.W, MOVX.L, and MOVY.L): Instruction formats of double data transfer instructions are shown in table 3.12. With double data transfer group instructions, X memory and Y memory can be accessed in parallel. In this case, the specific buses called X bus and Y bus are used to access X memory and Y memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict occurs among X, Y, and L buses. Load instructions for X memory specify the X0 or X1 register as the destination operand. Load instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers for X or Y memory specify the A0 or A1 register as the source operand. The double data transfer instructions use only word data (16 bits). When a word data transfer instruction is executed, the upper word of register operand is used. To load word data, data is loaded to the upper word of the destination register and the lower word of the destination register is automatically cleared to 0. Double data transfer instructions can be described in parallel to the DSP operation instructions. Even if a conditional operation instruction is specified in parallel to a double data transfer Rev. 1.00, 02/04, page 97 of 804 instruction, the specified condition does not affect the data transfer operations. For details, refer to section 3.5, DSP Data Operation Instructions. Double data transfer instructions can access only the X memory or Y memory and cannot access other memory space. The X bus and Y bus are 16 bits and support 64-kbyte address spaces corresponding to address areas H'A5000000 to H'A500FFFF and H'A5010000 to H'A501FFFF, respectively. Because these areas are included in the P2/Uxy area, they are not affected by the cache and address translation unit. Single data transfer instructions: The instruction formats of single data transfer instructions are shown in table 3.13. The single data transfer instructions access any memory location. All DSP registers* other than the DSR can be specified as source and destination operands. Guard bit registers A0G and A1G can also be specified as two independent registers. Because the single data transfer instructions use the L bus (LAB and LDB), these instructions can access any virtual space handled by the CPU. If these instructions access the cacheable area while the cache is enabled, the area accessed by these instructions are cached. The X memory and Y memory are mapped to the virtual address space and can also be accessed by the single data transfer instructions. In this case, bus conflict may occur between data transfer and instruction fetch because the CPU also uses the L bus for instruction fetches. The single data transfer instructions can handle both word and longword data. In word data transfer, only the upper word of the operand register is valid. In word data load, word data is loaded into the upper word of the destination registers and the lower word of the destination is automatically cleared to 0. If the guard bits are supported, the sign bit is extended before storage. In longword data load, longword data is loaded into the upper and lower word of the destination register. If the guard bits are supported, the sign bit is extended before storage. When the guard register is stored, the sign bit is extended to the upper 24 bits of the LDB and are loaded onto the LDB bus. Notes: * Because the DSR register is defined as the system register, it can be accessed by the LDS or STS instruction. 1. Any data transfer instruction is executed at the MA stage of the pipeline. 2. Any data transfer instruction does not modify the condition code bits of the DSR register. System control instructions: The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can also be used as the CPU system registers. Accordingly, data transfer operations between these DSP system registers and general registers or memory can be executed by the STS and LDS instructions. These DSP system registers can be treated as the CPU system register such as PR, MACL and MACH and can use the same addressing modes. Rev. 1.00, 02/04, page 98 of 804 Table 3.9 Instruction STS STS STS STS STS STS STS.L STS.L STS.L STS.L STS.L STS.L LDS.L LDS.L LDS.L LDS.L LDS.L LDS.L LDS LDS LDS LDS LDS LDS Extended System Control Instructions in DSP Mode Operation DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Rn Rn - 4 Rn, DSR (Rn) Rn - 4 Rn, A0 (Rn) Rn - 4 Rn, X0 (Rn) Rn - 4 Rn, X1 (Rn) Rn - 4 Rn, Y0 (Rn) Rn - 4 Rn, Y1 (Rn) (Rn) DSR, Rn + 4 Rn (Rn) A0, Rn + 4 Rn (Rn) X0, Rn + 4 Rn (Rn) X1, Rn + 4 Rn (Rn) Y0, Rn + 4 Rn (Rn) Y1, Rn + 4 Rn Rn DSR Rn A0 Rn X0 Rn X1 Rn Y0 Rn Y1 Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DSR,Rn A0,Rn X0,Rn X1,Rn Y0,Rn Y1,Rn DSR,@-Rn A0,@-Rn X0,@-Rn X1,@-Rn Y0,@-Rn Y1,@-Rn @Rn+,DSR @Rn+,A0 @Rn+,X0 @Rn+,X1 @Rn+,Y0 @Rn+,Y1 Rn,DSR Rn,A0 Rn,X0 Rn,X1 Rn,Y0 Rn,Y1 3.4.1 General Registers The DSP instructions 10 general registers in the 16 general registers as address pointers or index registers for double data transfers and single data transfers. In the following descriptions, another register function in the DSP instructions is also indicated within parentheses [ ]. * Double data transfer instructions (X memory and Y memory are accessed simultaneously) In double data transfers, X memory Y memory can be accessed simultaneously. To specify X and Y memory addresses, two address pointers are supported. Rev. 1.00, 02/04, page 99 of 804 Memory to be Accessed Address Pointer X memory (MOVX.W) Y memory (MOVY.W) R4,R5[Ax] R6,R7[Ay] Index Register R8 [Ix] R9 [Iy] * Single data transfer instructions In single data transfer, any virtual address space can be accessed via the L bus. The following address pointers and index registers are used. Address to be Accessed Any virtual space (MOVS.W/L) Address Pointer R4,R5, R2, R3[As] Index Register R8 [Is] 31 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R0 R10 R11 R12 R13 R14 R15 0 General registers (DSP mode) [As2] [As3] [As0] [As1, Ax1] [Ay0] [Ay1] [Ix, Is] [Iy] Double data transfers: R4, 5 R8 R6, 7 R9 [Ax] : Address register set for the X memory [Ix] : Index register for X address register set Ax [Ay] : Address register set for the Y memory [Iy] : Index register for Y address register set Ay Single data transfers: R4, 5, 2, 3 [As] : Address register set for all data memories R8 [Is] : Index register used for single data transfers Figure 3.5 General Registers (DSP Mode) In assembler, R0 to R9 are used as symbols. In the DSP data transfer instructions, the following register names (alias) can also be used. In assembler, described as shown below. Ix: .REG (R8) Ix indicates the alias of register 8. Other aliases are shown below. Ax0: .REG (R4) Ax1: .REG (R5) Ix: .REG (R8) Ay0: .REG (R6) Ay1: .REG(R7) Rev. 1.00, 02/04, page 100 of 804 Iy: .REG (R9) As0: .REG (R4); This definition is used for if the alias is required in the single data transfer As1: .REG (R5) ; This definition is used for if the alias is required in the single data transfer As2: .REG (R2) As3: .REG (R3) Is: .REG (R8) ; This definition is used for if the alias is required in the single data transfer 3.4.2 DSP Data Addressing Table 3.10 shows the relationship between the double data transfer instructions and single data transfer instructions. Table 3.10 Overview of Data Transfer Instructions Double Data Transfer Instructions MOVX.W, MOVY.W Address register Index register Addressing Ax: R4, R5, Ay: R6, R7 Ix: R8, Iy: R9 Nop/Inc (+2)/index addition: post-increment -- Modulo addressing Data bus Data length Bus conflict Memory Source register Destination register Possible XDB, YDB 16 bits (word) No X/Y data memory Dx, Dy: A0, A1 Dx: X0/X1 Dy: Y0/Y1 Single Data Transfer Instructions MOVS.W, MOVS.L As: R2, R3, R4, R5 Is: R8 Nop/Inc (+2, +4)/index addition: post-increment Dec (-2, -4): pre-decrement Not possible LDB 16/32 bits (word/longword) Yes Entire memory space Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Rev. 1.00, 02/04, page 101 of 804 Addressing Mode for Double Data Transfer Instructions: The double data transfer instructions supports the following three addressing modes. * Non-update address register addressing The Ax and Ay registers are address pointers. They are not updated. * Increment address register addressing The Ax and Ay registers are address pointers. After a data transfer, they are each incremented by 2 (post- increment). * Addition index register addressing The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy register is added to each (post-increment). The double data transfer instructions do not supports decrement addressing mode. To perform decrementing, -2 is set in the index register and addition index register addressing is specified. When using X/Y memory addressing, bit 0 of the address pointer is invalid. Accordingly, bit 0 of the address pointer and index register must be cleared to 0 in X/Y memory addressing. If 1 is written to the bit, correct operation cannot be guaranteed. When accessing X and Y memories using the X and Y buses, the upper word of Ax and Ay are ignored. The result of Ay + 2 or Ay + Iy is stored in the lower word of Ay, while the upper word retains its original value. The Ax + 2 and Ax + Ix operations are executed in longword (32 bits) and the upper word may be changed according to the result. Addressing Mode for Single Data Transfer Instructions: The following four kinds of addressing can be used with single data transfer instructions. * Non-update address register addressing The As register is an address pointer. An access to @As is performed but As is not updated. * Increment address register addressing: The As register is an address pointer. After an access to @As, the As register is incremented by 2 or 4 (post-increment). * Addition index register addressing: The As register is an address pointer. After an access to @As, the value of the Is register is added to the As register (post-increment). * Decrement address register addressing: The As register is an address pointer. Before a data transfer, -2 or -4 is added to the As register (i.e. 2 or 4 is subtracted) (pre-decrement). In single data transfer instructions, all bits in 32-bit address are valid. Rev. 1.00, 02/04, page 102 of 804 3.4.3 Modulo Addressing In double data transfer instructions, a modulo addressing can be used. The modulo addressing control instructions are listed in table 3.11. If the address pointer value reaches the preset modulo end address while a modulo addressing mode is specified, the address pointer value becomes the modulo start address. To control modulo addressing, the modulo register (MOD) extended in the DSP mode and the DMX and DMY bits of the SR register are used. The MOD register is provided to set the start and end addresses of the modulo address area. The upper and lower words of the MOD register store modulo start address (MS) and modulo end address (ME), respectively. The LDC and STC instructions are extended for MOD register handling. If the DMX bit of the SR register is set, the modulo addressing is specified for the X address register. If the DMY bit of the SR register is set, the modulo addressing is specified for the Y address register. Modulo addressing is valid for either the X or the Y address register, only; it cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set simultaneously (if they are, the DMY setting will be valid). (In the future, this specification may be changed.) The DMX and MDY bits of the SR can be specified by the STC or LDC instruction for the SR register. If an exception is accepted during modulo addressing, the MDX and MDY bits of the SR and MOD register must be saved. By restoring these register values, a control is returned to the modulo addressing after an exception handling. Table 3.11 Modulo Addressing Control Instructions Instruction STC MOD,Rn Operation MOD Rn Rn - 4 Rn, MOD (Rn) (Rn) Rn, Rn + 4 Rn Rn MOD Execution States 1 1 4 4 STC.L MOD,Rn LDC LDC @Rn+,MOD Rn+,MOD Rev. 1.00, 02/04, page 103 of 804 An example of the use of modulo addressing is shown below. MOV.L #H'70047000, R10 LDC Rn,MOD STC SR, R10 ;Specify MS=H'7000 ME = H'7004 ;Specify ME:MS to MOD register ; ; ; MOV.L #H'FFFFF3FF, R11 MOV.L #H'00000400, R12 AND R11, R10 OR R12, R10 LDC R10, SR ; ; ; Specify SR.MDX=1, SR.MDY=0, and X modulo addressing mode MOV.L #H'A5007000, R14 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVX.W @R4+,X0 ; R4: H'A5007000 H'A5007002 ; R4: H'A5007002 H'A5007004 ; R4: H'A5007004 H'A5007000 (Matches to ME and MS is set) ; R4: H'A5007000 H'A5007002 The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1. When the X or Y data transfer instruction specified by the DMX or DMY is executed, the address register contents before updating are compared with ME*, and if they match, start address MS is stored in the address register as the value after updating. When the addressing type of the X/Y data transfer instruction is no-update, the X/Y data transfer instruction is not returned to MS even if they match ME. When the addressing type of the X/Y data transfer is adding index register, address pointer is may not match and exceed ME. In this case, the modulo start address is not set as the address pointer. The maximum modulo size is 64 kbytes. This is sufficient to access the X and Y data memory. Note: Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and ME. Rev. 1.00, 02/04, page 104 of 804 3.4.4 Memory Data Formats Memory data formats that can be used in the DSP instructions are classified into word and longword. An address error will occur if word data starting from an address other than 2n is accessed by MOVS.W instruction or longword data starting from an address other than 4n is accessed by MOVS.L, LDS.L, or STS.L instruction. In such cases, the data accessed cannot be guaranteed An address error will not occur if word data starting from an address other than 2n is accessed by the MOVX.W or MOVY.W instruction. When using the MOVX.W or MOVY.W instruction, an address must be specified on the boundary 2n. If an address is specified other than 2n, the data accessed cannot be guaranteed. 3.4.5 Instruction Formats of Double and Single Data Transfer Instructions The format of double data transfer instructions is shown in tables 3.12, and that of single data transfer instructions in table 3.13. Table 3.12 Double Data Transfer Instruction Formats Type Mnemonic 15 14 13 12 11 10 9 1 1 1 1 0 0 0 Ax 8 7 0 Dx 6 5 0 0 4 3 0 0 1 1 Da 1 0 1 1 1 1 1 1 0 0 0 Ay 0 Dy 0 0 2 0 1 0 1 1 0 1 0 0 1 1 Da 1 0 1 1 0 1 0 1 1 0 1 1 0 X memory NOPX data MOVX.W @Ax,Dx transfer MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix Y memory NOPY data MOVY.W @Ay,Dy transfer MOVY.W @Ay+,Dy MOVY.W @Ay+Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay+ MOVY.W Da,@Ay+Iy Note: Ax: 0 = R4, 1 = R5 Ay: 0 = R6, 1 = R7 Dx: 0 = X0, 1 = X1 Dy: 0 = Y0, 1 = Y1 Da: 0 = A0, 1 = A1 Rev. 1.00, 02/04, page 105 of 804 Table 3.13 Single Data Transfer Instruction Formats Type Single data transfer Mnemonic MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As+ MOVS.L Ds,@As+ls Note: * Codes reserved for system use. 15 14 13 12 11 10 9 1 1 1 1 0 1 As 0:R4 1:R5 2:R2 3:R3 8 7 6 5 1:(*) 2:(*) 3:(*) 4:(*) 5:A1 6:(*) 7:A0 8:X0 9:X1 A:Y0 B:Y1 C:M0 D:A1G E:M1 F:A0G 4 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0 Ds 0:(*) Rev. 1.00, 02/04, page 106 of 804 3.5 3.5.1 DSP Data Operation Instructions DSP Registers There are eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register (DSR) as DSP registers (figure 3.3). Four kinds of operation access the DSP data registers. The first is DSP data processing. When a DSP fixed-point arithmetic operation instruction uses A0 or A1 as the source register, it uses the guard bits (bits 39 to 32). When it uses A0 or A1 as the destination register, guard bits 39 to 32 are valid. When a DSP fixed-point arithmetic operation instruction uses a DSP register other than A0 or A1 as the source register, it sign-extends the source register value to bits 39 to 32. When it uses one of these registers as the destination register, bits 39 to 32 of the result are discarded. The second kind of operation is an X or Y data transfer operation, MOVX.W, MOVY.W. This operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 3.4). The register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16). X0 or X1 can be the destination register of an X memory load and Y0 or Y1 can be the destination of a Y memory load, but no other register can be the destination register in this operation. When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but no other registers can be stored. The third kind of operation is a single-data transfer instruction, MOVS.W or MOVS.L. These instructions access any memory location through the LDB (figure 3.4). All DSP registers connect to the LDB and can be the source or destination register of the data transfer. These instructions have word and longword access modes. In word mode, registers to be loaded or stored by this instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G. When data is loaded into a register other than A0G and A1G in word mode, the lower half of the register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39-32 and the lower half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an 8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0 or A1, it is sign-extended to bits 39 to 32. The fourth kind of operation is system control instructions such as LDS, STS, LDS.L, or STS.L. The DSR, A0, X0, X1, Y0, and Y1 registers of the DSP register can be treated as system registers. For these registers, data transfer instructions between the CPU general registers and system registers or memory access instructions are supported. Tables 3.14 and 3.15 show the data type of registers used in DSP instructions. Some instructions cannot use some registers shown in the tables because of instruction code limitations. For example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details of register selectability. Rev. 1.00, 02/04, page 107 of 804 Table 3.14 Destination Register in DSP Instructions Guard Bits Registers A0, A1 Instructions DSP operation Fixed-point, PSHA, PMULS Integer, PDMSB Logical, PSHL Data transfer A0G, A1G Data transfer DSP operation MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PSHA, PMULS Integer, logical, PDMSB, PSHL Data transfer MOVX/Y.W, MOVS.W MOVS.L 39 32 31 Register Bits 16 15 0 Sign-extended 40-bit result Sign-extended 24-bit result Cleared 16-bit result Cleared Cleared Cleared Sign-extended 16-bit data Sign-extended 32-bit data 8-bit data 8-bit data No update No update 32-bit result 16-bit result 16-bit data 32-bit data X0, X1 Y0, Y1 M0, M1 Cleared Cleared Table 3.15 Source Register in DSP Operations Guard Bits Registers A0, A1 Instructions DSP operation Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer A0G, A1G Data transfer DSP operation MOVX/Y.W, MOVS.W MOVS.L MOVS.W MOVS.L Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data transfer Note: * MOVS.W MOVS.L 8-bit data 8-bit data Sign* Sign* 32-bit data 16-bit data 16-bit data 16-bit data 32-bit data 39 40-bit data 24-bit data 16-bit data 16-bit data 32-bit data 32 31 Register Bits 16 15 0 X0, X1 Y0, Y1 M0, M1 The data is sign-extended and input to the ALU. Rev. 1.00, 02/04, page 108 of 804 The DSP unit incorporates the DSP status register (DSR) which is used as a control register. The DSR register stores the DSP data operation result (zero, negative, others). The DSR register also has the DC bit whose function is similar to the T bit of the CPU register. The DC bit functions as status flag. Conditional DSP data operations are controlled based on the DC bit. These operation control affects only the DSP unit instructions. In other words, these operations control affects only the DSP registers and does not affect address register update and CPU instructions such as load and store instructions. A condition to be reflected on the DC bit should be specified to the DC status selection bits (CS[2:0]). The unconditional DSP type data operation instructions other than PMULS, MOVX, MOVY, and MOVS change the condition flag and DC bit. However, the CPU instructions including the MAC instruction do not modify the DC bit. In addition, conditional DSP data operation instructions do not modify the DSR. Table 3.16 DSR Register Bits Bits Bit Name Initial Value All 0 R/W R Function Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 11 to 9 TS2 to TS0 All 0 R/W T Bit Status Selection Specifies the operation result status to be set in the T bit in the SR register if the TC bit is 1. If the S bit of the SR register is set to 1, an overflow is detected. 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed greater than or equal to mode 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) 8 TC 0 R/W TC Bit 0: The T bit of the SR register is not affected by the DSP instruction. 1: The T bit of the SR register changes according to the TS bit of the DSR register while the DSP instruction is executed. Note, however, the T bit does not change during conditional DSP instruction execution. Rev. 1.00, 02/04, page 109 of 804 31 to 12 Bits 7 Bit Name GT Initial Value 0 R/W R/W Function Signed Greater Bit Indicates that the operation result is positive (except 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater than operand 2 6 Z 0 R/W Zero Bit Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: Operation result is zero (0), or operands are equal 5 N 0 R/W Negative Bit Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: Operation result is negative, or operand 1 is smaller than operand 2 4 V 0 R/W Overflow Bit Indicates that the operation result has overflowed 1: Operation result has overflowed 3 to 1 CS All 0 R/W DC Bit Status Selection Designate the mode for selecting the operation result status to be set in the DC bit 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed greater than or equal to mode 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) Rev. 1.00, 02/04, page 110 of 804 Bits 0 Bit Name DC Initial Value 0 R/W R/W Function DSP Status Bit Sets the status of the operation result in the mode designated by the CS bits 0: Designated mode status has not occurred (false) 1: Designated mode status has occurred Indicates the operation result by carry or borrow regardless of the CS bit status after the PADDC or PSUBC instruction has been executed. The DSR is assigned to the system registers. For the DSR, the following load and store instructions are supported. STS DSR,Rn; STS.L DSR,@-Rn; LDS Rn,DSR; LDS.L @Rn+,DSR; If the DSR is read by the STS instruction, upper bits (bits 31 to 16) are all 0 3.5.2 DSP Instruction Set DSP instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field. Instructions can be specified independently, and are also executed independently. B-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. The formats of the DSP operation instructions are shown in table 3.17. The respective operands are selected independently from the DSP registers. The correspondence between DSP instruction operands and registers is shown in table 3.18. Parallel processing only instructions in the A field (without those in the B field) can be executed (transferring data in parallel without DSP data operation instructions). Rev. 1.00, 02/04, page 111 of 804 Table 3.17 DSP Instruction Formats Type Double data operation instructions Single data operation instructions Conditional single data DCT operation instructions DCF DCT DCF DCT DCF Unconditional single data operation instructions Instruction Formats ALUop. Sx, Sy, Du MLTop. Se, Df, Dg ALUop. Sx, Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz ALUop. Sx, Dz ALUop. Sy, Dz ALUop. Sy, Dz ALUop. Sx, Sy, Dz ALUop. Sx, Dz ALUop. Sy, Dz MLTop. Se, Sf, Dg Table 3.18 Correspondence between DSP Instruction Operands and Registers ALU, Shift Operations Register A0 A1 M0 M1 X0 X1 Y0 Y1 Sx Yes Yes Yes Yes Sy Yes Yes Yes Yes Dz Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes Yes Yes Se Yes Yes Yes Yes Multiply Operations Sf Yes Yes Yes Yes Dg Yes Yes Yes Yes When writing parallel instructions, the B-field instruction is written first, followed by the A-field instruction. A sample parallel processing program using DSP instructions is shown in figure 3.6. Parallel processing only instructions in the A field (without those in the B field) can be executed (transferring data in parallel without DSP data operation instructions) PADD DCF PINC A0, M0, A0 M1, A1 PMULS X0, Y0, M0 MOVX.W @R4+, X0 MOVY.W @R6+, Y0 MOVY.W @R7+, Y1 [NOPY] MOVX.W @R5+R8, X0 MOVX.W @R4, X1 PCMP M1, M0 Figure 3.6 Sample Parallel DSP Instruction Program Rev. 1.00, 02/04, page 112 of 804 Square brackets mean that the contents can be omitted. The no operation instructions NOPX and NOPY can be omitted. For details on the B field in DSP instructions, refer to section 3.6.4, DSP Data Operation Instruction Set. The DSR register condition code bit (DC) is always updated on the basis of the result of an unconditional ALU or shift operation instruction. Conditional instructions do not update the DC bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19. Rev. 1.00, 02/04, page 113 of 804 Table 3.19 DC Bit Update Definitions CS [2:0] 0 0 0 Condition Mode Carry or borrow mode Description The DC bit is set if an ALU arithmetic operation generates a carry or borrow, and is cleared otherwise. When a PSHA or PSHL shift instruction is executed, the last bit data shifted out is copied into the DC bit. When an ALU logical operation is executed, the DC bit is always cleared. 0 0 1 Negative value mode When an ALU or shift (PSHA) arithmetic operation is executed, the MSB of the result, including the guard bits, is copied into the DC bit. When an ALU or shift (PSHL) logical operation is executed, the MSB of the result, excluding the guard bits, is copied into the DC bit. 0 0 1 1 0 1 Zero value mode Overflow mode The DC bit is set if the result of an ALU or shift operation is allzeros, and is cleared otherwise. The DC bit is set if the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. 1 0 0 Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is mode cleared if the result is all-zeros. DC = ~{(negative value ^ over-range) | zero value}; In case of arithmetic operation DC = 0; In case of logical operation 1 0 1 Signed greater-orequal mode If the result of an ALU or shift (PSHA) arithmetic operation exceeds the destination register range, including the guard bits (over-range), the definition is the same as in negative value mode. If the result is not over-range, the definition is the opposite of that in negative value mode. When an ALU or shift (PSHL) logical operation is executed, the DC bit is always cleared. DC = ~(negative value ^ over-range); In case of arithmetic operation DC = 0 ; In case of logical operation 1 1 1 1 0 1 Reserved (setting prohibited) Reserved (setting prohibited) Rev. 1.00, 02/04, page 114 of 804 * Conditional Operations and Data Transfer Some instructions belonging to this class can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel specification is made. Examples are shown in figure 3.7. DCT PADD X0,Y0,A0 When condition is True Before execution: X0=H'33333333, Y0=H'55555555, A0=H'123456789A, R4=H'00008000, R6=H'00005000, R9=H'00000004, (R4)=1111 (R6)=2222 After execution: X0=H'11110000, Y0=H'55555555, A0=H'0088888888, R4=H'00008002, R6=H'00005004, R9=H'00000004, (H'00008000)=H'1111 (H'00008233)=H'2222 MOVX.W @R4+,X0 MOVY.W A0,@R6+R9 ; When condition is False Before execution: X0=H'33333333, Y0=H'55555555, A0=H'123456789A, R4=H'00008000, R6=H'00005000, R9=H'00000004, (R4)=1111, (R6)=2222 After execution: X0=H'11110000, Y0=H'55555555, A0=H'123456789A, R4=H'00008002, R6=H'00005004, R9=H'00000004, (H'00008000)=H'1111 (H'00008233)=H'2222 Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions * Assignment of NOPX and NOPY Instruction Codes When there is no data transfer instruction to be parallel-processed simultaneously with a DSP data operation instruction, an NOPX or NOPY instruction can be written as the data transfer instruction, or the instruction can be omitted. The instruction code is the same whether an NOPX or NOPY instruction is written or the instruction is omitted. When there in no DSP data operation instruction to be parallel-processed simultaneously with a data transfer instruction, an NOPX or NOPY instruction can be written or the instruction can be omitted. Examples of NOPX and NOPY instruction codes are shown in table 3.20. Rev. 1.00, 02/04, page 115 of 804 Table 3.20 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 Code 1111100000001011 1011000100000111 PADD X0,Y0,A0 NOPX MOVY.W @R6+R9,Y0 1111100000000011 1011000100000111 PADD X0,Y0,A0 NOPX NOPY 1111100000000000 1011000100000111 PADD X0,Y0,A0 NOPX 1111100000000000 1011000100000111 PADD X0,Y0,A0 1111100000000000 1011000100000111 MOVX.W @R4+,X0 MOVX.W @R4+,X0 MOVS.W @R4+,X0 NOPX MOVY.W @R6+R9,Y0 MOVY.W @R6+R9,Y0 NOPX NOP NOPY MOVY.W @R6+R9,Y0 NOPY 1111000000001011 1111000000001000 1111010010001000 1111000000000011 1111000000000011 1111000000000000 0000000000001001 3.5.3 DSP-Type Data Formats This LSI has several different data formats that depend on the instruction. This section explains the data formats for DSP type instructions. Figure 3.8 shows three DSP-type data formats with different binary point positions. A CPU-type data format with the binary point to the right of bit 0 is also shown for reference. The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSPtype integer format has the binary point between bit 16 and bit 15. The DSP-type logical format does not have a binary point. The valid data lengths of the data formats depend on the instruction and the DSP register. Rev. 1.00, 02/04, page 116 of 804 DSP type fixed point 39 With guard bits S 31 30 Without guard bits 39 Multiplier input S 31 30 S 16 15 0 -1 to +1 - 2-15 0 -1 to +1 - 2-31 31 30 0 -28 to +28 - 2-31 DSP type integer 39 With guard bits S 31 Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) S 31 22 S 31 21 16 15 S 0 -16 to +16 16 15 0 -32 to +32 16 15 0 -215 to +215 - 1 32 31 16 15 0 -223 to +223 - 1 39 DSP type logical 31 16 15 0 CPU type integer Longword 31 S 0 -231 to +231 - 1 S: Sign bit : Binary point : Does not affect the operations Figure 3.8 Data Formats The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent values from -64 to +63, but -32 to +32 are valid numbers for the instruction. Also the shift amount for a logical shift operation has a 6-bit field, but -16 to +16 are valid numbers for the instruction. The results when an invalid shift amount is specified cannot be guaranteed. Rev. 1.00, 02/04, page 117 of 804 3.5.4 ALU Fixed-Point Arithmetic Operations Figure 3.9 shows the ALU fixed-point arithmetic operation flow. Table 3.21 shows the variation of this type of operation and table 3.22 shows the correspondence between each operand and registers. 39 Guard 31 0 39 Guard 31 0 Source 1 Source 2 ALU DSR GT Z N V DC Destination Guard 39 31 0 Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. ALU fixed-point operations are executed between registers. Each source and destination operand are selected independently from one of the DSP registers. When a register providing guard bits is specified as an operand, the guard bits are activated for this type of operation. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Rev. 1.00, 02/04, page 118 of 804 Table 3.21 Variation of ALU Fixed-Point Operations Mnemonic PADD PSUB PADDC PSUBC PCMP PCOPY Function Addition Subtraction Addition with carry Subtraction with borrow Comparison Data copy Source 1 Sx Sx Sx Sx Sx Sx All 0 PABS Absolute Sx All 0 PNEG Negation Sx All 0 PCLR Clear All 0 Source 2 Sy Sy Sy Sy Sy All 0 Sy All 0 Sy All 0 Sy All 0 Destination Dz or Du Dz or Du Dz Dz -- Dz Dz Dz Dz Dz Dz Dz Table 3.22 Correspondence between Operands and Registers Register A0 A1 M0 M1 X0 X1 Y0 Y1 Sx Yes Yes Yes Yes Sy Yes Yes Yes Yes Dz Yes Yes Yes Yes Yes Yes Yes Yes Du Yes Yes Yes Yes As shown in figure 3.10, data loaded from the memory at the MA stage to X0 by the data transfer instruction (MOVX.W @R4+,X0) which is programmed at the same line as the ALU operation (PADD X0,Y0,A0) , is not used as a source operand for this operation, even though the destination operand X0 of the data load operation is identical to the source operand of the ALU operation. In this case, results of previous operation (MOVX.W @R4+,X0) are used as the source operands for the ALU operation, and then updated as the destination operand X0 of the data transfer instruction (MOVX.W @R4+,X0). . Rev. 1.00, 02/04, page 119 of 804 Operation Sequence Example PADD X0, Y0, A0 Slot Stage IF ID EX MA/DSP MOVX.W @R4+, X0 MOVX.W @R4+, X0 1 MOVX 2 MOVX & PADD 3 4 5 6 MOVX MOVX & PADD Addressing Addressing MOVX MOVX & PADD Previous cycle result is used. Figure 3.10 Operation Sequence Example Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. However, in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in DSR. The DC bit result is as follows: Carry or Borrow Mode: CS[2:0] = B'000: The DC bit indicates that carry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. Some examples are shown in figure 3.11. This mode is the default condition. When the input data is negative in a PABS or PNEG instruction, carry is generated. Rev. 1.00, 02/04, page 120 of 804 Example 1 Guard bits 0000 0000 1111111111111111 +) 0000 0000 0000 0000 0000 0001 0000 0001 0000 0000 0000 0000 Carry detecting point Carry is detected Example 2 Guard bits 111111110111 0000 0000 0000 +) 0011 11110001 0000 0000 0000 (1) 0011 11101000 0000 0000 0000 Carry detecting point Carry is not detected Example 3 Guard bits 0000 0000 0000 0000 0000 0001 -) 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 Borrow detecting point Borrow is not detected Example 4 Guard bits 0000 0000 0001 0000 0000 0001 -) 0000 0000 0001 0000 0000 0010 111111111111111111111111 Borrow detecting point Borrow is detected Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode Negative Value Mode: CS[2:0] = B'001: The DC flag indicates the same value as the MSB of the operation result. When the result is a negative number, the DC bit shows 1. When it is a positive number, the DC bit shows 0. The ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the MSB of the operation result regardless of the destination operand. Some examples are shown in figure 3.12. Example 1 Guard bits 1100 0000 0000 0000 0000 0000 +) 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 Sign bit Negative value Example 2 Guard bits 0011 0000 0000 0000 0000 0000 +) 0000 0000 1000 0000 0000 0001 0011 0000 1000 0000 0000 0001 Sign bit Positive value Figure 3.12 DC Bit Generation Examples in Negative Value Mode Zero Value Mode: CS[2:0] = B'010: The DC flag indicates whether the operation result is 0 or not. When the result is 0, the DC bit shows 1. When it is not 0, the DC bit shows 0. Overflow Mode: CS[2:0] = B'011: The DC bit indicates whether or not overflow occurs in the result. When an operation yields a result beyond the range of the destination register, except the guard-bit parts, the DC bit is set. Even though guard bits are provided in the destination register, the DC bit always indicates the result of when no guard bits are provided. So, the DC bit is always Rev. 1.00, 02/04, page 121 of 804 set if the guard-bit parts are used for large number representation. Some DC bit generation examples in overflow mode are shown in figure 3.13. Example 1 Guard bits 111111111111111111111111 +) 111111111000 0000 0000 0000 111111110111111111111111 Overflow detecting field Overflow case Example 2 Guard bits 111111111111111111111111 +) 111111111000 0000 0000 0001 111111111000000000000000 Overflow detecting field Non overflow case Figure 3.13 DC Bit Generation Examples in Overflow Mode Signed Greater Than Mode: CS[2:0] = B'100: The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data (signed) as the result of compare operation PCMP. Therefore, the PCMP operation should be executed before the conditional operation is executed under this condition mode. This mode is similar to the Negative Value Mode described before, because the result of a compare operation is a positive value if the source 1 data is greater than the source 2 data. However, the signed bit of the result shows a negative value if the compare operation yields a result beyond the range of the destination operand, including the guard-bit parts (called "Over-range"), even though the source 1 data is greater than the source 2 data. The DC bit is updated concerning this type of special case in this condition mode. The equation below shows the definition of getting this condition: DC = ~ {(Negative ^ Over-range) | Zero} When the PCMP operation is executed under this condition mode, the result of the DC bit is the same as the T bit's result of the CMP/GT operation of the CPU instruction. Signed Greater Than or Equal Mode: CS[2:0] = B'101: The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare operation PCMP. Therefore, the PCMP operation should be executed before the conditional operation is executed under this condition mode. This mode is similar to the Signed Greater Than Mode described before but the equal case is also included in this mode. The equation below shows the definition of getting this condition: DC = ~ (Negative ^ Over-range) When the PCMP operation is executed under this condition mode, the result of the DC bit is the same as the T bit's result of a CMP/GE operation of the CPU instruction. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit Rev. 1.00, 02/04, page 122 of 804 always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. Note: The DC bit is always updated as the carry flag for `PADDC' and is always updated as the carry/borrow flag for `PSUBC' regardless of the CS[2:0] state. * Overflow Protection The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See section 3.5.11, Overflow Protection, for details. 3.5.5 ALU Integer Operations Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of this type of operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.22. 39 Guard 31 16 0 39 Guard 31 16 0 Source 1 Source 2 ALU DSR GT Z N V DC Destination Ignored Guard 39 31 16 0 Cleared to 0 Figure 3.14 ALU Integer Arithmetic Operation Flow Rev. 1.00, 02/04, page 123 of 804 Table 3.23 Variation of ALU Integer Operations Mnemonic PINC Function Increment by 1 Source 1 Sx +1 PDEC Decrement by 1 Sx -1 Source 2 +1 Sy -1 Sy Destination Dz Dz Dz Dz Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base precision and 8 bits of the guard-bits parts. So the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the upper word excluding the guard bits of the operation result are input into the destination register. In ALU integer arithmetic operations, the lower word of the source operand is ignored and the lower word of the destination operand is automatically cleared. The guard-bit parts are effective in integer arithmetic operations if they are supported. Others are basically the same operation as ALU fixed-point arithmetic operations. As shown in table 3.23, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or -1. When a word data is loaded into one of the DSP unit's registers, it is input as an upper word data. When a register providing guard bits is specified as an operand, the guard bits are also activated. These operations, as well as ALU fixed-point arithmetic operations, are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. This is the same as ALU fixed-point arithmetic operations but the lower word of each source and destination operand is not used in order to generate them. See section 3.5.4, ALU Fixed-Point Arithmetic Operations, for details. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. See section 3.5.4, ALU Fixed-Point Arithmetic Operations, for details. * Overflow Protection The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section 3.5.11, Overflow Protection, for details. Rev. 1.00, 02/04, page 124 of 804 3.5.6 ALU Logical Operations Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of operation. The correspondence between each operand and registers is the same as the ALU fixedpoint arithmetic operations as shown in table 3.21. The ALU logical operation is executed between registers. Each source operand and destination operand is selected independently from one of the DSP registers. As shown in figure 3.15, this type of operation uses only the upper word of each operand. The lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared. These operations are also executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. 39 31 16 0 39 31 16 0 Source 1 Source 2 ALU DSR GT Z N V DC Destination Ignored 39 31 16 0 Cleared to 0 Figure 3.15 ALU Logical Operation Flow Table 3.24 Variation of ALU Logical Operations Mnemonic PAND POR PXOR Function Logical AND Logical OR Logical exclusive OR Source 1 Sx Sx Sx Source 2 Sy Sy Sy Destination Dz Dz Dz Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR register are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR. The DC bit result is: Rev. 1.00, 02/04, page 125 of 804 Carry or Borrow Mode: CS[2:0] = B'000: The DC bit is always cleared to 0. Negative Value Mode: CS[2:0] = B'001: Bit 31 of the operation result is loaded into the DC bit. Zero Value Mode: CS[2:0] = B'010: The DC bit is set to1when the operation result is zero; otherwise it is cleared to 0. Overflow Mode: CS[2:0] = B'011: The DC bit is always cleared to 0. Signed Greater Than Mode: CS[2:0] = B'100: The DC bit is always cleared to 0. Signed Greater Than or Equal Mode: CS[2:0] = B'101: The DC bit is always cleared to 0. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. 3.5.7 Fixed-Point Multiply Operation Figure 3.16 shows the fixed-point multiply operation flow. Table 3.25 shows the variation of this type of operation and table 3.26 shows the correspondence between each operand and registers. The multiply operation of the DSP unit is single-word signed single-precision multiplication. The fixed-point multiply operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. If a double-precision multiply operation is needed, the CPU double-word multiply instructions can be made of use. Rev. 1.00, 02/04, page 126 of 804 39 31 S 0 16 0 39 31 S 16 0 Source 1 Source 2 Point position S: Signed bit MAC Destination S 39 31 1 0 0 Ignored Figure 3.16 Fixed-Point Multiply Operation Flow Table 3.25 Variation of Fixed-Point Multiply Operation Mnemonic PMULS Function Signed multiplication Source 1 Se Source 2 Sf Destination Dg Table 3.26 Correspondence between Operands and Registers Register A0 A1 M0 M1 X0 X1 Y0 Y1 Se Yes Yes Yes Yes Sf Yes Yes Yes Yes Dg Yes Yes Yes Yes Note: The multiply operations basically generate 32-bit operation results. So when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy bit 31 of the operation result. The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.16. In the CPU instruction multiply operations, the lower words of both source operands are input into a MAC unit. The operation result is also different from the CPU's case. The CPU instruction multiply operation result is aligned to the LSB of the destination, but the fixed-point multiply operation result of DSP unit is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always 0. Rev. 1.00, 02/04, page 127 of 804 Multiply is always unconditional, but does not affect any condition code bits, DC, N, Z, V, and GT, in DSR. * Overflow Protection The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11, Overflow Protection, for details. If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean (+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF. Rev. 1.00, 02/04, page 128 of 804 3.5.8 Shift Operations Shift operations barrel shift and can use either register or immediate value as the shift amount operand. Other source and destination operands are specified by the register. There are two kinds of shift operations of arithmetic and logical shifts. Table 3.27 shows the variation of this type of operation. The correspondence between each operand and registers, except for immediate operands, is the same as the ALU fixed-point operations as shown in table 3.21. Table 3.27 Variation of Shift Operations Mnemonic PSHA Sx, Sy, Dz PSHL Sx, Sy, Dz Function Arithmetic shift Logical shift Source 1 Sx Sx Dz Dz Source 2 Sy Sy Imm1 Imm2 Destination Dz Dz Dz Dz PSHA #Imm1, Dz Arithmetic shift with immediate PSHL #Imm2, Dz Logical shift with immediate -32 Imm1 +32, -16 Imm2 +16 Arithmetic Shift: Figure 3.17 shows the arithmetic shift operation flow. Left shift 39 32 31 16 15 0 0 (MSB copy) Shift out >=0 39 Shift amount data (source 2) 32 31 <0 +32 to -32 23 22 16 15 Sy 6 0 Ignored Updated 0 GT DSR Z Shift out N V DC 39 32 31 Right shift 16 15 0 Imm1 Figure 3.17 Arithmetic Shift Operation Flow Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guardbit parts when a register not providing the guard-bit parts is specified as the source operand. When a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. In this arithmetic shift operation, all bits of the source 1 and destination operands are activated. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either a register or immediate operand. The available shift range is from -32 to Rev. 1.00, 02/04, page 129 of 804 +32. Here, a negative value means the right shift, and a positive value means the left shift. It is possible for any source 2 operand to specify from -64 to +63 but the result is unknown if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. This operation is executed in the DSP stage, as shown in figure 3.10 as well as in ALU fixed-point arithmetic operations. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = B'000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = B'001 The DC bit is set to 1 when the operation result is a negative value, and cleared to 0 when the operation result is zero or a positive value. 3. Zero Value Mode: CS[2:0] = B'010 The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0. 4. Overflow Mode: CS[2:0] = B'011 The DC bit is set to 1 when an overflow occurs. 5. Signed Greater Than Mode: CS[2:0] = B'100 The DC bit is always cleared to 0. 6. Signed Greater Than or Equal Mode: CS[2:0] = B'101 The DC bit is always cleared to 0. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. * Overflow Protection The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section 3.5.11, Overflow Protection, for details. Logical Shift: Figure 3.18 shows the logical shift operation flow. Rev. 1.00, 02/04, page 130 of 804 Cleared to 0 39 32 31 Left shift 16 15 0 39 32 31 Right shift 16 15 0 Shift out 0 0 Shift out >=0 39 Shift amount data (source 2) 5 32 31 <0 +16 to -16 22 21 16 15 Sy 0 Updated DSR 0 Ignored GT Z N V DC Imm2 Figure 3.18 Logical Shift Operation Flow As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand and the destination operand. The lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared as in the ALU logical operations. The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can be specified by either the register or immediate operand. The available shift range is from -16 to +16. Here, a negative value means the right shift, and a positive value means the left shift. It is possible for any source 2 operand to specify from -32 to +31, but the result is unknown if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination's. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. In case of an unconditional operation, they are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR. The DC bit result is: 1. Carry or Borrow Mode: CS[2:0] = B'000 The DC bit indicates the last shifted out data as the operation result. 2. Negative Value Mode: CS[2:0] = B'001 Bit 31 of the operation result is loaded into the DC bit. 3. Zero Value Mode: CS[2:0] = B'010 The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0. Rev. 1.00, 02/04, page 131 of 804 4. Overflow Mode: CS[2:0] = B'011 The DC bit is always cleared to 0. 5. Signed Greater Than Mode: CS[2:0] = B'100 The DC bit is always cleared to 0. 6. Signed Greater Than or Equal Mode: CS[2:0] = B'101 The DC bit is always cleared to 0. The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is always cleared in this operation. So is the GT bit. 3.5.9 Most Significant Bit Detection Operation The PDMSB, most significant bit detection operation, is used to calculate the shift amount for normalization. Figure 3.19 shows the PDMSB operation flow and table 3.28 shows the operation definition. Table 3.29 shows the possible variations of this type of operation. The correspondence between each operand and registers is the same as for ALU fixed-point operations, as shown in table 3.21. Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts. When a register not providing the guard-bit parts is specified as a destination operand, the upper word of the operation result is input into the destination register. As shown in figure 3.19, the PDMSB operation uses all bits as a source operand, but the destination operand is treated as an integer operation result because shift amount data for normalization should be integer data as described in section 3.5.8, Arithmetic Shift. These operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically updated in accordance with the operation result. In case of a conditional operation, they are not updated, even though the specified condition is true, and the operation is executed. In case of an unconditional operation, they are always updated with the operation result. Rev. 1.00, 02/04, page 132 of 804 39 Guard 31 16 15 0 Source 1 or 2 Priority encoder DSR GT Z N V DC Destination Guard Cleared to 0 31 16 0 39 Figure 3.19 PDMSB Operation Flow The definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR. The DC bit result is Carry or Borrow Mode: CS[2:0] = B'000: The DC bit is always cleared to 0. Negative Value Mode: CS[2:0] = B'001: The DC bit is set to 1 when the operation result is a negative value, and cleared to 0 when the operation result is zero or a positive value. Zero Value Mode: CS[2:0] = B'010: The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0. Overflow Mode: CS[2:0] = B'011: The DC bit is always cleared to 0. Signed Greater Than Mode: CS[2:0] = B'100: The DC bit is set to 1 when the operation result is a positive value; otherwise it is cleared to 0. Signed Greater Than or Equal Mode: CS[2:0] = B'101: The DC bit is set to 1 when the operation result is zero or a positive value; otherwise it is cleared to 0. Rev. 1.00, 02/04, page 133 of 804 Table 3.28 Operation Definition of PDMSB Source Data Guard Bit Upper Word Lower Word 3 0 0 0 0 2 0 0 0 1 1 0 0 1 * 0 0 1 * * Result for DST Guard Bit 39-32 All 0 All 0 All 0 All 0 Upper Word 31-22 21 20 19 18 17 16 Decimal All 0 All 0 All 0 All 0 0 0 0 0 1 1 1 1 1 1 1 1 : 1 1 1 1 1 1 0 0 1 0 1 0 +31 +30 +29 +28 39 38 ... 33 32 31 30 29 28 ... 0 0 0 0 0 0 0 0 ...0 ...0 ...0 ...0 : 0 0 0 0 0 0 0 0 0 0 ...0 ...0 ...0 ...0 ...0 : 0 1 1 0 ...* ...* * * * * * * * * * * 0 0 0 0 1 0 0 0 1 * 0 0 1 * * 0 1 * * * 1 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... ... ... ... : ... ... ... ... ... : ... ... * * * * * * * * * * * * * * * * * * * * All 0 All 0 All 0 All 1 All 1 All 0 All 0 All 0 All 1 All 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 : 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 +2 +1 0 -1 -2 * * * * * * * * All 1 All 1 All 1 All 1 1 1 1 1 1 1 : 0 0 0 0 0 0 -8 -8 1 1 1 1 1 1 1 1 1 1 ...1 ...1 ...1 ...1 ...1 : 0 1 1 1 1 * 0 1 1 1 * * 0 1 1 * * * 0 1 * * * * 0 ... ... ... ... ... : * * * * * * * * * * * * * * * * * * * * All 1 All 1 All 0 All 0 All 0 All 1 All 1 All 0 All 0 All 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 : 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 -2 -1 0 +1 +2 1 1 1 1 1 1 1 1 ...1 ...1 ...1 ...1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... ... ... ... 1 1 1 1 0 1 1 1 * 0 1 1 * * 0 1 All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 +28 +29 +30 +31 Note: * means don't care. Table 3.29 Variation of PDMSB Operation Mnemonic PDMSB Function MSB detection Source Sx -- Rev. 1.00, 02/04, page 134 of 804 Source 2 -- Sy Destination Dz Dz The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0] bits. See the negative value mode part above. The Z bit always indicates the same state as the DC bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit is always cleared. The GT bit always indicates the same state as the DC bit set in signed greater than mode by the CS[2:0] bits. See the signed greater than mode part above. 3.5.10 Rounding Operation The DSP unit provides the function that rounds from 32 bits to 16 bits. In case of providing guardbit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is added to the source operand data and then, the lower word is cleared. Figure 3.20 shows the rounding operation flow and figure 3.21 shows the operation definition. Table 3.30 shows the variation rounding operation. The correspondence between each operand and registers is the same as ALU fixed-point operations as shown in table 3.21. As shown in figure 3.21, the rounding operation uses full-size data for both source and destination operands. These operations are executed in the DSP stage as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is performed. The rounding operation is always executed unconditionally, so that the DC, N, Z, V, and GT bits in DSR are always updated in accordance with the operation result. The definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR. The result of these condition code bits is the same as the ALU-fixed point arithmetic operations. 39 Guard 31 16 15 0 H'00008000 Source 1 or 2 ALU DSR GT Z N V DC Destination Guard Cleared to 0 31 16 0 39 Figure 3.20 Rounding Operation Flow Rev. 1.00, 02/04, page 135 of 804 Rounded result H'00 0003 H'00 0002 H'00 0001 Analog value Figure 3.21 Definition of Rounding Operation Table 3.30 Variation of Rounding Operation Mnemonic PRND Function Rounding Source 1 Sx Source 2 Sy Destination Dz Dz * Overflow Protection The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.5.11, Overflow Protection, for details. 3.5.11 Overflow Protection The S bit in SR is used as the overflow protection enable bit. The S bit is effective for any arithmetic operations executed in the DSP unit, including the CPU instruction multiply and MAC operations. The arithmetic operation overflows when the operation result exceeds the range of two's complement representation without guard-bit parts. Table 3.31 shows the definition of overflow protection for fixed-point arithmetic operations, including fixed-point multiplication described in section 3.5.7, Fixed-Point Multiply Operation. Table 3.32 shows the definition of overflow protection for integer arithmetic operations. The lower word of the saturation value of the integer arithmetic operation is don't care. Lower word value cannot be guaranteed. When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits. Table 3.31 Definition of Overflow Protection for Fixed-Point Arithmetic Operations Sign Positive Negative Overflow Condition Result > 1 - 2 Result < -1 -31 Fixed Value 1-2 -1 -31 H'00 0001 8000 H'00 0002 0000 H'00 0002 8000 True value Hex Representation 00 7FFF FFFF FF 8000 0000 Rev. 1.00, 02/04, page 136 of 804 Table 3.32 Definition of Overflow Protection for Integer Arithmetic Operations Sign Positive Negative Note: * Overflow Condition Result > 2 - 1 Result < -2 means don't care. 15 15 Fixed Value 2 -1 -2 15 15 Hex Representation 00 7FFF **** FF 8000 **** 3.5.12 Local Data Move Instruction The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in order to support CPU instruction multiply/MAC operations. They can be also used as temporary storage registers by local data move instructions between MACH/L and other DSP registers. Figure 3.22 shows the flow of seven local data move instructions. Table 3.33 shows the variation of this type of instruction. MACH MACL PSTS PLDS X0 X1 A0 A1 Y0 Y1 M0 M1 A0G A1G DSR Cannot be used Figure 3.22 Local Data Move Instruction Flow Table 3.33 Variation of Local Data Move Operations Mnemonic PLDS PSTS Function Data move from DSP register to MACL/MACH Data move from MACL/MACH to DSP register Operand Dz Dz This instruction is very similar to other transfer instructions. If either the A0 or A1 register is specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are not updated regardless of the instruction result. This instruction can operate with MOVX and MOVY in parallel. Rev. 1.00, 02/04, page 137 of 804 3.5.13 Operand Conflict When an identical destination operand is specified with multiple parallel instructions, data conflict occurs. Table 3.34 shows the correspondence between each operand and registers. Table 3.34 Correspondence between Operands and Registers X-Memory Load Instructions Ax DSP A0 Registers A1 M0 M1 X0 X1 Y0 Y1 *2 *2 *2 *2 *1 *1 *1 *1 *2 Ix Dx Y-Memory Load Instructions Ay Iy Dy 6-Operand ALU Instructions Sx * 1 3-Operand Multiply Instructions Se *1 Sf *1 Dg * 2 3-Operand ALU Instructions Sx * 1 Sy Du * 2 Sy Dz *1 *1 *1 *1 * 1 *2 *2 *1 * 1 *1 *1 * *1 *1 *1 *1 1 *1 *1 *2 *2 *2 *2 *2 *1 *1 *1 *1 *1 *1 Notes: 1. Registers available for operands 2. Registers available for operands (when there is operand conflict) There are three cases of operand conflict problems. * When ALU and multiply instructions specify the same destination operand (Du and Dg) * When X-memory load and ALU instructions specify the same destination operand (Dx and Du, or Dz) * When Y-memory load and ALU instructions specify the same destination operand (Dy and Du, or Dz) In these cases above, the result is not guaranteed. Rev. 1.00, 02/04, page 138 of 804 3.6 3.6.1 DSP Extended Function Instruction Set CPU Extended Instruction Set Table 3.35 DSP Mode Extended System Control Instructions Instruction SETRC #imm SETRC Rn LDRS @(disp,PC) LDRE @(disp,PC) STC MOD,Rn STC RS,Rn STC RE,Rn STS DSR,Rn STS A0,Rn STS X0,Rn STS X1,Rn STS Y0,Rn STS Y1,Rn STS.L DSR,@-Rn STS.L A0,@-Rn STS.L X0,@-Rn STS.L X1,@-Rn STS.L Y0,@-Rn STS.L Y1,@-Rn STC.L MOD,@-Rn STC.L RS,@-Rn STC.L RE,@-Rn LDS.L @Rn + ,DSR LDS.L @Rn + ,A0 LDS.L @Rn + ,X0 LDS.L @Rn + ,X1 LDS.L @Rn + ,Y0 Instruction Code 10000010iiiiiiii 0100nnnn00010100 10001100dddddddd 10001110dddddddd 0000nnnn01010010 0000nnnn01100010 0000nnnn01110010 0000nnnn01101010 0000nnnn01111010 0000nnnn10001010 0000nnnn10011010 0000nnnn10101010 0000nnnn10111010 0100nnnn01100010 0100nnnn01110010 0100nnnn10000010 0100nnnn10010010 0100nnnn10100010 0100nnnn10110010 0100nnnn01010011 0100nnnn01100011 0100nnnn01110011 0100nnnn01100110 0100nnnn01110110 0100nnnn10000110 0100nnnn10010110 0100nnnn10100110 Operation immRC (of SR) Rn[11:0] RC (of SR) (disp x 2 + PC) RS (disp x 2 + PC) RE MODRn RSRn RERn DSRRn A0Rn X0Rn X1Rn Y0Rn Y1Rn Rn-4Rn, DSR(Rn) Rn-4Rn, A0(Rn) Rn-4Rn, X0(Rn) Rn-4Rn, X1(Rn) Rn-4Rn, Y0(Rn) Rn-4Rn, Y1(Rn) Rn-4Rn, MOD(Rn) Rn-4Rn, RS(Rn) Rn-4Rn, RE(Rn) (Rn) DSR, Rn + 4Rn (Rn) A0, Rn + 4Rn (Rn) X0, Rn + 4Rn (Rn) X1, Rn + 4Rn (Rn) Y0, Rn + 4Rn Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 1.00, 02/04, page 139 of 804 Instruction LDS.L @Rn + ,Y1 LDC.L @Rn + ,MOD LDC.L @Rn + ,RS LDC.L @Rn + ,RE LDS Rn,DSR LDS Rn,A0 LDS Rn,X0 LDS Rn,X1 LDS Rn,Y0 LDS Rn,Y1 LDC Rn,MOD LDC Rn,RS LDC Rn,RE Instruction Code 0100nnnn10110110 0100nnnn01010111 0100nnnn01100111 0100nnnn01110111 0100nnnn01101010 0100nnnn01111010 0100nnnn10001010 0100nnnn10011010 0100nnnn10101010 0100nnnn10111010 0100nnnn01011110 0100nnnn01101110 0100nnnn01111110 Operation (Rn) Y1, Rn + 4Rn (Rn) MOD, Rn + 4Rn (Rn) RS, Rn + 4Rn (Rn) RE, Rn + 4Rn RnDSR RnA0 RnX0 RnX1 RnY0 RnY1 RnMOD RnRS RnRE Execution States T Bit 1 4 4 4 1 1 1 1 1 1 4 4 4 Rev. 1.00, 02/04, page 140 of 804 3.6.2 Double-Data Transfer Instruction Set Table 3.36 Double Data Transfer Instruction Instruction X NOPX memory MOVX.W @Ax,Dx data transfer MOVX.W @Ax + ,Dx MOVX.W @Ax + Ix,Dx MOVX.W Da,@Ax MOVX.W Da,@Ax + Instruction Code Operation 1111000*0*0*00** X memory no access 111100A*D*0*01** (Ax) MSW of Dx, 0 LSW of Dx Execution States DC 1 1 111100A*D*0*10** (Ax) MSW of Dx, 0 LSW of 1 Dx, Ax + 2 Ax 111100A*D*0*11** (Ax) MSW of Dx, 0 LSW of 1 Dx, Ax + Ix Ax 111100A*D*1*01** MSW of Da (Ax) 111100A*D*1*10** MSW of Da (Ax), Ax + 2 Ax 1 1 MOVX.W Da,@Ax + Ix 111100A*D*1*11** MSW of Da (Ax), Ax + Ix Ax 1 Y NOPY memory MOVY.W @Ay,Dy data transfer MOVY.W @Ay + ,Dy MOVY.W @Ay + Iy,Dy MOVY.W Da,@Ay MOVY.W Da,@Ay + 111100*0*0*0**00 Y memory no access 1 1 111100*A*D*0**01 (Ay) MSW of Dy, 0 LSW of Dy 111100*A*D*0**10 (Ay) MSW of Dy, 0 LSW of 1 Dy, Ay + 2 Ay 111100*A*D*0**11 (Ay) MSW of Dy, 0 LSW of Dy, Ay + Iy Ay 111100*A*D*1**01 MSW of Da (Ay) 111100*A*D*1**10 MSW of Da (Ay), Ay + 2 ->Ay 1 1 1 MOVY.W Da,@Ay + Iy 111100*A*D*1**11 MSW of Da (Ay), Ay + Iy Ay 1 Rev. 1.00, 02/04, page 141 of 804 3.6.3 Single-Data Transfer Instruction Set Table 3.37 Single Data Transfer Instructions Instruction MOVS.W @-As,Ds MOVS.W @As,Ds MOVS.W @As + ,Ds MOVS.W @As + Ix,Ds MOVS.W Ds,@-As* MOVS.W Ds,@As* MOVS.W Ds,@As + * MOVS.W Ds,@As + Ix* MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As + ,Ds MOVS.L @As + Ix,Ds MOVS.L Ds,@-As MOVS.L Ds,@As MOVS.L Ds,@As + MOVS.L Ds,@As + Ix Note: * Instruction Code Operation Execution States DC 111101AADDDD0000 As-2 As, (As) MSW of Ds, 0 - 1 > LSW of Ds 111101AADDDD0100 (As) MSW of Ds, 0 LSW of Ds 1 111101AADDDD1000 (As) MSW of Ds, 0 LSW of Ds, As + 2 As 111101AADDDD1100 (Asc) MSW of Ds, 0 LSW of Ds, As + Ix ->As 111101AADDDD0001 As-2 MSW of Ds, As(As) 111101AADDDD0101 MSW of Ds(As) 111101AADDDD1001 MSW of Ds (As), As + 2 As 111101AADDDD1101 MSW of Ds (As), As + Ix As 111101AADDDD0010 As-4 As, (As) Ds 111101AADDDD0110 (As) Ds 111101AADDDD1010 (As) Ds, As + 4 As 111101AADDDD1110 (As) Ds, As + Ix As 111101AADDDD0011 As-4 As, Ds (As) 111101AADDDD0111 Ds (As) 111101AADDDD1011 Ds (As), As + 4 VAs 111101AADDDD1111 Ds (As), As + Ix As 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If guard bit registers A0G and A1G are specified in source operand Ds, the data is output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8]. The correspondence between DSP data transfer operands and registers is shown in table 3.38. Rev. 1.00, 02/04, page 142 of 804 Table 3.38 Correspondence between DSP Data Transfer Operands and Registers Register CPU R0 Ax Ix Yes Dx Yes Yes Ay Yes Yes Iy Yes Dy Yes Yes Da Yes Yes As Yes Yes Yes Yes Ds Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes register R1 R2 (As2) R3 (As3) R4 (Ax0, As0) Yes R5 (Ax1, As1) Yes R6 (Ay0) R7 (Ay1) R8 (Ix) R9 (Iy) DSP A0 register A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Rev. 1.00, 02/04, page 143 of 804 3.6.4 DSP Data Operation Instruction Set Table 3.39 DSP Data Operation Instructions Instruction Instruction Code Operation Se*SfDg (Signed) Execution States DC PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du 111110********** 1 1 1 1 1 1 1 1 1 1 1 * * * * * Sx + SyDu Se*SfDg (Signed) PMULS Se,Sf,Dg 0111eeffxxyygguu PSUB Sx,Sy,Du 111110********** Sy-SyDu Se*SfDg (Signed) PMULS Se,Sf,Dg 0110eeffxxyygguu PADD Sx,Sy,Dz 111110********** 10110001xxyyzzzz DCT PADD Sx,Sy,Dz 111110********** 10110010xxyyzzzz DCF PADD Sx,Sy,Dz 111110********** 10110011xxyyzzzz PSUB Sx,Sy,Dz 111110********** 10100001xxyyzzzz DCT PSUB Sx,Sy,Dz 111110********** 10100010xxyyzzzz DCF PSUB Sx,Sy,Dz 111110********** 10100011xxyyzzzz PSHA Sx,Sy,Dz 111110********** 10010001xxyyzzzz DCT PSHA Sx,Sy,Dz 111110********** 10010010xxyyzzzz If Sy>=0, Sx< Rev. 1.00, 02/04, page 144 of 804 Instruction DCF PSHA Sx,Sy,Dz Instruction Code 111110********** 10010011xxyyzzzz Operation If DC=0 & Sy>=0, Sx< Execution States DC 1 PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz If Sy>=0, Sx< 1 * * * * * DCT PSHL Sx,Sy,Dz 111110********** 10000010xxyyzzzz If DC=1 & Sy>=0, Sx< DCF PSHL Sx,Sy,Dz 111110********** 10000011xxyyzzzz PCOPY Sx,Dz 111110********** 11011001xx00zzzz 1 1 1 1 1 1 1 1 1 1 1 PCOPY Sy,Dz 111110********** 1111100100yyzzzz SyDz DCT PCOPY Sx,Dz 111110********** 11011010xx00zzzz If DC=1, SxDz If DC=0, nop DCT PCOPY Sy,Dz 111110********** 1111101000yyzzzz If DC=1, SyDz If DC=0, nop DCF PCOPY Sx,Dz 111110********** 11011011xx00zzzz If DC=0, SxDz If DC=1, nop DCF PCOPY Sy,Dz 111110********** 1111101100yyzzzz If DC=0, SyDz If DC=1, nop PDMSB Sx,Dz 111110********** 10011101xx00zzzz SxDz normalization count shift value PDMSB Sy,Dz 111110********** 1011110100yyzzzz SyDz normalization count shift value DCT PDMSB Sx,Dz 111110********** 10011110xx00zzzz If DC=1, normalization count shift value SxDz If DC=0, nop If DC=1, normalization count shift value SyDz If DC=0, nop If DC=0, normalization count shift value SxDz If DC=1, nop DCT PDMSB Sy,Dz 111110********** 1011111000yyzzzz DCF PDMSB Sx,Dz 111110********** 10011111xx00zzzz Rev. 1.00, 02/04, page 145 of 804 Instruction DCF PDMSB Sy,Dz Instruction Code Operation 111110********** 1011111100yyzzzz If DC=0, normalization count shift value SyDz If DC=1, nop MSW of Sx+ 1Dz Execution States DC 1 1 1 * * * * * PINC Sx,Dz 111110********** 10011001xx00zzzz PINC Sy,Dz 111110********** 1011100100yyzzzz MSW of Sy+ 1Dz DCT PINC Sx,Dz 111110********** 10011010xx00zzzz If DC=1, MSW of Sx+ 1Dz If DC=0, nop 1 DCT PINC Sy,Dz 111110********** 1011101000yyzzzz If DC=1, MSW of Sy+ 1Dz If DC=0, nop 1 DCF PINC Sx,Dz 111110********** 10011011xx00zzzz If DC=0, MSW of Sx + 1Dz If DC=1, nop 1 DCF PINC Sy,Dz 111110********** 1011101100yyzzzz If DC=0, MSW of Sy+ 1Dz If DC=1, nop 1 PNEG Sx,Dz 111110********** 11001001xx00zzzz 0-SxDz 1 1 1 1 1 1 1 1 1 PNEG Sy,Dz 111110********** 1110100100yyzzzz 0-SyDz DCT PNEG Sx,Dz 111110********** 11001010xx00zzzz If DC=1, 0-SxDz If DC=0, nop DCT PNEG Sy,Dz 111110********** 1110101000yyzzzz If DC=1, 0-SyDz If DC=0, nop DCF PNEG Sx,Dz 111110********** 11001011xx00zzzz If DC=0, 0-SxDz If DC=1, nop DCF PNEG Sy,Dz 111110********** 1110101100yyzzzz If DC=0, 0-SyDz If DC=1, nop POR Sx,Sy,Dz 111110********** 10110101xxyyzzzz Sx | SyDz DCT POR Sx,Sy,Dz 111110********** 10110110xxyyzzzz If DC=1, Sx | SyDz If DC=0, nop DCF POR Sx,Sy,Dz 111110********** 10110111xxyyzzzz If DC=0, Sx | SyDz If DC=1, nop Rev. 1.00, 02/04, page 146 of 804 Instruction Instruction Code Operation Sx & SyDz Execution States DC PAND Sx,Sy,Dz 111110********** 10010101xxyyzzzz DCT PAND Sx,Sy,Dz 111110********** 10010110xxyyzzzz DCF PAND Sx,Sy,Dz 111110********** 10010111xxyyzzzz PXOR Sx,Sy,Dz 111110********** 10100101xxyyzzzz DCT PXOR Sx,Sy,Dz 111110********** 10100110xxyyzzzz DCF PXOR Sx,Sy,Dz 111110********** 10100111xxyyzzzz PDEC Sx,Dz 111110********** 10001001xx00zzzz DCT PDEC Sx,Dz 111110********** 10001010xx00zzzz DCF PDEC Sx,Dz 111110********** 10001011xx00zzzz PDEC Sy,Dz 111110********** 1010100100yyzzzz DCT PDEC Sy,Dz 111110********** 1010101000yyzzzz DCF PDEC Sy,Dz 111110********** 1010101100yyzzzz PCLR Dz 111110********** 100011010000zzzz DCT PCLR Dz 111110********** 100011100000zzzz DCF PCLR Dz 111110********** 100011110000zzzz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * If DC=1, Sx & SyDz If DC=0, nop If DC=0, Sx & SyDz If DC=1, nop Sx ^ SyDz If DC=1, Sx ^ SyDz If DC=0, nop If DC=0, Sx ^ SyDz If DC=0, nop Sx [39:16]-1Dz If DC=1, Sx [39:16]-1Dz If DC=0, nop If DC=0, Sx [39:16]-1Dz If DC=1, nop Sy [31:16]-1Dz If DC=1, Sy [31:16]-1Dz If DC=0, nop If DC=0, Sy [31:16]-1Dz If DC=1, nop h'00000000Dz If DC=1, h'00000000Dz If DC=0, nop If DC=0, h'00000000Dz If DC=1, nop Rev. 1.00, 02/04, page 147 of 804 Instruction PSHA #imm,Dz Instruction Code Operation 111110********** 00010iiiiiiizzzz Execution States DC If imm>=0, Dz< * * - Carry PSHL #imm,Dz 111110********** 00000iiiiiiizzzz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PSTS MACH,Dz 111110********** 110011010000zzzz DCT PSTS MACH,Dz 111110********** 110011100000zzzz If DC=1, MACHDz If DC = 0, nop If DC=0, MACHDz If DC = 1, nop MACLDz DCF PSTS MACH,Dz 111110********** 110011110000zzzz PSTS MACL,Dz 111110********** 110111010000zzzz DCT PSTS MACL,Dz 111110********** 110111100000zzzz If DC=1, MACLDz If DC = 0, nop If DC=0, MACLDz If DC = 1, nop DzMACH DCF PSTS MACL,Dz 111110********** 110111110000zzzz PLDS Dz,MACH 111110********** 111011010000zzzz DCT PLDS Dz,MACH 111110********** 111011100000zzzz If DC=1, DzMACH If DC = 0, nop If DC=0, DzMACH If DC = 1, nop DzMACL DCF PLDS Dz,MACH 111110********** 111011110000zzzz PLDS Dz,MACL 111110********** 111111010000zzzz DCT PLDS Dz,MACL 111110********** 111111100000zzzz If DC=1, DzMACL If DC = 0, nop If DC=0, DzMACL If DC = 1, nop Sx + Sy + DCDz CarryDC DCF PLDS Dz,MACL 111110********** 111111110000zzzz PADDC Sx,Sy,Dz 111110********** 10110000xxyyzzzz Rev. 1.00, 02/04, page 148 of 804 Instruction Instruction Code Operation Sx-Sy-DCDz BorrowDC Execution States DC PSUBC Sx,Sy, Dz 111110********** 10100000xxyyzzzz PCMP Sx,Sy 111110********** 10000100xxyy0000 PABS Sx,Dz 111110********** 10001000xx00zzzz PABS Sy,Dz 111110********** 1010100000yyzzzz PRND Sx,Dz 111110********** 10011000xx00zzzz PRND Sy,Dz 111110********** 1011100000yyzzzz 1 1 1 1 Borrow * * * * * Sx-SyDC update* If Sx<0, 0-SxDz If Sx>=0, SxDz If Sy<0, 0-SyDz If Sy>=0, SyDz Sx + h'00008000Dz LSW of Dzh'0000 1 Sy + h'00008000Dz LSW of Dzh'0000 1 Notes * See table 3.19. In the instruction column, the asterisks in upper line and the lower line indicate A field and B field, respectively. Rev. 1.00, 02/04, page 149 of 804 3.6.5 Operation Code Map in DSP Mode Table 3.40 shows the operation code map including an instruction codes extended in the DSP mode. Table 3.40 Operation Code Map Instruction Code MSB 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rm 0000 Rm 0000 Rn Fx Fx Fx: 0000 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 LSB MD: 00 0000 0001 STC STC STC STC SR, Rn SPC, Rn R0_BANK, Rn R4_BANK, Rn 00MD 0010 01MD 0010 10MD 0010 11MD 0010 00MD 0011 10MD 0011 Rm STC STC STC STC GBR, Rn MOD, Rn STC STC VBR, Rn Rs, Rn STC STC SSR, Rn RE, Rn R3_BANK, Rn R7_BANK, Rn R1_BANK, Rn STC R5_BANK, Rn STC BRAF R2_BANK, Rn STC R6_BANK, Rn STC Rm BSRF Rm PREF @Rm 01MD MOV.B Rm, @(R0, Rn) MOV.W Rm, @(R0, Rn) MOV.L Rm,@(R0, Rn) MUL.L Rm, Rn 0000 0000 00MD 1000 0000 0000 01MD 1000 0000 0000 10MD 1000 0000 0000 11MD 1000 0000 0000 Fx 0000 0000 Fx 0000 0000 Fx 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn 0000 Rn Fx Fx 1001 1010 1011 1000 1001 CLRT CLRS SETT SETS CLRMAC LDTLB NOP DIV0U RTS SLEEP RTE MOVT STS MACH, Rn STS MACL, Rn STS STS STS X0, Rn STS X1, Rn STS Rn PR, Rn DSR, Rn Y0, Rn STS STS A0, Rn Y1, Rn 00MD 1010 01MD 1010 10MD 1010 Fx 1011 Rev. 1.00, 02/04, page 150 of 804 Instruction Code MSB 0000 Rn Rm Fx: 0000 Fx: 0001 MD: 01 Rn Fx: 0010 MD: 10 MOV.L @(R0, Rm), Rn Fx: 0011 to 1111 MD: 11 MAC.L @Rm+,@Rn+ LSB MD: 00 Rn 11MD MOV. B @(R0, Rm), MOV.W @(R0, Rm), 0001 Rn Rm disp MOV.L Rm, @(disp:4, Rn) 0010 Rn 0010 Rn 0010 Rn 0010 Rn 0011 Rn 0011 Rn 0011 Rn 0011 Rn 0100 Rn 0100 Rn 0100 Rn Rm Rm Rm Rm Rm Rm Rm Rm Fx Fx Fx 00MD MOV.B Rm, @Rn MOV.W Rm, @Rn Rm, @-Rn Rm, Rn Rm, Rn MOV.L MOV.L XOR MULU.W CMP/HS Rm, @Rn Rm, @-Rn Rm, Rn Rm, Rn Rm, Rn Rm, Rn Rm, Rn Rm, Rn Rn Rn DIV0S OR Rm, Rn Rm, Rn 01MD MOV.B Rm, @-Rn MOV.W 10MD TST Rm, Rn AND 11MD CMP/STR 00MD CMP/EQ 01MD DIV1 10MD SUB 11MD ADD 0000 0001 0010 SHLL SHLR Rm, Rn XTRCT Rm, Rn MULSW Rm, Rn CMP/GE Rm, Rn CMP/GT Rm, Rn SUBV ADDV Rm, Rn Rm, Rn Rm, Rn Rm, Rn Rm, Rn Rn Rn DMULU.L Rm,Rn CMP/HI SUBC DMULS.L Rm,Rn DT CMP/PZ STS.L Rn Rn ADDC SHAL SHAR STS.L MACH, @-Rn MACL, @-Rn STS.L PR, @-Rn 0100 Rn 0100 Rn 0100 Rn 00MD 0011 01MD 0011 10MD 0011 STC.L SR, @-Rn STC.L SPC, @-Rn STC.L R0_BANK, @-Rn STC.L STC.L STC.L GBR, @-Rn MOD, @-Rn STC.L VBR, @-Rn STC.L RS, @-Rn STC.L R2_BANK, @-Rn STC.L R6_BANK, @-Rn ROTCL Rn ROTCR Rn LDS.L @Rm+, PR STC.L STC.L STC.L SSR, @-Rn RE, @-Rn R1_BANK, @-Rn STC.L R5_BANK, @-Rn SETRC Rn CMP/PL Rn LDS.L @Rm+, MACL R3_BANK, @-Rn STC.L R7_BANK, @-Rn 0100 Rn 11MD 0011 STC.L R4_BANK, @-Rn 0100 Rn 0100 Rn 0100 Rm Fx Fx 0100 0101 ROTL ROTR LDS.L Rn Rn 00MD 0110 @Rm+, MACH 0100 Rm 0100 Rm 01MD 0110 10MD 0110 LDS.L @Rm, X0 LDS.L @Rm, X1 LDS.L @Rm, DSR LDS.L @Rm, Y0 LDS.L @Rm, A0 LDS.L @Rm, Y1 Rev. 1.00, 02/04, page 151 of 804 Instruction Code MSB 0100 Rm 0100 Rm 0100 Rm Fx: 0000 Fx: 0001 MD: 01 LDC.L @Rm+, GBR Fx: 0010 MD: 10 LDC.L @Rm+, VBR LDC.L @Rm+, RS LDC.L @Rm+, R2_BANK LDC.L @Rm+, R6_BANK SHLL16 Rn SHLR16 Rn LDS LDS Rm, PR Rm, DSR Rm, Y0 @Rm Fx: 0011 to 1111 MD: 11 LDC.L @Rm+, SSR LDC.L @Rm+, RE LDC.L @Rm+, R3_BANK LDC.L @Rm+, R7_BANK LSB MD: 00 00MD 0111 01MD 0111 10MD 0111 LDC.L @Rm+, SR LDC.L @Rm+, SPC LDC.L @Rm+, MOD LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R5_BANK SHLL8 Rn SHLR8 Rn Rm, MACL 0100 Rm 11MD 0111 LDC.L @Rm+, R4_BANK 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm Fx Fx 1000 1001 SHLL2 Rn SHLR2 Rn LDS 00MD 1010 01MD 1010 10MD 1010 1011 Rm, MACH LDS LDS LDS Rm, A0 Rm, Y1 LDS JSR Rm, X0 @Rm LDS TAS.B Rm, X1 @Rn LDS JMP 0100 Rm/R Fx n 0100 Rn 0100 Rn 0100 Rm 0100 Rm 0100 Rm 0100 Rm 0100 Rn 0101 Rn 0110 Rn 0110 Rn Rm Rm 1100 1101 SHAD SHLD Rm, Rn Rm, Rn LDC LDC Rm, GBR Rm, MOD LDC LDC Rm, VBR Rm, RS Rm, R2_BANK Rm, R6_BANK LDC Rm, SSR LDC Rm, RE LDC Rm, R3_BANK LDC Rm, R7_BANK 00MD 1110 01MD 1110 10MD 1110 11MD 1110 Rm Rm Rm Rm 1111 disp 00MD 01MD LDC Rm, SR LDC Rm, SPC LDC Rm, R0_BANK LDC LDC Rm, R4_BANK LDC MAC.W @Rm+, @Rn+ MOV.L MOV.B MOV.B Rn (disp:4, Rm), Rn Rm, R1_BANK LDC Rm, R5_BANK LDC @Rm, Rn MOV.W @Rm, Rn @Rm+, MOV.W @Rm+, Rn MOV.L @Rm, Rn MOV.L @Rm+, Rn MOV NOT Rm, Rn Rm, Rn 0110 Rn 0110 Rn 0111 Rn Rm Rm imm 10MD 11MD SWAP.B Rm, Rn EXTU.B Rm, Rn ADD #imm : 8, Rn SWAP.W Rm, Rn EXTU.W Rm, Rn NEGC Rm, Rn EXTS.B Rm, Rn NEG Rm, Rn EXTS.W Rm, Rn 1000 00MD Rn imm disp MOV.B R0, @(disp: 4, Rn) MOV.W R0, @(disp: 4, Rn) SETRC #imm Rev. 1.00, 02/04, page 152 of 804 Instruction Code Fx: 0000 MSB 1000 01MD Rm Fx: 0001 MD: 01 MOV.W @(disp: 4, Rm), R0 disp: 8 disp: 8 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 LSB MD: 00 disp MOV.B @(disp:4, Rm), R0 1000 10MD imm/disp 1000 11MD imm/disp 1001 Rn 1010 disp 1011 disp 1100 00MD imm/disp disp CMP/EQ #imm:8, R0 BT LDRS @(disp:8,PC) BT/S BF LDRE @(disp:8,PC) BF/S disp: 8 disp: 8 MOV.W (disp : 8, PC), Rn BRA BSR MOV.B R0, @(disp: 8, GBR) disp : 12 disp: 12 MOV.W R0, @(disp: 8, GBR) MOV.W @(disp: 8, GBR), R0 #imm: 8, R0 MOV.L R0, @(disp: 8, GBR) MOV.L @(disp: 8, GBR), R0 XOR XOR.B #imm: 8, @(R0, GBR) #imm: 8, R0 MOVA @(disp: 8, PC), R0 OR OR.B #imm: 8, @(R0, GBR) #imm: 8, R0 TRAPA #imm: 8 1100 01MD disp MOV.B @(disp: 8, GBR), R0 1100 10MD imm 1100 11MD imm TST TST.B #imm: 8, R0 AND AND.B #imm: 8, @(R0, GBR) #imm: 8, @(R0, GBR) 1101 Rn 1110 Rn 1111 00** 1111 01** 1111 10** disp imm ******** ******** ******** MOV.L @(disp: 8, PC), Rn MOV #imm:8, Rn MOVX.W, MOVY.W Double data transfer instruction MOVS.W, MOVS.L Single data transfer instruction MOVX.W, MOVY.W Double data transfer instruction, with DSP parallel operation instruction (32-bit instruction ) 1111 11** ******** Notes: 1. For details, refer to the SH-3/SH-3E/SH3-DSP Programming Manual. 2. Instructions in the hatched areas are DSP extended instructions. These instructions can be executed only when the DSP bit in the SR register is set to 1. Rev. 1.00, 02/04, page 153 of 804 Rev. 1.00, 02/04, page 154 of 804 Section 4 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing. In addition, a function to control processing requested by LSI on-chip modules or an LSI external module to the CPU may also be required. Transferring control to a user-defined exception handling routine and executing the process to support the above functions are called exception handling. This LSI has two types of exceptions: general exceptions and interrupts. The user can execute the required processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program. A reset input can terminate the normal program execution and pass control to the reset vector after register initialization. This reset operation can also be regarded as an exception handling. This section describes an overview of the exception handling operation. Here, general exceptions and interrupts are referred to as exception handling. For interrupts, this section describes only the process executed for interrupt requests. For details on how to generate an interrupt request, refer to section 8, Interrupt Controller (INTC). 4.1 Register Descriptions There are four registers for exception handling. A register with an undefined initial value should be initialized by the software. Refer to section 27, List of Registers, for the register addresses and register states in each process. * * * * TRAPA exception register (TRA) Exception event register (EXPEVT) Interrupt event register 2 (INTEVT2) Exception address register (TEA) Rev. 1.00, 02/04, page 155 of 804 Figure 4.1 shows the bit configuration of each register. 31 0 31 0 31 0 31 TEA 12 11 INTEVT2 0 TEA 12 11 EXPEVT 0 INTEVT2 10 9 TRA 21 0 0 0 EXPEVT TRA Figure 4.1 Register Bit Configuration 4.1.1 TRAPA Exception Register (TRA) TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction is executed. Only bits 9 to 2 of the TRA can be re-written using the software. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 9 to 2 1 0 TRA All 0 R/W R 8-bit Immediate Data Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 31 to 10 Rev. 1.00, 02/04, page 156 of 804 4.1.2 Exception Event Register (EXPEVT) EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified by the hardware when an exception occurs. Only bits 11 to 0 of EXPEVT can be re-written using the software. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 11 to 0 EXPEVT * R/W 12-bit Exception Code Note: Initialized to H'000 at power-on reset and H'020 at manual reset. 31 to 12 4.1.3 Interrupt Event Register 2 (INTEVT2) INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified using the software. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 INTEVT2 R 12-bit Exception Code 31 to 12 4.1.4 Exception Address Register (TEA) TEA is assigned to address H'FFFFFFFC and stores the virtual address for an exception occurrence when an exception related to memory accesses occurs. TEA can be modified using the software. Bit 31 to 0 Bit Name TEA Initial Value All 0 R/W R/W Description Virtual Address For Exception Rev. 1.00, 02/04, page 157 of 804 4.2 4.2.1 Exception Handling Function Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) instruction is issued by the exception handler routine on completion of the routine, restoring the contents of PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations. If an exception occurs and the CPU accepts it, operations 1 to 8 are executed. 1. 2. 3. 4. 5. 6. The contents of PC are saved in SPC. The contents of SR are saved in SSR. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. The mode (MD) bit in SR is set to 1 to place the privileged mode. The register bank (RB) bit in SR is set to 1. When an exception source is a general exception, an exception code identifying the exception event is written to EXPEVT. When an exception source is an interrupt, an exception code is written to INTEVT2. If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA instruction is set to TRA. For an exception related to memory accesses, the virtual address where the exception occurred is written to TEA. Instruction execution jumps to the designed exception vector address to invoke the handler routine. 7. 8. The above operations from 1 to 8 are executed in sequence. During these operations, no other exceptions may be accepted unless multiple exception acceptance is enabled. In an exception handling routine for a general exception, the appropriate exception handling must be executed based on an exception source determined by the EXPEVT. In an interrupt exception handling routine, the appropriate exception handling must be executed based on an exception source determined by the INTEVT2. After the exception handling routine has been completed, program execution can be resumed by executing an RTE instruction. The RTE instruction causes the following operations to be executed. Rev. 1.00, 02/04, page 158 of 804 1. 2. 3. The contents of the SSR are restored into the SR to return to the processing state in effect before the exception handling took place. A delay slot instruction of the RTE instruction is executed.* Control is passed to the address stored in the SPC. The above operations from 1 to 3 are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction, a status different from that in effect before the exception handling can also be specified. Note: * For details on the CPU processing mode in which RTE delay slot instructions are executed, please refer to section 4.5, Usage Notes. 4.2.2 Exception Vector Addresses A vector address for general exceptions is determined by adding a vector offset to a vector base address. The vector offset for general exceptions is H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into the vector base register (VBR) using the software. The vector base address should reside in the virtual address (P1 or P2). 4.2.3 Exception Codes The exception codes are written to bits 11 to 0 of the EXPEVT register (for reset or general exceptions) or the INTEVT2 register (for interrupt requests) to identify each specific exception event. See section 8, Interrupt Controller (INTC), for details of the exception codes for interrupt requests. Table 4.1 lists exception codes for resets and general exceptions. 4.2.4 Exception Request and BL Bit (Multiple Exception Prevention) The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1, acceptance of general exceptions is restricted as described below, making it possible to effectively prevent multiple exceptions from being accepted. If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is accepted when the BL bit is cleared to 0. If the CPU is in power-down mode, an interrupt is accepted even if the BL bit is set to 1 and the CPU returns from power-down mode. A DMA address error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit is cleared to 0. User break requests generated while the BL bit is set are ignored and are not retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0. If a general exception other than a DMA address error or user break occurs while the BL bit is set to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules Rev. 1.00, 02/04, page 159 of 804 other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and this status is not detected by an external device. To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0. Before restoring the SPC and SSR, the BL bit must be set to 1. 4.2.5 Exception Source Acceptance Timing and Priority Exception Request of Instruction Synchronous Type and Instruction Asynchronous Type: Resets and interrupts are requested asynchronously regardless of the program flow. In general exceptions, a DMA address error and a user break under the specific condition are also requested asynchronously. The user cannot expect on which instruction an exception is requested. For general exceptions other than a DMA address error and a user break under a specific condition, each general exception corresponds to a specific instruction. Re-execution Type and Processing-completion Type Exceptions: All exceptions are classified into two types: a re-execution type and a processing-completion type. If a re-execution type exception is accepted, the current instruction executed when the exception is accepted is terminated and the instruction address is saved to the SPC. After returning from the exception processing, program execution resumes from the instruction where the exception was accepted. In a processing-completion type exception, the current instruction executed when the exception is accepted is completed, the next instruction address is saved to the SPC, and then the exception processing is executed. During a delayed branch instruction and delay slot, the following operations are executed. A reexecution type exception detected in a delay slot is accepted before executing the delayed branch instruction. A processing-completion type exception detected in a delayed branch instruction or a delay slot is accepted when the delayed branch instruction has been executed. In this case, the acceptance of delayed branch instruction or a delay slot precedes the execution of the branch destination instruction. In the above description, a delay slot indicates an instruction following an unconditional delayed branch instruction or an instruction following a conditional delayed branch instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed branch, the normal processing is executed. Acceptance Priority and Test Priority: Acceptance priorities are determined for all exception requests. The priority of resets, general exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the CPU status. Interrupts are accepted only when resets or general exceptions are not requested. If multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. Rev. 1.00, 02/04, page 160 of 804 1. 2. 3. 4. 5. 6. 7. 8. A processing-completion type exception generated at the previous instruction* A user break before instruction execution (re-execution type) An exception related to an instruction fetch (CPU address error) An exception caused by an instruction decode (General illegal instruction exceptions and slot illegal instruction exceptions: re-execution type, unconditional trap: processing-completion type) An exception related to data access (CPU address error) Unconditional trap (processing-completion type) A user break other than one before instruction execution (processing-completion type) DMA address error (processing-completion type) Note: * If a processing-completion type exception is accepted at an instruction, exception processing starts before the next instruction is executed. This exception processing executed before an exception generated at the next instruction is detected. Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all exception requests being processed. Rev. 1.00, 02/04, page 161 of 804 Table 4.1 Exception Type Exception Event Vectors Current Instruction Exception Event Power-on reset Manual reset Priority* 1 1 1 Exception Order 1 2 Process at BL=1 Reset Reset Excep-tion 5 Code* H'000 H'020 Vector Offset Reset Aborted (Instruction asynchronous type) General Re-executed User break(before 2 exception instruction events execution) (Instruction CPU address error 2 synchro(instruction access) nous type) 4 * Illegal general instruction exception Illegal slot instruction exception 2 0 Ignored H'1E0 H'00000100 1 Reset H'0E0 H'00000100 2 Reset H'180 H'00000100 2 2 Reset H'1A0 H'00000100 CPU address error 2 4 (data read/write)* Completed Unconditional trap (TRAPA instruction) User breakpoint (After instruction execution, address) General Completed exception events (Instruction asynchronous type) 2 3 4 Reset Reset H'0E0/ H'100 H'160 H'00000100 H'00000100 2 5 Ignored H'1E0 H'00000100 User breakpoint 2 (Data break, I-BUS break) DMA address error 2 5 Ignored H'1E0 H'00000100 6 Retained H'5C0 H'00000100 Interrupt (Instruction asynchronous type) Completed Nonmaskable interrupt (NMI) 3* 2 Retained Retained * * 3 H'00000600 H'00000600 External hardware 4* interrupt (IRQ interrupt) H-UDI interrupt 4* 2 3 2 Retained Retained * * 3 H'00000600 H'00000600 On-chip peripheral 4* module interrupt 2 3 Rev. 1.00, 02/04, page 162 of 804 Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest. A reset has the highest priority. An interrupt is accepted only when general exceptions are not requested. 2. For details on priorities in multiple interrupt sources, refer to section 8, Interrupt Controller (INTC). 3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The interrupt source code is specified in interrupt event register 2 (INTEVT2). For details, refer to section 8, Interrupt Controller (INTC). 4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code and vector offset are specified. 5. Exception codes H'040, H'060, H'080, H'0A0, H'0C0, H'0D0, H'120, H'140, and H'3E0 are reserved. Rev. 1.00, 02/04, page 163 of 804 4.3 Individual Exception Operations This section describes the conditions for specific exception handling, and the processor operations. Resets and general exceptions are explained in this section. For details of interrupts, see section 8, Interrupt Controller (INTC) 4.3.1 Resets Power-On Reset: * Conditions RESETP is low, power-on reset by WDT is requested, H-UDI reset * Operations Set EXPEVT to H'000, initialize VBR and SR, and branch to PC = H'A0000000.* The VBR register is cleared to H'00000000 by the initialization. In the SR register, the bits MD, RB, and BL are set to 1, the DSP bit is cleared to 0, and interrupt mask bits (I3 to I0) are set to B'1111. Initialize the CPU and on-chip peripheral modules. For details, refer to the register descriptions in the relevant sections. Perform a reset by the RESETP pin low at power supply. Note: * After a power-on reset, though address is H'A0000000, if the BOOT_E pin is asserted low, a branch is made to the ROM area for the boot function and the boot processing starts (see section 17, Boot Function). For the details of the H_UDI reset, see section 26, User Debugging Interface (H-UDI). Manual Reset: * Conditions Manual reset by WDT is request * Operations Set EXPEVT to H020, initialize VBR and SR, and branch to PC = H'A0000000.* The VBR register is cleared to H'00000000 by the initialization. In the SR register, the bits MD, RB, and BL are set to 1, the DSP bit is cleared to 0, and interrupt mask bits (I3 to I0) are set to B'1111. Initialize the CPU and on-chip peripheral modules. A register initialized by a power-on reset is different from that is initialized by a manual reset. For details, refer to the register descriptions in the relevant sections. Note: * After a manual reset, if the BOOT_E pin is asserted low, a branch is made to the ROM area for the boot function and the boot processing starts as in the case of the power-on reset. Rev. 1.00, 02/04, page 164 of 804 4.3.2 General Exceptions CPU address error: * Conditions Instruction is fetched from odd address (4n + 1, 4n + 3) Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3) Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user mode * Types Instruction synchronous, re-execution type * Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) * Exception code An exception occurred during read: H'0E0 An exception occurred during write: H'100 * Remarks The virtual address (32 bits) that caused the exception is set in TEA. Illegal general instruction exception: * Conditions When undefined code not in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For details on undefined code, refer to section 2.6.2, Operation Code Map. When an undefined code other than H'FC00 to H'FFFF is decoded, operation cannot be guaranteed. When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. * Types Instruction synchronous, re-execution type * Save address An instruction address where an exception occurs Rev. 1.00, 02/04, page 165 of 804 * Exception code H'180 * Remarks None Illegal slot instruction: * Conditions When undefined code in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. When an instruction that rewrites PC in a delay slot is decoded Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR * Types Instruction synchronous, re-execution type * Save address A delayed branch instruction address * Exception code H'1A0 * Remarks None Unconditional trap: * Conditions TRAPA instruction executed * Types Instruction synchronous, processing-completion type * Save address An address of an instruction following TRAPA * Exception code H'160 * Remarks The exception is a processing-completion type, so PC of the instruction after the TRAPA instruction is saved to SPC. The 8-bit immediate value in the TRAPA instruction is set in TRA[9:2]. Rev. 1.00, 02/04, page 166 of 804 User break point trap: * Conditions When a break condition set in the user break controller is satisfied * Types Break (L bus) before instruction execution: Instruction synchronous, re-execution type Operand break (L bus): Instruction synchronous, processing-completion type Data break (L bus): Instruction asynchronous, processing-completion type I bus break: Instruction asynchronous, processing-completion type * Save address Re-execution type: An address of the instruction where a break occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) Completion type: An address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) * Exception code H'1E0 * Remarks For details on user break controller, refer to section 25, User Break Controller (UBC). DMA address error: * Conditions Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) * Types Instruction asynchronous, processing-completion type * Save address An address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) * Exception code H'5C0 * Remarks An exception occurs when a DMA transfer is executed while an illegal instruction address described above is specified in the DMAC. Since the DMAC transfer is performed asynchronously with the CPU instruction operation, an exception is also requested asynchronously with the instruction execution. For details on DMAC, refer to section 10, Direct Memory Access Controller (DMAC). Note: Address error does not occurred in the USB host since the hardware automatically recognizes the address and performs accessing data of enough bit length. Rev. 1.00, 02/04, page 167 of 804 4.4 Exception Processing While DSP Extension Function is Valid In DSP mode (the DSP bit of SR is set to 1), some exception processing acceptance conditions or exception processing may be changed. 4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is executed when the DSP bit of SR is cleared to 0 (in a mode other than the DSP mode), an illegal instruction exception occurs. In the DSP mode, STC and LDC instructions for the SR register can be executed even in user mode. (Note, however, that only the RC[11:0], DMX, DMY, and RF[1:0] bits in the DSP extension bits can be changed.) 4.4.2 CPU Address Error In the DSP mode, a part of the space P2 (Uxy area: H'A5000000 to H'A5FFFFFF) can be accessed in user mode and no CPU address error will occur even if the area is accessed. 4.4.3 Exception in Repeat Control Period If an exception is requested or an exception is accepted during repeat control, the exception may not be accepted correctly or a program execution may not be returned correctly from exception processing that is different from the normal state. These restrictions may occur from repeat detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section, this period is called the repeat control period. The following shows program examples where the number of instructions in the repeat loop is 4 or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction address are described as RptDtct. The first, second, and third instructions following the repeat detection instruction are described as RptDtct1, RptDtct2, and RptDtct3. In addition, [A], [B], [C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table 4.2 summarizes the instruction positions regarding a repeat loop and restriction types. Rev. 1.00, 02/04, page 168 of 804 Table 4.2 Instruction Position [A] [B] [C1] [C2] Notes: 1. 2. 3. 4. Instruction Positions regarding a repeat loop and Restriction Types SPC* 1 Illegal Instruction*2 Interrupt, Break*3 CPU Address Error*4 Retained Added Illegal Added Retained Retained Instruction/data Instruction/data A specific address is specified in the SPC if an exception occurs while SR.RC[11:0] 2. Some of instructions are turned to be illegal instructions while SR.RC[11:0] 1. An interrupt, break or DMA address error request is retained while SR.RC[11:0] 1. A specific exception code is specified while SR.RC[11:0] 1. * Example 1: Repeat loop consisting of four instructions LDRS RptStart ; [A] ; [A] LDRE RptDtct + 4 SETRC #4 instr0 RptStart: instr1 ......... ......... RptDtct: RptDtct ; [A] ; [A] ; [A][Repeat start instruction] ; [A] ; [A] ; [B] A repeat detection instruction is an instruction three instructions before a repeat end instruction ; [C1] ; [C2] ; [C2][Repeat end instruction] ; [A] RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext Rev. 1.00, 02/04, page 169 of 804 * Example 2: Repeat loop consisting of three instructions LDRS RptDtct + 4 LDRE RptDtct + 4 SETRC #4 RptDtct: RptDtct ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction RptStart: RptDtct1 RptDtct2 RptEnd: RptDtct3 InstrNext ; [C1][Repeat start instruction] ; [C2] ; [C2][Repeat end instruction] ; [A] ; [A] ; [A] * Example 3: Repeat loop consisting of two instructions LDRS RptDtct + 6 LDRE RptDtct + 4 SETRC #4 RptDtct: RptDtct ; [A] ; [B] A repeat detection instruction is an instruction prior to a RptStart: RptDtct1 RptEnd: RptDtct2 InstrNext repeat start instruction ; [C1][Repeat start instruction] ; [C2][Repeat end instruction] ; [A] ; [A] ; [A] * Example 4: Repeat loop consisting of one instruction LDRS RptDtct + 8 LDRE RptDtct + 4 SETRC #4 RptDtct: RptDtct ; [A] ; [B] A repeat detection instruction is an instruction prior to a repeat start instruction RptStart: RptEnd: RptDtct1 InstrNext ; [C1][Repeat start instruction]== [Repeat end instruction] ; [A] ; [A] ; [A] Rev. 1.00, 02/04, page 170 of 804 SPC Saved by an Exception in Repeat Control Period: If an exception is accepted in the repeat control period while the repeat counter (RC[11:0]) in the SR register is two or greater, the program counter to be saved may not indicate the value to be returned correctly. To execute the repeat control after returning from an exception processing, the return address must indicate an instruction prior to a repeat detection instruction. Accordingly, if an exception is accepted in repeat control period, an exception other than re-execution type exception by a repeat detection instruction cannot return to the repeat control correctly. Table 4.3 SPC Value when a Re-Execution Type Exception Occurs in Repeat Control Number of Instructions in a Repeat Loop 1 RptDtct RptDtct1 2 RptDtct RptDtct1 RptDtct1 3 RptDtct RptDtct1 RptDtct1 RptDtct1 4 or Greater RptDtct RptDtct1 RS-4 RS-2 Instruction Where an Exception Occurs RptDtct RptDtct1 RptDtct2 RptDtct3 Note: The following symbols are used here. RptDtct: Repeat detection instruction address RptDtct1: An instruction address one instruction following the repeat detection instruction (In a repeat loop consisting of one to three instructions, RptDtct1 is equal to RptStart.) RptDtct2: An instruction address two instruction following the repeat detection instruction RptDtct3: An instruction address three instruction following the repeat detection instruction RS: Repeat start instruction address If a re-execution type exception is accepted at an instruction in the hatched areas above, a return address to be saved in the SPC is incorrect. If SR.RC[11:0] is 1 or 0, a correct return address is saved in the SPC. Rev. 1.00, 02/04, page 171 of 804 Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is executed at the address following RptDtct1, a general illegal instruction exception occurs. For details on an address to be saved in the SPC, refer to section 4.4.3, Exception in Repeat Control Period. * Branch instructions BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA * Repeat control instructions SETRC, LDRS, LDRE * Load instructions for SR, RS, and RE LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. An Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some exception will be retained to prevent an exception acceptance at an instruction where returning from the exception cannot be performed correctly. For details, refer to repeat loop program examples (1) to (4). In the examples, exceptions generated at instructions indicated as [B], and [C] ([C1] or [C2]) the following processing is executed. * Interrupt, DMA address error An exception request is not accepted and retained at instructions [B] and [C]. If an instruction indicates as [A] is executed the next time, an exception request is accepted.* As shown in examples (1) to (4), any interrupt or DMA address error cannot be accepted in a repeat loop consisting of four instructions or less. Note: An interrupt request or a DMA address error exception request is retained in the interrupt controller (INTC) and the direct memory access controller (DMAC) until the CPU can accept a request. * User break before instruction execution A user break before instruction execution is accepted at instruction [B], and an address of instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but the exception request is retained until an instruction [A] or [B] is executed the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. Rev. 1.00, 02/04, page 172 of 804 * User break after instruction execution A user break after instruction execution cannot be accepted at instructions [B] and [C] but the exception request is retained until an instruction [A] or [B] is executed the next time. Then, the exception request is accepted before an instruction [A] or [B] is executed. In this case, an address of instruction [A] or [B] is saved in the SPC. Table 4.4 Restrictions of Exception Acceptance in the Repeat Loop Instruction [B] Not accepted Not accepted Accepted Not accepted Instruction [C] Not accepted Not accepted Not accepted Not accepted Exception Type Interrupt DMA address error User break before instruction execution User break after instruction execution CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT. The SPC is saved according to the description in section 4.4.3, SPC Saved by an Exception in Repeat Control Period. After the CPU address error exception processing, the repeat control cannot be returned correctly. To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the repeat control period. Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. The restriction occurs when SR.RC[11:0] 1. Rev. 1.00, 02/04, page 173 of 804 Table 4.5 Instruction Where a Specific Exception Occurs When a Memory Access Exception Occurs in Repeat Control (SR.RC[11:0] 1) Number of Instructions in a Repeat Loop 1 2 3 4 or Greater Instruction Where an Exception Occurs RptDtct RptDtct1 RptDtct2 RptDtct3 Note: Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access Instruction/data access The following symbols are used here. RptDtct: Repeat detection instruction address RptDtct1: An instruction address one instruction following the repeat detection instruction RptDtct2: An instruction address two instruction following the repeat detection instruction RptDtct3: An instruction address three instruction following the repeat detection instruction Rev. 1.00, 02/04, page 174 of 804 4.5 1. Usage Notes An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according to the SR before restore. An acceptance of other exceptions is determined by the SR after restore, processing mode, and BL bit value. A processingcompletion type exception is accepted before an instruction at the RTE branch destination address is executed. However, note that the correct operation cannot be guaranteed if a reexecution type exception occurs. In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be accepted. If the MD and BL bits of the SR register are changed by the LDC instruction, an exception is accepted according to the changed SR value from the next instruction.* A processingcompletion type exception is accepted after the next instruction is executed. An interrupt and DMA address error in processing-completion type exceptions are accepted before the next instruction is executed. 2. 3. Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched and an instruction fetch exception is accepted according to the modified SR value. Rev. 1.00, 02/04, page 175 of 804 Rev. 1.00, 02/04, page 176 of 804 Section 5 Cache 5.1 * * * * * * Features Capacity: 16 kbytes Structure: Instructions/data mixed, 4-way set associative Locking: Way 2 and way 3 are lockable Line size: 16 bytes Number of entries: 256 entries/way Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0 individually. Group 1 (P0, P3, and U0 areas) Group 2 (P1 area) * Replacement method: Least-recently used (LRU) algorithm 5.1.1 Cache Structure The cache mixes instructions and data and uses a 4-way set associative system. It is composed of four ways (banks), and each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The entry data is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 4 kbytes (16 bytes x 256 entries) in the cache as a whole (4 ways). The cache capacity is 16 kbytes as a whole. Figure 5.1 shows the cache structure. Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 V U Tag address Entry 1 . . . . . . 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 255 24 (1 + 1 + 22) bits 255 128 (32 x 4) bits LW0 to LW3: Longword data 0 to 3 255 6 bits Figure 5.1 Cache Structure CASH001B_00020030200 Rev. 1.00, 02/04, page 177 of 804 Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31 to10 for memory access) used for comparison during cache searches. In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. The tag address is not initialized by either a power-on or manual reset. Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way. Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 5.1 shows the relationship between the LRU bits and the way to be replaced when the cache locking mechanism is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section 5.2.2, Cache Control Register 2.) If a bit pattern other than those listed in table 5.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 5.1. The LRU bits are initialized to B'000000 by a power-on reset, but are not initialized by a manual reset. Table 5.1 LRU and Way Replacement (when Cache Locking Mechanism is Disabled) Way to be Replaced 3 2 1 0 LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00, 02/04, page 178 of 804 5.2 Register Descriptions The cache has the following registers. For details on register addresses and register access size, refer to section 27, List of Registers. * Cache control register 1 (CCR1) * Cache control register 2 (CCR2) 5.2.1 Cache Control Register 1 (CCR1) The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which invalidates all cache entries), and WT and CB bits (which select either write-through mode or write-back mode). Programs that change the contents of the CCR1 register should be placed in address space that is not cached. Bit 31 to 4 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 3 CF 0 R/W Cache Flush Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). This bit is always read as 0. Write-back to external memory is not performed when the cache is flushed. 2 CB 0 R/W Write-Back Indicates the cache's operating mode for space P1. 0: Write-through mode 1: Write-back mode 1 WT 0 R/W Write-Through Indicates the cache's operating mode for spaces P0, U0, and P3. 0: Write-back mode 1: Write-through mode 0 CE 0 R/W Cache Enable Indicates whether the cache function is used. 0: The cache function is not used. 1: The cache function is used. Rev. 1.00, 02/04, page 179 of 804 5.2.2 Cache Control Register 2 (CCR2) The CCR2 register controls the cache locking mechanism in DSP mode only. The CPU enters DSP mode when the DSP bit (bit 12) in the status register (SR) is set to 1. The cache locking mechanism is disabled in non-DSP mode (DSP bit = 0). When a prefetch instruction (PREF@Rn) is issued in DSP mode and a cache miss occurs, the line of data pointed to by Rn will be loaded into the cache, according to the setting of bits 9 and 8 (W3LOAD, W3LOCK) and bits 1 and 0 (W2LOAD, W2LOCK in CCR2). Table 5.2 shows the relationship between the settings of bits and the way that is to be replaced when the cache is missed by a prefetch instruction. On the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the cache and the valid entry is held. For example, a prefetch instruction is issued while bits W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0, the cache is hit and new data is not loaded into way 3. In DSP mode, bits W3LOCK and W2LOCK restrict the way that is to be replaced, when instructions other than the prefetch instruction are issued. Table 5.3 shows the relationship between the settings of bits in CCR2 and the way that is to be replaced when the cache is missed by instructions other than the prefetch instruction. Programs that change the contents of the CCR2 register should be placed in address space that is not cached. Rev. 1.00, 02/04, page 180 of 804 Bit 31 to 10 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 9 8 W3LOAD W3LOCK 0 0 R/W R/W Way 3 Load (W3LOAD) Way 3 Lock (W3LOCK) When the cache is missed by a prefetch instruction while in DSP mode and when bits W3LOAD and W3LOCK in CCR2 are set to 1, the data is always loaded into way 3. Under any other condition, the prefetched data is loaded into the way to which LRU points. 7 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 1 0 W2LOAD W2LOCK 0 0 R/W R/W Way 2 Load (W2LOAD) Way 2 Lock (W2LOCK) When the cache is missed by a prefetch instruction while in DSP mode and when bits W2LOAD and W2LOCK in CCR2 are set to 1, the data is always loaded into way 2. Under any other condition, the prefetched data is loaded into the way to which LRU points. Note: W2LOAD and W3LOAD should not be set to 1 at the same time. Table 5.2 DSP Bit 0 1 1 1 1 1 1 Note: * Way Replacement when a PREF Instruction Misses the Cache W3LOAD * * * 0 0 0 1 W3LOCK * 0 0 1 1 * 1 W2LOAD * * 0 * 0 1 0 W2LOCK * 0 1 0 1 1 * Way to be Replaced Determined by LRU (table 5.1) Determined by LRU (table 5.1) Determined by LRU (table 5.4) Determined by LRU (table 5.5) Determined by LRU (table 5.6) Way 2 Way 3 Don't care W3LOAD and W2LOAD should not be set to 1 at the same time. Rev. 1.00, 02/04, page 181 of 804 Table 5.3 DSP Bit 0 1 1 1 1 Note: * Way Replacement when Instructions other than the PREF Instruction Miss the Cache W3LOAD * * * * * W3LOCK * 0 0 1 1 W2LOAD * * * * * W2LOCK * 0 1 0 1 Way to be Replaced Determined by LRU (table 5.1) Determined by LRU (table 5.1) Determined by LRU (table 5.4) Determined by LRU (table 5.5) Determined by LRU (table 5.6) Don't care W3LOAD and W2LOAD should not be set to 1 at the same time. Table 5.4 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0) Way to be Replaced 3 1 0 LRU (Bits 5 to 0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 Table 5.5 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1) Way to be Replaced 2 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 5.6 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1) Way to be Replaced 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00, 02/04, page 182 of 804 5.3 5.3.1 Operation Searching the Cache If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1, P3, and U0 are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.2 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 11 to 4 of the address (virtual) of the access to memory and the tag address of that entry is read. The virtual address (bits 31 to 10) of the access to memory and the physical address (tag address) read from the address array are compared. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 5.2 shows a hit on way 1. Virtual address 31 12 11 4 3 210 Entry selection Longword (LW) selection Ways 0 to 3 Ways 0 to 3 0 1 V U Tag address LW0 LW1 LW2 LW3 255 Address for accessing memory (bits 31 to 10) CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.2 Cache Search Scheme Rev. 1.00, 02/04, page 183 of 804 5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The LRU is updated to indicate that the hit way is the most recently hit way. Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 5.3. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared to 0 and the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cacheupdate cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. 5.3.3 Prefetch Operation Prefetch Hit: The LRU is updated to indicate that the hit way is the most recently hit way. The other contents of the cache are not changed. Instructions and data are not transferred from the cache to the CPU. Prefetch Miss: Instructions and data are not transferred from the cache to the CPU. The way that is to be replaced is shown in table 5.2. The other operations are the same as those for a read miss. 5.3.4 Write Access Write Hit: In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry that has been written to is set to 1, and the LRU is updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the entry that has been written to is not updated, and the LRU is updated to indicate that the hit way is the most recently hit way. Write Miss: In write-back mode, an external cycle starts when a write miss occurs, and the entry is updated. The way to be replaced is shown in table 5.3. When the U bit of the entry which is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The LRU is updated to indicate that the replaced way is the most recently updated way. After the cache has completed its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. Rev. 1.00, 02/04, page 184 of 804 5.3.5 Write-Back Buffer When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the fetching of new entries to the cache completes, the write-back buffer writes the entry back to the external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 5.3 shows the configuration of the write-back buffer. PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31 to 4): Physical address written to external memory Longword 0 to 3: One line of cache data to be written to external memory Figure 5.3 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is placed in an address space to which caching applies, use the memory-mapped cache to make the data invalid and written back, as required. Memory that is shared by this LSI's CPU and DMAC should also be handled in this way. Rev. 1.00, 02/04, page 185 of 804 5.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in privileged mode. The cache is mapped onto the P4 area in virtual address space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 Address Array The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array. In the address field, specify the entry address for selecting the entry, W for selecting the way, A for enabling or disabling the associative operation, and H'F0 for indicating address array access. As for W, B'00 indicates way 0, B'01 indicates way 1, B'10 indicates way 2, and B'11 indicates way 3. In the data field, specify the tag address, LRU bits, U bit, and V bit. Figure 5.4 shows the address and data formats. 0s should be specified in upper three bits (bits 31 to 29) of the tag address. The following three operations are available in the address array. Address-Array Read: Read the tag address, LRU bits, U bit, and V bit for the entry that corresponds to the entry address and way specified by the address field of the read instruction. In reading, the associative operation is not performed, regardless of whether the associative bit (A bit) specified in the address is 1 or 0. Address-Array Write (non-Associative Operation): Write the tag address, LRU bits, U bit, and V bit, specified by the data field of the write instruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. Ensure that the associative bit (A bit) in the address field is set to 0. When writing to a cache line for which the U bit = 1 and the V bit =1, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field of the write instruction. When 0 is written to the V bit, 0 must also be written to the U bit for that entry. Address-Array Write (Associative Operation): When writing with the associative bit (A bit) of the address = 1, the addresses in the four ways for the entry specified by the address field of the write instruction are compared with the tag address that is specified by the data field of the write instruction. Write the U bit and the V bit specified by the data field of the write instruction to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that receives a hit, nothing is written and there is no operation. This function is Rev. 1.00, 02/04, page 186 of 804 used to invalidate a specific entry in the cache. When the U bit of the entry that has received a hit is 1 at this point, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. 5.4.2 Data Array The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. In the address field, specify the entry address for selecting the entry, L for indicating the longword position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array access. As for L, B'00 indicates longword 0, B'01 indicates longword 1, B'10 indicates longword 2, and B'11 indicates longword 3. As for W, B'00 indicates way 0, B'01 indicates way 1, B'10 indicates way 2, and B'11 indicates way 3). Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be set to B'00. Figure 5.4 shows the address and data formats. The following two operations on the data array are available. The information in the address array is not affected by these operations. Data-Array Read: Read the data specified by L of the address filed, from the entry that corresponds to the entry address and the way that is specified by the address filed. Data-Array Write: Write the longword data specified by the data filed, to the position specified by L of the address field, in the entry that corresponds to the entry address and the way specified by the address field. Rev. 1.00, 02/04, page 187 of 804 (1) Address array access (a) Address specification Read access 31 24 23 14 13 12 11 4 3 2 0 1111 0000 Write access 31 24 23 *--------* W Entry address 0 * 0 0 14 13 12 11 4 3 2 0 1111 0000 *--------* W Entry address A * 0 0 (b) Data specification (both read and write accesses) 31 30 29 0 0 0 10 9 4 3 2 1 0 Tag address (28 to 10) LRU X X U V (2) Data array access (both read and write accesses) (a) Address specification 31 24 23 14 13 12 11 4 3 2 1 0 1111 0001 (b) Data specification 31 *--------* W Entry address L 0 0 0 Longword *: Don't care bit X: 0 for read, don't care for write Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access Rev. 1.00, 02/04, page 188 of 804 5.4.3 Usage Examples Invalidating Specific Entries: Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory-mapped cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and a match is found, the entry is written back if the entry's U bit is 1 and the V bit and U bit specified by the write data are written. If no match is found, there is no operation. In the example shown below, R0 specifies the write data and R1 specifies the address. ; R0=H01100010; specification of data for address array access, tag address=B0 0001 0001 0000 0000 00, LRU = B00 0001, U=0, V=0 ; R1=HF0000088; specification of address to be accessed in address array access, way = B00, entry address=B00001000, A=1 ; MOV.L R0,@R1 Reading the Data of a Specific Entry: To read the data field of a specific entry is enabled by the memory-mapped cache access. The longword indicated in the data field of the data array in figure 5.4 is read into the register. In the example shown below, R0 specifies the address and R1 shows what is read. ; R0=HF100 004C; specification of address for data array access, way=B00, entry address=B00000100, L=B11 ; MOV.L @R0,R1 ; Longword 3 is read. Rev. 1.00, 02/04, page 189 of 804 Rev. 1.00, 02/04, page 190 of 804 Section 6 X/Y Memory This LSI has on-chip 8 kbytes of X-memory and Y-memory that can be used to store instructions or data. 6.1 Features * Page There are four pages. The X memory is divided into two pages (pages 0 and 1) and the Y memory is divided into two pages (pages 0 and 1). * Memory map The X/Y memory is located in the virtual address space, physical address space. In the virtual address space, this memory is located in the addresses in P2/Uxy that are shown in table 6.1. These addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP = 1) according to the CPU operating mode. Table 6.1 Page Page 0 of X memory Page 1 of X memory Page 0 of Y memory Page 1 of Y memory X/Y Memory Virtual Addresses Memory Size (16 kbytes in Total Four Pages) H'A5007000 to H'A5007FFF H'A5008000 to H'A5008FFF H'A5017000 to H'A5017FFF H'A5018000 to H'A5018FFF On the other hand, virtual addresses shown in table 6.1 are located in a part of area 1 in the physical address space. When this memory is accessed from the physical address space, addresses in which the upper three bits are 0 in addresses shown in table 6.1 are used. * Ports Each page has three independent read/write ports and is connected to each bus. The X memory is connected to the I bus, X bus, and L bus. The Y memory is connected to the I bus, Y bus, and L bus. The L bus, X bus, and Y bus are used when this memory is accessed from the virtual address space. The I bus is used when this memory is accessed from the physical address space. * Priority order In the event of simultaneous accesses to the same page from different buses, the accesses are processed according to the priority order. The priority order is: I bus > X bus > L bus in the X memory and I bus > Y bus > L bus in the Y memory. XYM0010A_000020030200 Rev. 1.00, 02/04, page 191 of 804 6.2 6.2.1 Operation Access from CPU The 8/16/32-bit access by the CPU can be performed via the L bus or I bus. Methods for accessing by the CPU are via the L bus from the virtual addresses, and via the I bus from the physical addresses. As long as a conflict on the page does not occur, access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU operating mode, access from the CPU is as follows: Privileged mode and privileged DSP mode (SR. MD = 1): The X/Y memory can be accessed by the CPU from spaces P0 and P2. User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the CPU from spaces U0 and Uxy. User mode (SR.MD = 0 and SR.DSP = 0): The X/Y memory can be accessed by the CPU from space U0. 6.2.2 Access from DSP The16/32-bit access by the DSP can be performed via the L bus or I bus. A 16-bit access by the DSP can be performed via the X and Y buses. Methods for accessing from the DSP differ according to instructions. With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory access via the Y bus can be performed simultaneously. In the case of a single data transfer instruction, methods for accessing from the DSP are directly via the L bus from the virtual addresses, and via the I bus from the physical addresses. As long as a conflict on the page does not occur, access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU operating mode, access from the CPU is as follows: Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The X/Y memory can be accessed by the DSP from spaces P0 and P2. User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the DSP from spaces U0 and Uxy. Rev. 1.00, 02/04, page 192 of 804 6.2.3 Access from I Bus Master Module The X/Y memory is always accessed by I bus master modules such as the DMAC and USBH via the I bus, which is a physical address bus. The 8/16/32-bit access is performed by the DMAC and 8/32-bit access is performed by the USBH. When accessing other than the P4 area (A31 to A29 = B'111), three most significant bits of the address are internally set to B'000 even if the logic addresses are specified other than P4 area. Therefore, access is performed through I bus. 6.3 6.3.1 Usage Notes Page Conflict In the event of simultaneous accesses to the same page from different buses, the conflict on the pages occurs. Although each access is completed correctly, this kind of conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such conflict as far as possible. For example, conflict will not arise if different memory or different pages are accessed by each bus. 6.3.2 Bus Conflict The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory by the CPU not via the I bus but from space P2 or Uxy via the L bus, conflict on the I bus can be prevented. 6.3.3 Cache Settings When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled (CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. In a program that requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The relationship described above is summarized in table 6.2. Rev. 1.00, 02/04, page 193 of 804 Table 6.2 Setting CCR1.CE 0 1 Note: Cache Settings Address Space and Access Enabled or Disabled P0, U0 B X P2, Uxy A A A: Enabled (recommended) B: Enabled X: Disabled 6.3.4 Sleep Mode The XYMCLKC bit of memory clock control register (MCCR) should be set to 1 when I bus master module such as DMAC accesses this memory in sleep mode. There is the following restrictions when the X/Ymemory is accessed in the processing the exception handling and interrupt while this function is used. 1. The program of the exception handling and the interrupt processing should not be placed in the X/Y memory and U memory. 2. Eight NOP instructions should be added to the head of the exception handling and the interrupt processing program. 3. When the SLEEP instruction is executed, 16 instructions which include above-mentioned eight NOP instructions for the head of the exception handling and the interrupt processing should be placed outside of cache (Miss hit or non-cacheable area (P2) ). * Example 1 Take out outside cache by using the address-array write (associative operation). (Refer to section 5.4, Memory Mapped Cache in section 5, Cache and Invalidating Specific Entries in section 5.4.3, Usage Examples.) * Example 2 The value of vector base register (VBR) is changed to non-cacheable area (P2) before the SLEEP instruction is executed. In this case, execute the SLEEP instruction after confirming the written VBR value (the branch instruction for the flag confirmation is used). After SLEEP ends, the VBR should be restored with the previous value. Rev. 1.00, 02/04, page 194 of 804 Section 7 U Memory This LSI has on-chip 128-kbyte U memory which can be used to store instructions or data. 7.1 Features * Page There are two pages (pages 0 and 1). * Memory map The U memory is located in both the virtual address space and physical address space. In the virtual address space, this memory is located in the addresses in P2/Uxy that are shown in table 7.1. These addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP = 1) according to the CPU operating mode. Table 7.1 Page Page 0 of U memory Page 1 of U memory U Memory Virtual Addresses Memory Size (128 kbytes in Total Two Pages) H'A55F0000 to H'A55FFFFF H'A5600000 to H'A560FFF On the other hand, virtual addresses shown in table 7.1 are located in a part of area 1 in the physical address space. When this memory is accessed from the physical address space, addresses in which the upper three bits are 0 in addresses shown in table 7.1 are used. * Ports Each page has two independent read/write ports and is connected to the I bus or L bus. The L bus is used when this memory is accessed from the virtual address space. The I bus is used when this memory is accessed from the physical address space. * Priority order In the event of simultaneous accesses to the same page from different buses, the accesses are processed according to the priority order. The priority order is: I bus > L bus. RAMS300B_000020030200 Rev. 1.00, 02/04, page 195 of 804 7.2 7.2.1 Operation Access from CPU The 8/16/32-bit access by the CPU can be performed via the L bus or I bus. Methods for accessing by the CPU are directly via the L bus from the virtual addresses, and via the I bus from the physical addresses. As long as a conflict on the page does not occur, access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU operating mode, access from the CPU is as follows: Privileged mode and privileged DSP mode (SR. MD = 1): The U memory can be accessed by the CPU from spaces P0 and P2. User DSP mode (SR.MD = 0 and SR.DSP = 1): The U memory can be accessed by the CPU from spaces U0 and Uxy. User mode (SR.MD = 0 and SR.DSP = 0): The U memory can be accessed by the CPU from space U0. 7.2.2 Access from DSP The U memory can be accessed from the DSP only by a single data transfer instruction. The16/32 -bit access by the DSP can be performed via the L bus or I bus. The access cannot be performed by an X data transfer instruction and a Y data transfer instruction. Methods for accessing from the DSP are via the L bus from the virtual addresses, and via the I bus from the physical addresses. As long as a conflict on the page does not occur, access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the CPU operating mode, access from the CPU is as follows: Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The U memory can be accessed by the DSP from spaces P0 and P2. User DSP mode (SR.MD = 0 and SR.DSP = 1): The U memory can be accessed by the DSP from spaces U0 and Uxy. 7.2.3 Access from I Bus Master Module The U memory is always accessed by I bus master modules such as the DMAC and USBH via the I bus, which is a physical address bus. The 8/16/32-bit access can be performed by the DMAC and the 8/32-bit access can be performed by the USBH. When accessing other than the P4 area (A31 to A29 = B'111), three most significant bits of the address are internally set to B'000 even if the logic addresses are specified other than P4 area. Therefore, access is performed through I bus. Rev. 1.00, 02/04, page 196 of 804 7.3 7.3.1 Usage Notes Page Conflict In the event of simultaneous accesses to the same page from different buses, the conflict on the pages occurs. Although each access is completed correctly, this kind of conflict tends to lower U memory accessibility. Therefore it is advisable to provide software measures to prevent such conflict as far as possible. For example, conflict will not arise if different memory or different pages are accessed by each bus. 7.3.2 Bus Conflict The I bus is shared by several bus master modules. When the U memory is accessed via the I bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of conflict tends to lower U memory accessibility. Therefore it is advisable to provide software measures to prevent such conflict as far as possible. For example, by accessing the U memory by the CPU not via the I bus but from space P2 or Uxy via the L bus, conflict on the I bus can be prevented. 7.3.3 Cache Settings When the U memory is accessed via the I bus using the cache from the CPU and DSP, correct operation cannot be guaranteed. If the U memory is accessed while the cache is enabled (CCR1.CR = 1), it is advisable to access the U memory via the L bus from space P2 or Uxy. In a program that requires high performance, it is advisable to access the U memory from space P2 or Uxy. The relationship described above is summarized in table 7.2. Table 7.2 Setting CCR1.CE 0 1 Note: Cache Settings Address Space and Access Enabled or Disabled P0, U0 B X P2, Uxy A A A: Enabled (recommended) B: Enabled X: Disabled Rev. 1.00, 02/04, page 197 of 804 7.3.4 sleep mode The UMCLKC bit of memory clock control register (MCCR) should be set to 1 when I bus master module such as DMAC accesses this memory in sleep mode. There is the following restrictions when the U memory is accessed in the processing the exception handling and interrupt while this function is used. 1. The program of the exception handling and the interrupt processing should not be placed in the U memory and X/Y memory. 2. Eight NOP instructions should be added to the head of the exception handling and the interrupt processing program. 3. When the SLEEP instruction is executed, 16 instructions which include above-mentioned eight NOP instructions for the head of the exception handling and the interrupt processing should be placed outside of cache (Miss hit or non-cacheable area (P2) ). * Example 1 Take out outside cache by using the address-array write (associative operation). (Refer to section 5.4, Memory Mapped Cache in section 5, Cache and Invalidating Specific Entries in section 5.4.3, Usage Examples.) * Example 2 The value of vector base register (VBR) is changed to non-cacheable area (P2) before the SLEEP instruction is executed. In this case, execute the SLEEP instruction after confirming the written VBR value (the branch instruction for the flag confirmation is used). After SLEEP ends, the VBR should be restored with the previous value. Rev. 1.00, 02/04, page 198 of 804 Section 8 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 8.1 Features * 16 levels of interrupt priority can be set By setting the interrupt priority registers, the priorities of on-chip peripheral module and IRQ interrupts can be selected from 16 levels for individual request sources. * NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceler. * IRQ interrupts can be set Detection of low level, high level, rising edge, or falling edge * Interrupt request signal can be output (IRQOUT pin) Bus mastership can be required by signaling the external bus master that the external interrupt and on-chip peripheral module interrupt requests have been generated * Interrupts can be enabled or disabled Interrupts can be enabled or disabled individually for each interrupt source with the interrupt mask registers and interrupt mask clear registers. Rev. 1.00, 02/04, page 199 of 804 Figure 8.1 shows a block diagram of the INTC. NMI IRQ0 BT(IRQ1)*1 IRQ2 IRQ3 IRQ4 USBF(IRQ7)*2 DMAC SCIF USBH USBF TMU WDT H-UDI SIOF Input/output control (Interrupt request) Priority identifier Comparator Interrupt request SR I3 I2 I1 I0 CPU IPR ICR IRR0 IMR IMCR Internal bus Bus interface Legend: DMAC : DMA controller SIOF : Serial I/O with FIFO SCIF : Serial communication interfaces with FIFO USBH : USB host controller USBF : USB function controller TMU : Timer unit BT : Bluetooth interface WDT : Watchdog timer H-UDI : User-debugging interface ICR : Interrupt control registers IPR : Interrupt priority registers IMR : Interrupt mask registers IMCR : Interrupt mask clear registers IRR0 : Interrupt request register 0 SR : Status register INTC Notes: 1. The interrupt request pin for the BT (Bluetooth interface) is connected to the IRQ1 pin and is handled as an external interrupt. 2. The interrupt request pin for the USBF (USB function controller) standby recovery is connected to the IRQ7 pin and is handled as an external interrupt. Figure 8.1 Block Diagram of INTC Rev. 1.00, 02/04, page 200 of 804 8.2 Input/Output Pins Table 8.1 shows the INTC pin configuration. Table 8.1 Pin Name NMI IRQ7, IRQ4 to IRQ0* IRQOUT* 2 1 Pin Configuration I/O Input Input Output Description Nonmaskable Interrupt Input Input of interrupt request signal which is not maskable Interrupt Input Input of interrupt request signal Bus Mastership Request Output Signal of interrupt request generation Notes: 1. IRQ1 is used as the bluetooth interface interrupt request pin and does not support an external pin function. IRQ7 is used as the standby recovery interrupt request pin and does not support an external pin function. 2. When the NMI or H-UDI interrupt request is generated and the response time of CPU is short, this pin may not be asserted. 8.3 Register Descriptions The INTC has the following registers. For details on register addresses and register states during each processing, refer to section 27, List of Registers. * * * * * * * * * * * * * * * * * Interrupt control register 0 (ICR0) Interrupt control register 1 (ICR1) Interrupt control register 2 (ICR2) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt request register 0 (IRR0) Interrupt mask register 0 (IMR0) Interrupt mask register 1 (IMR1) Interrupt mask register 4 (IMR4) Interrupt mask register 5 (IMR5) Interrupt mask register 6 (IMR6) Rev. 1.00, 02/04, page 201 of 804 * * * * * * * Interrupt mask register 9 (IMR9) Interrupt mask clear register 0 (IMCR0) Interrupt mask clear register 1 (IMCR1) Interrupt mask clear register 4 (IMCR4) Interrupt mask clear register 5 (IMCR5) Interrupt mask clear register 6 (IMCR6) Interrupt mask clear register 9 (IMCR9) Interrupt Priority Registers A to H (IPRA to IPRH) 8.3.1 IPRA to IPRH are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module and IRQ interrupts. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description These bits set the priority level for each interrupt source in 4-bit units. For details, see table 8.2, Interrupt Sources and IPRA to IPRH. Rev. 1.00, 02/04, page 202 of 804 Table 8.2 Register IPRA IPRB IPRC IPRD Interrupt Sources and IPRA to IPRH Bits 15 to 12 TMU0 WDT IRQ3 IRQ7(for USBF standby recovery interrupt request 3 signal) * DMAC Reserved*1 SCIF0 Reserved*1 Bits 11 to 8 TMU1 Reserved*1 IRQ2 Reserved* 1 Bits 7 to 4 TMU2 Reserved*1 IRQ1(for BT)*2 Reserved* 1 Bits 3 to 0 Reserved*1 Reserved*1 IRQ0 IRQ4 IPRE IPRF IPRG IPRH Reserved*1 Reserved*1 SCIF1 SIOF Reserved*1 USBF Reserved* 1 Reserved*1 USBH Reserved*1 Reserved*1 Reserved*1 Notes: 1. Always read as 0. The write value should always be 0. If 1 is written to the bit, correct operation cannot be guaranteed. 2. IRQ1 is connected to the bluetooth interface (BT) interrupt request signal and cannot be used for other functions. 3. IRQ7 is connected to the USBF (USB function controller) standby recovery interrupt request signal and cannot be used for other functions. As shown in table 8.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F means priority level 15 (the highest level). Rev. 1.00, 02/04, page 203 of 804 8.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. Bit 15 Bit Name NMIL Initial Value 0/1* R/W R Description NMI Input Level Sets the level of the signal input at the NMI pin. This bit can be read from to determine the NMI pin level. This bit cannot be modified. 0: NMI input level is low 1: NMI input level is high 14 to 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 8 NMIE 0 R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal at the NMI pin is detected. 0: Interrupt request is detected at the falling edge of NMI input 1: Interrupt request is detected at the rising edge of NMI input 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Note: * 1 when NMI input is high, 0 when NMI input is low. Rev. 1.00, 02/04, page 204 of 804 8.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ4 to IRQ0 individually: rising edge, falling edge, high level, or low level. Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 14 IRQE* 1 R/W Interrupt Request Enable Enables or disables the use of pins IRQ7, IRQ4 to IRQ0 as six independent interrupt pins. 0 : Use of pins IRQ7, IRQ4 to IRQ0 as six independent interrupt pins enabled 1 : Use of pins IRQ7, IRQ4 to IRQ0 as interrupt pins disabled 13 to 10 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 205 of 804 Bit 9 8 7 6 5 4 3 2 1 0 Bit Name IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial Value 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Select These bits select whether interrupt request signals corresponding to pins IRQ4 to IRQ0 are detected by a rising edge, falling edge, high level, or low level. Bit 2n+1 Bit 2n IRQn1S 0 IRQn0S 0 Interrupt request is detected at the falling edge of IRQn input Interrupt request is detected at the rising edge of IRQn input Interrupt request is detected on low level of IRQn input Interrupt request is detected on high level of IRQn input 0 1 1 1 0 1 Legend: Note: * n = 0 to 4 The IRQE bit must be cleared to 0 before the BL bit in the status register (SR) is cleared to 0 in the initialization routine after reset, and must then not be changed. If the IRQE bit is set to 1 when the BL bit is cleared to 0, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 206 of 804 8.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for the external interrupt input pin IRQ7: rising edge, falling edge, high level, or low level. Bit 15 to 4 Bit Name Initial Value All 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 3 2 IRQ71S IRQ70S 0 0 R/W R/W IRQ7 Sense Select These bits select whether interrupt request signals corresponding to pin IRQ7 are detected by a rising edge, falling edge, high level, or low level. Bit 2n+1 Bit 2n IRQ71S 0 IRQ70S 0 Interrupt request (USBF standby recovery interrupt request) is detected at the falling edge of IRQ7 input Setting prohibited Setting prohibited Setting prohibited 0 1 1 1 0 1 Note: When the USBF standby recovery interrupt request need not to be detected, clear the bits 15 to 12 in IPRD to 0 or set the bit 7 in IMR0 to 1, and the IRQ7 interrupt request should be masked. 1 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0 or the bit7 in IMR0 should be set to 1. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 207 of 804 8.3.5 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ7, IRQ4* to IRQ0. Note: * In this LSI, IRQ7 and IRQ1 are used specific to internal module and cannot function as external pins. Bit 7 6*1 5* 4 3 2 1 0 1 Bit Name IRQ7R* IRQ4R* IRQ3R* IRQ2R* IRQ1R* IRQ0R* 2 2 2 2 2 2 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R R R/W R/W R/W R/W R/W Description IRQn Interrupt Request Indicates whether there is interrupt request input to the IRQn pin. When edge-detection mode is set for IRQn, an interrupt request is cleared by writing 0 to the IRQnR bit after reading IRQnR = 1. When level-detection mode is set for IRQn, these bits indicate whether an interrupt request is input. The interrupt request is set/cleared by only 1/0 input to the IRQn pin. IRQnR 0: No interrupt request input to IRQn pin 1: Interrupt request input to IRQn pin Legend: n = 0 to 4, 7 Notes: 1. Bits 6 to 5 are reserved bits. These bits are always read as undefined value. The write value should always be 0. If 1 is written to the bits, correct operation cannot be guaranteed. 2. The IRQ7R, IRQ4R to IRQ0R bits are cleared to 0 after the IRQE bit in the interrupt control register 1 (ICR1) is cleared to 0 in the initialization routine after reset. 8.3.6 Interrupt Mask Registers 0, 1, 4 to 6, and 9 (IMR0, IMR1, IMR4 to IMR6, and IMR9) IMR0, IMR1, IMR4 to IMR6, and IMR9 are 8-bit readable/writable registers that mask the IRQ and on-chip peripheral module interrupts. When an interrupt source is masked, interrupt requests may be mistakenly detected, depending on the operation state of the IRQ pins and on-chip peripheral modules. To prevent this, set IMR0, IMR1, IMR4 to IMR6, and IMR9 while no interrupts are set to be generated, and then read the new settings from these registers. Table 8.3 shows the relationship between IMR and each interrupt source. Rev. 1.00, 02/04, page 208 of 804 Bit 7 6 5 4 3 2 1 0 Bit Name IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Interrupt Mask Table 8.3 lists the correspondence between the interrupt sources and interrupt mask registers. IMn 1 0 Read Write Interrupt source of the corresponding bit is masked Interrupt source of the corresponding bit is not masked No processing Legend: n = 7 to 0 Table 8.3 Correspondence between Interrupt Sources and IMR0 to IMR9/IMCR0 to IMCR9 Bit Name (Function Name) 7 6 5 4 IRQ4 3 IRQ3 2 IRQ2 1 IRQ1 (BT) 0 IRQ0 Register Name IMR0/IMCR0 IRQ7 (USBF standby recovery interrupt request) IMR1/IMCR1 IMR4/IMCR4 IMR5/IMCR5 IMR6/IMCR6 IMR9/IMCR9 Note: TUNI2 (TMU2) -- TUNI1 (TMU1) TUNI0 (TMU0) DEI3 DEI2 USBFI1 (USBF) DEI1 (DMAC) SCIFI1 (SCIF1) SIOFI (SIOF) USBFI0 DEI0 SCIFI0 (SCIF0) USBHI (USBH) ITI (WDT) : Reserved. These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 209 of 804 8.3.7 Interrupt Mask Clear Registers 0, 1, 4 to 6, and 9 (IMCR0, IMCR1, IMCR4 to IMCR6, and IMCR9) IMCR0, IMCR1, IMCR4 to IMCR6, and IMCR9 are 8-bit writable registers that clear the mask settings for the IRQ and on-chip peripheral module interrupts. Table 8.3 shows the relationship between IMCR and each interrupt source. Bit 7 6 5 4 3 2 1 0 Bit Name IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 Initial Value R/W W W W W W W W W 0 Description Interrupt Mask Clear Table 8.3 lists the correspondence between interrupt sources and interrupt mask clear registers. IMC n 1 Write Corresponding bit in interrupt mask register IMRn is cleared No processing Legend: n = 7 to 0 Rev. 1.00, 02/04, page 210 of 804 8.4 Interrupt Sources There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an interrupt, so the interrupt request is ignored. 8.4.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. When the BL bit in the status register (SR) is 0, NMI interrupts are accepted. NMI interrupts are edge-detected. In sleep or standby mode, the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is used to select either rising or falling edge detection. When using edge-input detection for NMI interrupts, a pulse width of at least two P cycles (peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt mask level bits (I3 to I0) in the status register (SR). It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt. 8.4.2 IRQ Interrupts IRQ interrupts are input by level or edge from pins IRQ7, IRQ4 to IRQ0. The priority level can be set by interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15. When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. When the ICR1 and ICR2 registers are rewritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to IRR0 after reading IRR0. Edge input interrupt detection requires input of a pulse width of more than two cycles on a peripheral clock (P) basis. When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler. The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt handling. Rev. 1.00, 02/04, page 211 of 804 8.4.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following modules*: * * * * * * * * DMA controller (DMAC) Serial I/O with FIFO (SIOF) Serial communication interfaces with FIFO (SCIF0 and SCIF1) USB host controller (USBH) USB function controller (USBF) Timer unit (TMU) Watchdog timer (WDT) User-debugging interface (H-UDI) Note: * An interrupt generated at the bluetooth interface (BT) is not handles as a on-chip peripheral module interrupt and is connected to the eternal interrupt pin (IRQ1) of this LSI. The USB function controller (USBF) standby recovery interrupt is not handled as a on-chip peripheral module interrupt and is connected to the external interrupt pin (IRQ7) of this LSI. Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt event register 2 (INTEVT2). It is easy to identify sources by using the value of the INTEVT2 register as a branch offset. A priority level (from 0 to 15) can be set for each module except H-UDI by writing to interrupt priority registers A to H (IPRA to IPRH). The priority level of the H-UDI interrupt is 15 (fixed). The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral module interrupt handling. 8.4.4 Interrupt Exception Handling and Priority There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. The priority of each interrupt source is set within priority levels 0 to 15; level 15 is the highest and level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. Table 8.4 lists the codes for the interrupt event register 2 (INTEVT2) and the order of interrupt priority. Each interrupt source is assigned a unique code by INTEVT2. The start address of the interrupt service routine is common for each interrupt source. This is why, for instance, the value of INTEVT2 is used as an offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. Rev. 1.00, 02/04, page 212 of 804 IRQ interrupt and on-chip peripheral module interrupt priorities can be set properly between 0 and 15 for each module by setting interrupt priority registers A to C and F to H (IPRA to IPRC and IPRF to IPRH). A reset assigns priority level 0 to IRQ and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 8.4. Table 8.4 Interrupt Exception Handling Sources and Priority Interrupt Priority Priority IPR within IPR Default Interrupt Code (Initial Value) (Bit Numbers) Setting Unit Priority H'1C0 H'5E0 IRQ0 IRQ1(BT) IRQ2 IRQ3 IRQ4 H'600 H'620 H'640 H'660 H'680 16 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRC (3 to 0) IPRC (7 to 4) IPRC (11 to 8) IPRC (15 to 12) IPRD (3 to 0) IPRD (15 to 12) High Interrupt Source NMI H-UDI IRQ IRQ7 (USBF H'6E0 standby recovery) DMAC DEI0 DEI1 DEI2 DEI3 USBH USBF USBHI USI0 USI1 SCIF0 SCIF1 SIOF TMU0 TMU1 TMU2 WDT SCIFI0 SCIFI1 SIOFI1 TUNI0 TUNI1 TUNI2 ITI H'800 H'820 H'840 H'860 H'A00 H'A20 H'A40 H'C00 H'C20 H'CA0 H'400 H'420 H'440 H'560 0 to 15 (0) IPRE (15 to 12) High Low 0 to 15 (0) 0 to 15 (0) IPRF (3 to 0) IPRF (7to 4) High Low 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRG (15 to 12) -- IPRG (11 to 8) IPRH (11 to 8) -- -- IPRA (15 to 12) -- IPRA (11 to 8) IPRA (8 to 4) -- -- Low IPRB (15 to 12) -- Rev. 1.00, 02/04, page 213 of 804 8.5 8.5.1 Operation Interrupt Sequence The sequence of interrupt operations is described below. Figure 8.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A to H (IPRA to IPRH). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected, according to table 8.4, Interrupt Exception Handling Sources and Priority. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in synchronization with the peripheral clock (P). The CPU receives an interrupt at a break in instructions. 5. The interrupt source code is set in the interrupt event register 2 (INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), register bank bit (RB), and mode bit (MD) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt handler may branch with the INTEVT2 register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by acceptance of an interrupt in this LSI. 2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. Rev. 1.00, 02/04, page 214 of 804 Program execution state No Interrupt generated? Yes No SR.BL=0 or sleep mode? Yes No Standby mode? Yes NMI? Yes NMI? Yes No No No IRQ? Yes Level 15 interrupt? Yes Yes I3 to I0 level 14or lower? No Save SR to SSR; save PC to SPC Set BL/RB bits in SR to1 Branch to exception handler Yes No Level 14 interrupt? Yes I3 to I0 level 13 or lower? No Yes No Set interrupt cause in INTEVT2 Level 1 interrupt? Yes I3 to I0 level 0? No No I3 to I0: Interrupt mask bits in status register (SR) Figure 8.2 Interrupt Operation Flowchart Rev. 1.00, 02/04, page 215 of 804 8.5.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT2. The code in INTEVT2 can be used as an offset for branching to the specific handler. 2. Clear the interrupt source in each specific handler. 3. Save SSR and SPC to memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When the sequence of interrupt operations is described above, if an interrupt of higher priority than the one being handled occurs directly after execution of the operation in step 4, it can be accepted. Rev. 1.00, 02/04, page 216 of 804 Section 9 Bus State Controller (BSC) 9.1 Overview The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 9.1.1 Features The BSC has the following features: 1. Physical address space is divided into eight areas A maximum 16 Mbytes for each of the three areas, CS0, CS3, and CS4, totally 48 Mbytes. Can specify the normal space interface, SRAM interface with byte selection, burst ROM interface, and SDRAM interface*1 Can select the data bus width (8 or 16 bits) for each address space*2. Controls the insertion of the wait state for each address space. Controls the insertion of the wait state for each read access and write access. Can set the independent idling cycle in the continuous access for five cases: read-write (in same space/different space), read-read (in same space/different space), the first cycle is a write access. 2. Normal space interface Supports the interface that can directly connect to the normal memories such as SRAM and ROM. 3. Burst ROM interface High-speed access to the ROM that has the page mode function (page flash ROM). 4. SDRAM interface Can set the SDRAM in CS3 area. Multiplex output for row address/column address. Efficient access by single read/single write. High-speed access by the bank-active mode. Supports an auto-refresh and self-refresh. Rev. 1.00, 02/04, page 217 of 804 5. Byte-selection SRAM interface Can connect directly to a byte-selection SRAM 6. Bus arbitration Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 7. Refresh function Supports the auto-refresh and self-refresh functions. Specifies the refresh interval using the refresh counter and clock selection Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8) Notes: 1. Some CSn arias do not support the some memory interfaces. For the sorts of memory interfaces that are supported by each area, see section 9.3, Area Overview. 2. The data bus width of the CS0 area is 16-bit fixed. Rev. 1.00, 02/04, page 218 of 804 BSC functional block diagram is shown in figure 9.1. BACK BREQ Bus right controller CMNCR Internal bus Internal master module Internal slave module WAIT Wait controller . . . CS0WCR . . . CS4WCR RWTCNT BOOT_E External memory area control circuit MD5 A23 to A0, D15 to D0 BS, RD/WR, RD, WE1, WE0 RAS, CAS, CKE, DQM1, DQM0 . . . CS4BCR . . . Memory controller SDCR RTCSR RTCNT REFOUT Refresh controller Comparator Interrupt controller RTCOR BSC Legend CMNCR CSnWCR RWTCNT CSnBCR SDCR RTCSR RTCNT RTCOR : Common control register : CSn space wait control register (n = 0, 3, 4) : Reset wait counter : CSn space bus control register (n = 0, 3, 4) : SDRAM control register : Refresh timer control/status register : Refresh timer counter : Refresh time constant register Figure 9.1 BSC Functional Block Diagram Rev. 1.00, 02/04, page 219 of 804 Module bus CS0, CS3, CS4 Area controller . . . CS0BCR 9.2 Input/Output Pins Table 9.1 shows the pin configuration of BSC. Table 9.1 Name A23 to A0 D15 to D0 BS Pin Configuration I/O O I/O O Function Address Bus Data Bus Bus Cycle Start Asserted when a normal space or burst ROM is accessed. Asserted by the same timing as CAS in SDRAM access. CS0, CS3, CS4 O RD/WR RD WE1/DQM1 O O O Chip Select Read/Write Connects to WE pins when SDRAM or byte-selection SRAM is connected. Read Pulse Signal (read data output enable signal) WE1: Controls that D15 to D8 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. DQM1: Controls that D15 to D8 are being selected. Connected to the DQM1 pin when SDRAM is connected. WE0/DQM0 O WE0: Controls that D7 to D0 are being written to. Connected to the byte select signal when a byte-selection SRAM is connected. DQM0: Controls that D7 to D0 are being selected. Connected to the DQM0 pin when SDRAM is connected. RAS CAS CKE WAIT BREQ BACK MD5 O O O I I O I Connects to the RAS pin when SDRAM is connected. Connects to the CAS pin when SDRAM is connected. Connected to the CKE pin when SDRAM is connected. External Wait Input Bus Request Input Bus enable output Endian Select 0: Big endian 1: Little endian REFOUT BOOT_E O I Refresh request output when a bus is released Boot Enable For details see section 17, BOOT Function (BOOT). Rev. 1.00, 02/04, page 220 of 804 9.3 9.3.1 Area Overview Area Division In the architecture of this LSI, the logical spaces have 32-bit address spaces. The cache access method is shown by the upper three bits. For details see section 5, Cache. The remaining 29 bits are mapped in 512-Mbyte physical address space that are used for division of the space into eight areas. The BSC performs control for this 29-bit physical space. Figure 9.2 shows the mapping from the logical address space to the physical address space. Area 1 is used for the internal I/O, and area 2 and area 5 to area 7 are reserved. The other three areas (area 0, area 3, and area 4) are used as external address spaces. As listed in table 9.2, this LSI can connect each type of memories to three area of an external address space among the physical address spaces divided into eight areas, respectively. And it outputs chip select signals (CS0, CS3, and CS4) for each of them. CS0 is asserted during area 0 access; CS4 is asserted during area 4 access. H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 Physical address space H'00000000 H'04000000 H'08000000 H'0C000000 H'10000000 H'14000000 Area 0 (CS0) Area 1 (Internal I/O) Area 2 (Reserved area) P0 Area 3 (CS3) Area 4 (CS4) Area 5 (Reserved area) Area 6 (Reserved area) Area 7 (Reserved area) H'1FFFFFFF Logical address space Figure 9.2 Logical Address Space and Physical Address Space Rev. 1.00, 02/04, page 221 of 804 9.3.2 Shadow Area Areas 0, 3, and 4 are decoded by physical addresses A28 to A26, which correspond to areas B'000, B'011, and B'100. Address bits A31 to A29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 x n (n = 1 to 6). Addresses A25 and A24 are ignored since addresses A23 to A0 are supported for the external pins of the address bus. Accordingly, for example, H'01000000 to H'03FFFFFF in the area 0 is shadow space. Area P4 (H'E0000000 to H'FFFFFFFF) is an internal I/O area and is assigned for internal register addresses. Area P4 does not become shadow space. Rev. 1.00, 02/04, page 222 of 804 9.3.3 Address Map The external address space has a capacity of 48 Mbytes and is used by dividing three partial spaces. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed in table 9.2. Table 9.2 Area Address Space Map of External Address Space Memory to be Connected 1 Physical Address H'00000000 to H'00FFFFFF H'01000000 to H'03FFFFFF Capacity 16 Mbytes Shadow Access Size 8, 16, 32* (n = 1 to 6) 2 Area 0 Normal memory* (CS0 area) Burst ROM H'00000000 + H'20000000 x n to Shadow H'03FFFFFF + H'20000000 x n Area 1 Internal I/O H'04000000 to H'07FFFFFF H'04000000 + H'20000000 x n to H'07FFFFFF + H'20000000 x n Area 2 Reserved area*4 H'08000000 + H'20000000 x n to H'0BFFFFFF + H'20000000 x n (n = 1 to 6) (n = 1 to 6) 8, 16, 32*3 Area 3 Normal memory*1 H'0C000000 to H'0CFFFFFF 16 Mbytes (CS3 area) Byte-selection H'0D000000 to H'0FFFFFFF Shadow SRAM H'0C000000 + H'20000000 x n to Shadow SDRAM H'0FFFFFFF + H'20000000 x n Normal memory* Area 4 (CS4 area) Burst ROM Byte-selection SRAM Area 5 Area 6 Area 7 Reserved area*4 Reserved area*4 Reserved area*4 1 (n = 1 to 6) 8, 16, 32*3 H'10000000 to H'10FFFFFF H'11000000 to H'13FFFFFF 16 Mbytes Shadow H'10000000 + H'20000000 x n to Shadow H'13FFFFFF + H'20000000 x n H'14000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n H'18000000 + H'0000000 x n to H'1BFFFFFF + H'20000000 x n H'1C000000 + H'20000000 x n to H'1FFFFFFF + H'20000000 x n (n = 1 to 6) (n = 1 to 6) (n = 0 to 6) (n = 0 to 7) Notes: 1. Normal memory can be connected to the external device which has an interface, such as the SRAM and ROM. 2. In the area 0 (selected when the chip select signal CS0 is asserted), the data bus width is 16-bit fixed. 3. The data bus width is set by the CSn space bus control register (CSnBCR). The data bus width should be 16 bits when SDRAM is connected in area 3. 4. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 223 of 804 9.3.4 Data Bus Width The data bus width of areas 3 and 4 is set 8 bits or 16 bits by the CSn space bus control register (CSnBCR, n = 3 or 4). The data bus width of area 0 is fixed 16 bits. For details, see section 9.4.2, CSn Space Bus Control Register. 9.4 Register Descriptions The BSC has the following registers. Refer to section 27, List of Registers, for the register addresses and the register states in each operating mode. Do not access spaces other than CS0 until the termination of the setting the memory interface. When accessing spaces other than CS0, set the CSn space bus control register (CSnBCR) which corresponds to the area to be accessed before setting the CSn space wait control register (CSnWCR). * Common control register (CMNCR) * CS0 space bus control register (CS0BCR) * CS3 space bus control register (CS3BCR) * CS4 space bus control register (CS4BCR) * CS0 space wait control register (CS0WCR) * CS3 space wait control register (CS3WCR) * CS4 space wait control register (CS4WCR) * SDRAM control register (SDCR) * Refresh timer control/status register (RTCSR) * Refresh timer counter (RTCNT) * Refresh time constant register (RTCOR) * Reset wait counter (RWTCNT) * SDRAM mode register for CS3 space (SDMR3)* Note: * Substance of this register is in the SDRAM, and can be written to by accessing the area of this register. For details, see Power-On Sequence in section 9.5.5, SDRAM Interface. Rev. 1.00, 02/04, page 224 of 804 9.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. CMNCR is initialized by a power-on reset, but not by a manual reset or in standby mode and holds the previous value. Do not access external memory other than area 0 until the CMNCR register initialization is complete. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 7 6 DMAIW1 DMAIW0 0 0 R/W Wait states between access cycles when DMA single R/W address transfer is performed Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycled inserted 5 DMAIWA 0 R/W Method of inserting wait states between access cycles when DMA single address transfer is performed Specifies the method of inserting the idle cycles specified by the DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. Setting this bit will make this LSI insert the idle cycles even when the continuous accesses to an external device with DACK are performed. 0: Idle cycle is inserted when other device drives the data bus after an external device with DACK drives the data bus. 1: Idle cycle is inserted every time when an external device with DACK is accessed. 4 1 R Reserved This bit is always read as 1. The write value should always be 1. When 0 is written to this bit, correct operation cannot be guaranteed. 31 to 8 Rev. 1.00, 02/04, page 225 of 804 Bit 3 Bit Name ENDIAN Initial Value 0/1* R/W R Description Endian Flag Samples the external pin for specifying endian on power-on reset (MD5) and specifies the pin value as the initial value. All address spaces are defined by this bit. This is a read-only bit. 0: The external pin for specifying endian (MD5) was low level on power-on reset. This LSI is being operated as big endian. 1: The external pin for specifying endian (MD5) was high level on power-on reset. This LSI is being operated as little endian. 2 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in standby mode for A23 to A0, BS, CSn, RD/WR, WEn/DQMn, and RD. 0: High impedance in standby mode. 1: Driven in standby mode 0 HIZCNT 0 R/W High-Z Control Specifies the state in standby mode and bus released for CKIO, CKE, RAS, and CAS. 0: High impedance in standby mode and bus released for CKIO, CKE, RAS, and CAS. 1: Driven in standby mode and bus released for CKIO, CKE, RAS, and CAS. Note: * The external pin for specifying endian (MD5) is sampled on power-on reset. When big endian is specified, this bit is read as 0 and when little endian is specified, this bit is read as 1. Rev. 1.00, 02/04, page 226 of 804 9.4.2 CSn Space Bus Control Register (CSnBCR) (n=0, 3, 4) CSnBCR is a 32-bit readable/writable register that specifies the memory to be connected to each area, the number of idle cycles between bus cycles, and the bus-width. CSnBCR is initialized by a power-on reset, but not by a manual reset or in standby mode and holds the previous value. Do not access external memory other than area 0 until CSnBCR register initialization is completed. Bit 31 30 Bit Name Initial Value All 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. IWW1 IWW0 1 1 R/W Idle Cycles between Write-read Cycles and Write-write 1 R/W Cycles* These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and writewrite cycle. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 27 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 26 25 IWRWD1 IWRWD0 1 1 R/W Idle Cycles for Another Space Read-Write*1 R/W Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous accesses switch between different spaces. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 29 28 Rev. 1.00, 02/04, page 227 of 804 Bit 24 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 23 22 IWRWS1 IWRWS0 1 1 R/W Idle Cycles for Read-Write in the Same Space*1 R/W Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous accesses are for the same space. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 21 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 20 19 IWRRD1 IWRRD0 1 1 R/W Idle Cycles for Read-Read in Another Space*1 R/W Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses switch between different spaces. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 18 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 228 of 804 Bit 17 16 Bit Name IWRRS1 IWRRS0 Initial Value 1 1 R/W Description R/W Idle Cycles for Read-Read in the Same Space R/W Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous accesses are for the same space. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 15 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 14 13 12 TYPE2 TYPE1 TYPE0 0 0 0 R/W Memory Type* 2 R/W Specify the type of memory connected to a space. R/W 000: Normal space 001: Burst ROM 010: Setting prohibited 011: Byte-selection SRAM 100: SDRAM 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited For details for memory type in each area, refer to table 9.2. 11 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 229 of 804 Bit 10 9 Bit Name BSZ1 BSZ0 Initial Value 1 0/1 R/W R/W R/W Description Data Bus Size*3 Specify the data bus sizes of spaces. The data bus sizes of areas 3 and 4 are shown below. 00: Setting prohibited 01: 8-bit size 10: 16-bit size 11: Setting prohibited Note: The initial values of CS0BCR and other CSnBCR are 10 and 11, respectively. The valid value should be set. The data bus width of the area 0 is fixed 16 bits. Other settings are ignored. 8 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Notes: 1. In actual operation, same idle cycles might be inserted by factors other than the specification of this bit. 2. If an unappropriated memory is specified to be connected to a space, correct operation cannot be guaranteed. 3. The initial data bus sizes of other than area 0 after a reset cannot be set. Therefore, the data bus sizes should be set 8 or 16 bits before the areas are accessed. Rev. 1.00, 02/04, page 230 of 804 9.4.3 CSn Space Wait Control Register (CSnWCR) (n=0, 3, 4) CSnWCR is a 32-bit register which specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type specified by the CSn space bus control register (CSnBCR). Specify CSnBCR register first, then specify the CSnWCR register. CSnWCR is initialized by a power-on reset, but not by a manual reset or in standby mode and holds the previous value. Normal Space, Byte-Selection SRAM: * CS0WCR Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Is 1 is written to these bits, correct operation cannot be guaranteed. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 31 to 13 Rev. 1.00, 02/04, page 231 of 804 Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value 1 0 1 0 R/W R/W R/W R/W R/W Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 1 0 HW1 HW0 0 0 R/W R/W Delay Cycles from RD, WEn negation to Address, CSn negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00, 02/04, page 232 of 804 * CS3WCR Bit 31 to 21 Bit Name Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/WR signal timing when the byteselection SRAM interface is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W Number of Access Wait Cycles R/W Specify the number of cycles that are necessary for R/W read/write access. R/W 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Rev. 1.00, 02/04, page 233 of 804 Bit 6 Bit Name WM Initial Value R/W Description 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. * CS4WCR Bit 31 to 21 Bit Name Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection Specifies the WEn and RD/WR signal timing when the byteselection SRAM interface is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 234 of 804 Bit 18 17 16 Bit Name WW2 WW1 WW0 Initial Value R/W Description 0 0 0 R/W Number of Write Access Wait Cycles R/W Specify the number of cycles that are necessary for write R/W access. 000: The same cycles as WR3 to WR0 setting (read access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 12 11 SW1 SW0 0 0 R/W Number of Delay Cycles from Address, CSn Assertion to RD, R/W WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00, 02/04, page 235 of 804 Bit 10 9 8 7 Bit Name WR3 WR2 WR1 WR0 Initial Value R/W Description 1 0 1 0 R/W Number of Access Wait Cycles R/W Specify the number of cycles that are necessary for read R/W access. R/W 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 1 0 HW1 HW0 0 0 R/W Delay Cycles from RD, WEn negation to Address, CSn R/W negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00, 02/04, page 236 of 804 Burst ROM: * CS0WCR Bit Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 17 16 BW1 BW0 0 0 R/W Number of Burst Wait Cycles R/W Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R/W Number of Access Wait Cycles R/W Specify the number of wait cycles to be inserted in the write R/W cycle and the first read cycle. R/W 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited 31 to 18 Rev. 1.00, 02/04, page 237 of 804 Bit 6 Bit Name WM Initial Value 0 R/W Description R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. * CS4WCR Bit Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 17 16 BW1 BW0 0 0 R/W Number of Burst Wait Cycles R/W Specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 12 11 SW1 SW0 0 0 R/W Number of Delay Cycles from Address, CSn Assertion to R/W RD, WE Assertion 31 to 18 Specify the number of delay cycles from address and CSn assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00, 02/04, page 238 of 804 Bit 10 9 8 7 Bit Name W3 W2 W1 W0 Initial Value 1 0 1 0 R/W Description R/W Number of Access Wait Cycles R/W Specify the number of wait cycles to be inserted in the write R/W cycle and the first read cycle. R/W 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 1 0 HW1 HW0 0 0 R/W Delay Cycles from RD, WEn negation to Address, CSn R/W negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00, 02/04, page 239 of 804 SDRAM: * CS3WCR Bit 31 to 15 Initial Bit Name Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 14 13 TRP1 TRP0 0 0 R/W Number of Cycles from Auto-precharge/PRE Command to R/W ACTV Command Specify the number of minimum cycles from the start of autoprecharge or issuing of PRE command to the issuing of ACTV command for the same bank. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 12 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 11 10 TRCD1 TRCD0 0 1 R/W Number of Cycles from ACTV Command to R/W READ(A)/WRIT(A) Command Specify the number of minimum cycles from issuing ACTV command to issuing READ(A)/WRIT(A) command. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 9 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 240 of 804 Bit 8 7 Initial Bit Name Value A3CL1 A3CL0 1 0 R/W Description R/W CAS Latency R/W Specify the CAS latency. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 4 3 TRWL1 TRWL0 0 0 R/W Number of Cycles from WRITA/WRIT Command to AutoR/W precharge/PRE Command Specifies the number of cycles from issuing WRITA/WRIT command to the start of auto-precharge or to issuing PRE command. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 2 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 1 0 TRC1 TRC0 0 0 R/W Number of Cycles from REF Command/Self-refresh Release R/W to ACTV Command Specify the number of cycles from issuing the REF command or releasing self-refresh to issuing the ACTV command.. 00: 3 cycles 01: 4 cycles 10: 6 cycles 11: 9 cycles Rev. 1.00, 02/04, page 241 of 804 9.4.4 SDRAM Control Register (SDCR) SDCR is a 32-bit register that specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. SDCR is initialized by a power-on reset, but not by a manual reset or in standby mode and holds the previous value. Bits other than RFSH and RMODE should be written to at the initialization settings and not be changed afterward. When writing to RFSH and RMODE, the values before writing should be written to the other bits. The area 3 should not be accessed until this register setting has been completed while the synchronous DRAM is used. Bit 31 to 13 Initial Bit Name Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 12 SLOW 0 R/W Low-Frequency Mode Specifies the output timing of command, address, and write data for SDRAM and the latch timing of read data from SDRAM. Setting this bit makes the hold time for command, address, write and read data. This mode is suitable for SDRAM with low-frequency clock. 0: Command, address, and write data for SDRAM is output at the rising edge of CKIO. Read data from SDRAM is latched at the rising edge of CKIO. 1: Command, address, and write data for SDRAM is output at the falling edge of CKIO. Read data from SDRAM is latched at the falling edge of CKIO. 11 RFSH 0 R/W Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh Rev. 1.00, 02/04, page 242 of 804 Bit 10 Initial Bit Name Value RMODE 0 R/W Description R/W Refresh Control Specifies whether to perform auto-refresh or self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed 9 PDOWN 0 R/W Power-Down Mode Specifies whether the SDRAM is entered in power-down mode or not after the memory access other than SDRAM is completed. If this bit is set to 1, the CKE pin is pulled to low to place the SDRAM to power-down mode triggered by memory access other than SDRAM after the SDRAM access ends. 0: Does not place the SDRAM in power-down mode. 1: Places the SDRAM in power-down mode. 8 BACTV 0 R/W Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: When bank active mode is specified, the data bus width should be set 16 bits. 7 to 5 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 4 3 A3ROW1 A3ROW0 0 0 R/W Number of Bits of Row Address R/W Specify the number of bits of the row address. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) Rev. 1.00, 02/04, page 243 of 804 Bit 2 Initial Bit Name Value 0 R/W Description R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 1 0 A3COL1 A3COL0 0 0 R/W Number of Bits of Column Address R/W Specify the number of bits of the column address. 00: 8 bits 01: 9 bits 10: 10 bits 11: Setting prohibited Rev. 1.00, 02/04, page 244 of 804 9.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR is a 32-bit readable/writable register that specifies various items about refresh for SDRAM. When the RTCSR is written, the upper 16 bits of the write data must be HA55A to cancel write protection. Bit 31 to 8 Initial Bit Name Value All 0 R/W Description R Write Protection These bits are always read as 0. When writing to these bits, the upper 16-bit of the write data should be HA55A to cancel write protection. The lower 8-bit is should always be 0. If other value is written to these bits, correct operation cannot be guaranteed. 7 CMF 0 R/W Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied. 6 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W Clock Select R/W Select the clock input to count-up the refresh timer counter R/W (RTCNT). 000: Stop the counting-up 001: B/4 010: B/16 011: B/64 100: B/256 101: B/1024 110: B/2048 111: B/4096 Rev. 1.00, 02/04, page 245 of 804 Bit 2 1 0 Initial Bit Name Value RRC2 RRC1 RRC0 0 0 0 R/W Description R/W Refresh Count R/W Specify the number of continuous refresh cycles, when the R/W refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: Once 001: Twice 010: 4 times 011: 6 times 100: 8 times 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 9.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter register that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit 31 to 8 Initial Bit Name Value All 0 R/W Description R/W Write Protection These bits are always read as 0. When writing to these bits, the upper 16-bit of the write data should be H'A55A to cancel write protection. The lower 8-bit is should always be 0. If other value is written to these bits, correct operation cannot be guaranteed. 7 to 0 All 0 R/W 8-bit Counter Rev. 1.00, 02/04, page 246 of 804 9.4.7 Refresh Time Constant Register (RTCOR) RTCOR is a 32-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit 31 to 8 Initial Bit Name Value All 0 R/W Description R Write Protection These bits are always read as 0. When writing to these bits, the upper 16-bit of the write data should be HA55A to cancel write protection. The lower 8-bit is should always be 0. If other value is written to these bits, correct operation cannot be guaranteed. 7 to 0 All 0 R/W Refresh Time Specify the upper limit value of the refresh timer counter (RTCNT). 9.4.8 Reset Wait Counter (RWTCNT) RWTCNT is a 7-bit counter. This counter starts to increment by synchronizing the CKIO after a power-on reset is released, and stops when the value reaches H'007F. External bus access is suspended while the counter is operating. This counter is provided to minimize the time from releasing a reset for flash memory to the first access. This register cannot be read or written to. Rev. 1.00, 02/04, page 247 of 804 9.5 9.5.1 Operating Description Endian/Access Size and Data Alignment This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low level on power-on reset, the endian will become big endian and when MD5 pin is high level on power-on reset, the endian will become little endian. Two data bus widths (8 bits and 16 bits) are available for normal memory and byte-selection SRAM. Note that the data bus width for the area 0 is fixed 16 bits. The data bus width of SDRAM is fixed 16 bits. Data alignment is performed in accordance with the data bus width of the device and endian. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Table 9.3 through 9.6 show the relationship between endian, device data width, and access unit. Table 9.3 16-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 1st time at 0 2nd time at 2 D15 to D8 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 31 to 24 Data 15 to 8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16 Data 7 to 0 Strobe Signals WE1/DQM1 Assert Assert Assert Assert Assert Assert WE0/DQM0 Assert Assert Assert Assert Assert Assert Rev. 1.00, 02/04, page 248 of 804 Table 9.4 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals WE1/DQM1 WE0/DQM0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 1st time at 0 2nd time at 1 1st time at 2 2nd time at 3 1st time at 0 2nd time at 1 3rd time at 2 4th time at 3 D15 to D8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Table 9.5 Operation 16-Bit External Device/Little Endian Access and Data Alignment Data Bus D15 to D8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 Data 31 to 24 Assert Assert Assert Assert Assert Assert Strobe Signals WE1/DQM1 WE0/DQM0 Assert Assert Assert Assert Assert Assert Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 1st time at 0 2nd time at 2 Rev. 1.00, 02/04, page 249 of 804 Table 9.6 Operation 8-Bit External Device/Little Endian Access and Data Alignment Data Bus D15 to D8 D7 to D0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24 Strobe Signals WE1/DQM1 WE0/DQM0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 Longword access at 0 1st time at 0 2nd time at 1 1st time at 2 2nd time at 3 1st time at 0 2nd time at 1 3rd time at 2 4th time at 3 Rev. 1.00, 02/04, page 250 of 804 9.5.2 Normal Space Interface Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byteselection pin, see section 9.5.7, Byte-Selection SRAM Interface. Figure 9.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 CKIO T2 A23 to A0 CSn RD/WR Read RD D15 to D0 RD/WR WEn Write D BS DACK * Note: * The waveform for DACK is when active low is specified. Figure 9.3 Normal Space Basic Access Timing (Access Wait 0) Rev. 1.00, 02/04, page 251 of 804 There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 16 bits are always read in case of a 16-bit device, and 8 bits in case of an 8-bit device. When writing, only the WEn signal for the byte to be written is asserted. Reading/writing for cache fill or copy back is performed continuously in total of 16 bytes according to the specified data bus width. During the processing, bus is not released. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary, the CPU performs longword accesses to perform a cache fill operation on the external interface. Writing to the write-through area and reading/writing to the area not to be cached are performed according to the actual access size. It is necessary to output the data that has been read using the RD signal when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 9.4 and 9.5 show the basic timings of normal space accesses. If the WM bit of the CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.4). If the WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 9.5). Figure 9.6 and figure 9.7 shows the examples of SRAM connection. Note that bits of external memory address and those of this LSI address are connected shifted when using the data in longword units (figure 9.6) and in word units (figure 9.7) since this LSI address is divided in byte units. Rev. 1.00, 02/04, page 252 of 804 T1 CKIO T2 Tnop T1 T2 A23 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACK * WAIT Note: * The waveform for DACK is when active low is specified. Figure 9.4 Continuous Access for Normal Space 1 Data Bus Width = 16 bits, Long-Word Access, CSnWCR.WN Bit = 0 (Access Wait = 0, Cycle Wait = 0) Rev. 1.00, 02/04, page 253 of 804 T1 CKIO T2 T1 T2 A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACK * WAIT Note: * The waveform for DACK is when active low is specified. Figure 9.5 Continuous Access for Normal Space 2 Data Bus Width = 16 bits, Long-Word Access, CSnWCR.WN Bit = 1 (Access Wait = 0, Cycle Wait = 0) Rev. 1.00, 02/04, page 254 of 804 This LSI **** **** **** 128k x 8 bits SRAM **** **** **** **** A17 A1 CSn RD D15 **** A16 A0 CS OE I/O7 D8 WE1 D7 **** **** **** I/O0 WE **** D0 WE0 A16 A0 CS OE I/O7 I/O0 WE Figure 9.6 Example of 16-Bit Data-Width SRAM Connection 128 k x 8 bits SRAM A16 A0 CS OE I/O7 I/O0 WE This LSI A16 ... **** A0 CSn RD D7 D0 WE0 Figure 9.7 Example of 8-Bit Data-Width SRAM Connection ... Rev. 1.00, 02/04, page 255 of 804 ... ... 9.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for area 4 to insert wait cycles independently in read access and in write access. The areas other than 4 have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 9.8. T1 Tw T2 CKIO A23 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACK* Note: * The waveform for DACK is when active low is specified. Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. Rev. 1.00, 02/04, page 256 of 804 Wait states inserted by WAIT signal T1 Tw Tw Twx T2 CKIO A23 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 WAIT BS DACKn* Note: * The waveform for DACK is when active low is specified. Figure 9.9 Wait State Timing for Normal Space Access (Wait State Insertion using WAIT Signal) Rev. 1.00, 02/04, page 257 of 804 9.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A23 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn* Note: * The waveform for DACK is when active low is specified. Figure 9.10 CSn Assert Period Expansion Rev. 1.00, 02/04, page 258 of 804 9.5.5 SDRAM Interface SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQM1, DQM0, CKEand CS3. All the signals other than CS3 are common to all areas, and signals other than CKE are valid when CS3 is asserted. The data bus width of the area that is connected to SDRAM should be set to16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals. These commands are shown below. * * * * * * * * * * * NOP Auto-refresh (REF) Self-refresh (SELF) All banks pre-charge (PALL) Specified bank pre-charge (PRE) Bank active (ACTV) Read (READ) Read with pre-charge (READA) Write (WRIT) Write with pre-charge (WRITA) Write mode register (MRS) The byte to be accessed is specified by DQM1 and DQM0. Reading or writing is performed for a byte whose corresponding DQMn is low. For details on the relationship between DQMn and the byte to be accessed, refer to section 9.5.1, Endian/Access Size and Data Alignment. Figures 9.11 shows as example of the connection of the SDRAM with this LSI. Address area of this LSI is allocated in byte units. Therefore, note that bit addresses of an external memory and those of this LSI differ when handling data in longword units or word units. Rev. 1.00, 02/04, page 259 of 804 This LSI A14 64-Mbit synchronous SDRAM (1M x 16 bits x 4 banks) A13 A0 CKE CLK CS ... A1 CKE CKIO CSn RAS CAS RD/WR D15 RAS CAS WE I/O15 I/O0 DQMU DQML ... D0 DQM1 DQM0 Figure 9.11 Example of 16-Bit Data-Width SDRAM Connection Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CS3BCR, AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 9.7 to 9.9 show the relationship between the settings of bits BSZ[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A23 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ[1:0] =B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. Rev. 1.00, 02/04, page 260 of 804 ... ... Table 9.7 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (1)-1 Setting CS3BCR.BSZ [1:0] B'10 (Data bus width: 16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 SDCR.A3ROW [1:0] B'00 (Row address bit count: 11 bits) Row Address Output Cycle A25 A24 A23 A22 A21* A20* A19 2 2 SDCR.A3COL [1:0] B'00 (Column address bit count: 8 bits) Column Address Output Cycle A17 A16 A15 A14 A21*2 A20* L/H* 2 1 Synchronous DRAM Pin Function Unused A12 (BA1) A11 (BA0) A10/AP Specifies bank Specifies address /precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Example of connected memory 16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00, 02/04, page 261 of 804 Table 9.7 Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (1)-2 Setting CS3BCR.BSZ [1:0] B'10 (Data bus width: 16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 SDCR.A3ROW [1:0] B'01 (Row address bit count: 12 bits) Row Address Output Cycle A25 A24 A23 A22* A21* A20 A19 2 2 SDCR.A3COL [1:0] B'00 (Column address bit count: 8 bits) Column Address Output Cycle A17 A16 A15 A22*2 A21* A12 L/H* 1 2 Synchronous DRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP Specifies bank Address Specifies address /precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Example of connected memory 64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00, 02/04, page 262 of 804 Table 9.8 Setting Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (2)-1 CS3BCR.BSZ [1:0] B'10 (Data bus width: 16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 SDCR.A3ROW [1:0] B'01 (Row address bit count: 12 bits) Row Address Output Cycle A26 A25 A24 A23* A22* A21 A20 2 2 SDCR.A3COL [1:0] B'01 (Column address bit count: 9 bits) Column Address Output Cycle A17 A16 A15 A23*2 A22* A12 L/H* 1 2 Synchronous DRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP Specifies bank Address Specifies address /precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Example of connected memory 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00, 02/04, page 263 of 804 Table 9.8 Setting Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (2)-2 CS3BCR.BSZ [1:0] B'10 (Data bus width: 16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 SDCR.A3ROW [1:0] B'01 (Row address bit count: 12 bits) Row Address Output Cycle A27 A26 A25 A24* A23* A22 A21 2 2 SDCR.A3COL [1:0] B'10 (Column address bit count: 10 bits) Column Address Output Cycle A17 A16 A15 A24*2 A23* A12 L/H* 1 2 Synchronous DRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP Specifies bank Address Specifies address /precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Example of connected memory 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00, 02/04, page 264 of 804 Table 9.9 Setting Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (3)-1 CS3BCR.BSZ [1:0] B'10 (Data bus width: 16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 SDCR.A3ROW [1:0] B'10 (Row address bit count: 13 bits) Row Address Output Cycle A26 A25 A24*2 A23* A22 A21 A20 2 SDCR.A3COL [1:0] B'01 (Column address bit count: 9 bits) Column Address Output Cycle A17 A16 A24*2 A23* A13 A12 L/H* 1 2 Synchronous DRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP Specifies bank Address Specifies address /precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Example of connected memory 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00, 02/04, page 265 of 804 Table 9.9 Setting Relationship between CS3BCR.BSZ[1:0], SDCR.A3ROW[1:0], SDCR.A3COL[1:0], and Address Multiplex Output (3)-2 CS3BCR.BSZ [1:0] B'10 (Data bus width: 16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 SDCR.A3ROW [1:0] B'10 (Row address bit count: 13 bits) Row Address Output Cycle A27 A26 A25*2 A24* A23 A22 A21 2 SDCR.A3COL [1:0] B'10 (Column address bit count: 10 bits) Column Address Output Cycle A17 A16 A25*2 A24* A13 A12 L/H* 1 2 Synchronous DRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP Specifies bank Address Specifies address /precharge Address A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Unused Example of connected memory 512-Mbit product (8 Mwords x 16 bits x 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00, 02/04, page 266 of 804 Burst Read: A burst read occurs in the following cases with this LSI. * Access size in reading is larger than data bus width. * 16-byte transfer in cache miss. * 16-byte transfer in DMAC (access to non-cacheable region) This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that is connected to a 16-bit data bus. Table 9.10 shows the relationship between the access size and the number of bursts. Table 9.10 Relationship between Access Size and Number of Bursts Data Bus Width 16 bits Access Size 8 bits 16 bits 32 bits 16 bits Number of Bursts 1 1 2 8 Figures 9.12 and 9.13 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READA command is issued in the Tc1 to Tc7 cycles, the READA command is issued in the Tc8 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td8 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1 and TRP0 bits of the CS3WCR register. In this LSI, wait cycles can be inserted by specifying each bit in the CS3WCR register to connect the SDRAM in variable frequencies. Figure 9.13 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READA command is output can be specified using the TRCD1 and TRCD0 bits of the CS3WCR register. If the TRCD1 and TRCD0 bits specify two cycles or more, a Trw cycle where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READA command is output to the Td1 cycle where the read data is latched can be specified using the A3CL1 and A3CL0 bits of the CS3WCR register. The number of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the synchronous DRAM. Rev. 1.00, 02/04, page 267 of 804 Tr ACTV CKIO A23 to A0 A11* CS3 RAS CAS RD/WR DQMn D15 to D0 Tc1 READ Td1 Tc2 READ Td2 Tc3 READ Td3 Tc4 READ Td5 Td4 Tc6 Tc5 READ READ Td6 Tc7 READ Td7 Tc8 READA Td8 Tde NOP Tap Note: * Address pin to be connected to the A10 pin of SDRAM. Figure 9.12 Burst Read Basic Timing (Auto Pre-charge) Td7 Td3 Td6 Td4 Td5 Td2 Tw Td1 Tc8 Tc5 Tc6 Tc7 Tc4 Tc3 Tr Trw Tc1 Tc2 ACTV NOP READ READ READ READ READ READ READ READA NOP CKIO A23 to A0 A11* CS3 RAS CAS RD/WR DQMn D15 to D0 Note: * Address pin to be connected to the A10 pin of SDRAM. Td8 Tde NOP Tap Figure 9.13 Burst Read Wait Specification Timing (Auto Pre-charge) Rev. 1.00, 02/04, page 268 of 804 Single Read: A read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous SDRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Figure 9.14 shows the single read basic timing. Tr CKIO A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tc1 Td1 Tde Tap Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.14 Single Read Wait Specification Timing (Auto Pre-charge) Rev. 1.00, 02/04, page 269 of 804 Burst Write: A burst write occurs in the following cases in this LSI. * Access size in writing is larger than data bus width. * Copyback of the cache * 16-byte transfer in DMAC (access to non-cacheable region) This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 8 times to write 16-byte continuous data to the SDRAM that is connected to a 16-bit data bus. The relationship between the access size and the number of bursts is shown in table 9.10. Figure 9.15 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1 to Tc7 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc8 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the auto-precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CSn space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits of the CS3WCR register. The number of Tap cycles is specified by the TRP1 and TRP0 bits of the CS3WCR register. Tr Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trwl Tap CKIO A23 to A0 A11* CS3 RAS CAS RD/WR DQMn D15 to D0 Note: * Address pin to be connected to the A10 pin of SDRAM. Figure 9.15 Basic Timing for Synchronous DRAM Burst Write (Auto Pre-charge) Rev. 1.00, 02/04, page 270 of 804 Single Write: A write access ends in one cycle when data is written in non-cacheable region and the data bus width is larger than or equal to access size. This is called single write. Figure 9.16 shows the single write basic timing. Tr CKIO A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tc1 Trwl Tap Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.16 Single Write Basic Timing (Auto-Precharge) Rev. 1.00, 02/04, page 271 of 804 Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. When the bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As synchronous DRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the TRP[1:0] bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 9.17, a burst read cycle for the same row address in figure 9.18, and a burst read cycle for different row addresses in figure 9.19. Similarly, a single write cycle without auto-precharge is shown in figure 9.260, a single write cycle for the same row address in figure 9.21, and a single write cycle for different row addresses in figure 9.22. In figure 9.18, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of latency for the DQMn signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMn signal is asserted after the Tc cycle. When bank active mode is set, if only accesses to the respective banks in area with the bank-active function set are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 9.17 or 9.20, followed by repetition of the cycle in figure 9.18 or 9.21. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 9.19 or 9.22 is executed instead of that in figure 9.18 or 9.21. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Rev. 1.00, 02/04, page 272 of 804 Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tc5 Td5 Tc6 Td6 Tc7 Td7 Tc8 Td8 Tde CKIO A23 to A0 A11* CS3 RAS CAS RD/WR DQMn D15 to D0 Note: * Address pin to be connected to the A10 pin of SDRAM. Figure 9.17 Burst Read Timing (No Auto Precharge) Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tc5 Td5 Tc6 Td6 Tc7 Td7 Tc8 Td8 Tde Tnop Tc1 CKIO A23 to A0 A11* CS3 RAS CAS RD/WR DQMn D15 to D0 Note: * Address pin to be connected to the A10 pin of SDRAM. Figure 9.18 Burst Read Timing (Bank Active, Same Row Address) Rev. 1.00, 02/04, page 273 of 804 Tp CKIO A23 to A0 A11* CS3 RAS CAS RD/WR DQMn D15 to D0 Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tc5 Td5 Tc6 Td6 Tc7 Td7 Tc8 Td8 Tde Note: * Address pin to be connected to the A10 pin of SDRAM. Figure 9.19 Burst Read Timing (Bank Active, Different Row Addresses) Rev. 1.00, 02/04, page 274 of 804 Tr ACTV CKIO A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tc1 WRIT Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.20 Single Write Timing (No Auto Precharge) Rev. 1.00, 02/04, page 275 of 804 Tnop NOP CKIO A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tc1 WRIT Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.21 Single Write Timing (Bank Active, Same Row Address) Rev. 1.00, 02/04, page 276 of 804 Tp PRE CKIO A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tpw NOP Tr ACTV Tc1 WRIT Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.22 Single Write Timing (Bank Active, Different Row Addresses) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Autorefreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. 1. Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0] in RTCSR, and the value set by in RTCOR. The each register should be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and RRC[2:0] in RTCSR settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 9.23 shows the auto-refresh cycle timing. Rev. 1.00, 02/04, page 277 of 804 After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state after waiting for the completion when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the TRP[1:0] bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the TRC[1:0] bits in CS3WCR after the Trr cycle. The TRC[1:0] bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is inserted between the Tp cycle and Trr cycle when the setting value of the TRP[1:0] bits in CS3WCR is longer than or equal to 2 cycles. Tp PALL CKIO A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Hi-z Tpw Trr REF Trc Trc Trc Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.23 Auto-Refresh Timing 2. Self-refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the TRP[1:0] bits in CS3WSR. The SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the TRC[1:0] bits in CS3WCR. Rev. 1.00, 02/04, page 278 of 804 Self-refresh timing is shown in figure 9.24. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. After self-refreshing has been cleared, CKE should be high for a specified time for the SDRAM. When the SDRAM is in power-down mode (PDOWN in SDCR is set to 1), transition to self-refresh mode should be made after clearing power-down mode. Tp PALL CKIO CKE A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Hi-z Tpw Trr SELF Trc Trc Trc Trc Trc Figure 9.24 Self-Refresh Timing Rev. 1.00, 02/04, page 279 of 804 Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. This LSI supports requests by the REFOUT pin for the bus mastership while waiting for the refresh request. The REFOUT pin is asserted low until the bus mastership is acquired. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is completed. Rev. 1.00, 02/04, page 280 of 804 Low-Frequency Mode: When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency. Figure 9.25 shows the access timing in low-frequency mode. In this mode, commands, addresses, and write data are output in synchronization with the falling edge of CKIO, which is half a cycle delayed than the normal timing. Read data is fetched at the falling edge of CKIO, which is half a cycle faster than the normal timing. This timing allows the hold time of commands, addresses, write data, and read data to be extended. If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of commands, addresses, write data, and read data are not guaranteed. Take the operating frequency and timing design into consideration when making the SLOW bit setting. Tr CKIO (High) CKE A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tc1 Td1 Tde Tap Tr Tc1 Tnop Trwl Tap Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.25 Low-Frequency Mode Access Timing Rev. 1.00, 02/04, page 281 of 804 Power-Down Mode: If the PDOWN bit of the SDCR register is set to 1, the SDRAM is placed in the power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle is inserted to assert the CKE signal in order to cancel the power-down mode. After the SDRAM access ends, it is possible to shift to the power down mode again by accessing the memory other than SDRAM (CKE becomes Low level). Figure 9.26 shows the access timing in power-down mode. Power-down CKIO CKE A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Tnop Tr Tc1 Td1 Tde Tap Power-down Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.26 Power-Down Mode Access Timing Rev. 1.00, 02/04, page 282 of 804 Power-On Sequence: In order to use the SDRAM, mode setting must first be performed after powering on. To perform SDRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the SDRAM mode register by accessing the SDMR3 register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CS3, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a write to address H'A4FD5000 + X for SDRAM. In this operation the data is ignored. To set burst read/single write (burst length 1) or burst read/burst write (burst length 1), CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a word-size access to the addresses shown in table 9.11. In this time 0 is output at the external address pins of A12 or later. Table 9.11 Access Address in SDRAM Mode Register Write * Setting for Area 3 (SDMR3) Burst read/single write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 Access Address H'A4FD5440 H'A4FD5460 External Address Pin H'0000440 H'0000460 Burst read/burst write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 Access Address H'A4FD5040 H'A4FD5060 External Address Pin H'0000040 H'0000060 Mode register setting timing is shown in figure 9.27. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued eight times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the TRP[1:0] bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the TRC[1:0]bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer the manual of the SDRAM to be used for the idle time to be needed. When the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Rev. 1.00, 02/04, page 283 of 804 Tp PALL CKIO Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop A23 to A0 A11*1 CS3 RAS CAS RD/WR DQMn D15 to D0 BS DACK*2 Hi-Z Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACK is when active low is specified. Figure 9.27 Synchronous DRAM Mode Write Timing (Based on JEDEC) Rev. 1.00, 02/04, page 284 of 804 9.5.6 Burst ROM Interface The burst ROM interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM interface, basically the same access as the normal space interface is performed, but the 2nd and subsequent accesses are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at the falling edge of the CKIO signal. For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits of the CSnWCR register is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the BW[1:0] bits of the CSnWCR register is inserted. In the access to the burst ROM, the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that do not perform the burst operation in the page flash ROM interface, access timing is same as a normal space interface. Table 9.12 lists a relationship between bus width, access size, and the number of bursts. Figure 9.28 shows a timing chart. Table 9.12 Relationship between Data Bus Width, Access Size, and Number of Bursts Data Bus Width 8 bits Access Size 8 bits 16 bits 32 bits 16 bytes 16 bits 8 bits 16 bits 32 bits 16 bytes Number of Bursts 1 2 4 16 1 1 2 8 Number of Accesses 1 1 1 1 1 1 1 1 Rev. 1.00, 02/04, page 285 of 804 T1 CKIO A23 to A0 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 CSn RD/WR RD D7 to D0 WAIT BS DACK* Note: * The waveform for DACK is when active low is specified. Figure 9.28 Burst ROM Access (Data Bus Width 8 Bits, 4-byte Transfer (number of burst 4), Access Wait for the 1st time 2, Access Wait for 2nd Time and after 1) Rev. 1.00, 02/04, page 286 of 804 9.5.7 Byte-Selection SRAM Interface Basic Access Timing: The byte-selection SRAM interface is a memory interface which outputs a byte-selection pin (WE) in a read/write bus cycle. This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit of the CSnWCR register is cleared to 0 (initial value), the write access timing of the byte-selection SRAM interface is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 9.29. In write access, data is written to the memory according to the timing of the byteselection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit of the CSnWCR register is set to 1, the WEn pin and RD/WR pin timings change. Figure 9.30 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW[1:0] bits of the CSnWCR register. Figure 9.31 shows an example of Connection with Byte-Selection SRAM. Rev. 1.00, 02/04, page 287 of 804 T1 T2 CKIO A23 to A0 CSn WEn RD/WR Read RD D15 to D0 RD/WR High Write RD D15 to D0 BS DACKn* Note: * The waveform for DACK is when active low is specified. Figure 9.29 Byte-Selection SRAM Basic Access Timing (BAS = 0) Rev. 1.00, 02/04, page 288 of 804 T1 CKIO T2 A23 to A0 CSn WEn RD/WR Read RD D15 to D0 RD/WR Write High RD D15 to D0 BS DACKn* Note: * The waveform for DACK is when active low is specified. Figure 9.30 Byte-Selection RAM Basic Access Timing (BAS = 1) 64Kx16bit SRAM A16 A1 CSn RD RD/WR D15 D0 WE1 WE0 A15 A0 CS OE WE I/O 15 I/O 0 UB LB This LSI Figure 9.31 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM Rev. 1.00, 02/04, page 289 of 804 Byte-Selection SRAM Interface Restrictions: The BAS bit should not be set to 1 for the byte-selection SRAM while the SDRAM in auto-refresh is used. If the BAS bit is set to 1, a refresh cannot be issued. Problems: When the byte-selection SRAM is accessed (BAS = 1) before a refresh is carried out, the ACTV command is issued instead of the RD/WR low output during the PALL command cycle. Therefore, the operation of SDRAM cannot be guaranteed in subsequent REF command. Avoidance measures: 1. 2. A pseudo SRAM which is mixed with SDRAM should support UB and LB control write. When the WE pin of MCP is necessary to be connected to the RD/WR pin of this LSI to use MCP incorporating a flash memory, make access according to the following procedure. Make SDRAM enter in self-refresh Set the functions of CSnBCR and CSnWCR in the flash memory area for using the byteselection SRAM (BAS = 1): accessing byte-selection SRAM and WE write control. Start write access to a flash memory When a write access to a flash memory ends, set the UB and LB control (BAS = 0) and then clear the self-refresh function. Instead of the PALL command, the ACTV command is issued at the first cycle of the refresh sequence. CKIO CS3 RAS CAS RD/WR Low is not output. Figure 9.32 Waveform in the Event of a Problem Rev. 1.00, 02/04, page 290 of 804 9.5.8 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting wait cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by bits IWW[1:0], IWRWD[1:0], IWRWS[1:0], IWRRD[1:0], and IWRRS[1:0] in the CSnBCR register , and bits DMAIW[1:0] and DMAIWA in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are shown below. Continuous accesses are write-read or write-write Continuous accesses are read-write for different spaces Continuous accesses are read-write for the same space Continuous accesses are read-read for different spaces Continuous accesses are read-read for the same space Data output from an external device caused by DMA single transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single transfer is followed by any type of access (DMAIWA = 1) 9.5.9 Bus Arbitration 1. 2. 3. 4. 5. 6. In bus arbitration, the LSI operates in two ways; 1. The LSI has the bus mastership in the normal state, and releases the bus mastership after receiving a bus request from another device. 2. The LSI does not have the bus mastership in the normal state; it requests the bus mastership each time that external access is necessary. In the case of the LSI with bus mastership in the normal state, this is called master mode. This LSI supports master mode. To prevent device malfunction while the bus mastership is transferred between master and slave, the LSI negates all of the bus control signals before bus release. When the bus mastership is received, all of the bus control signals are first negated and then driven appropriately. In this case, output buffer contention can be prevented because the master and slave drive the same signals with the same values. In addition, to prevent noise while the bus control signal is in the high impedance state, pull-up resistors must be connected to these control signals. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of Rev. 1.00, 02/04, page 291 of 804 bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The states that do not allow bus mastership release are shown below. 1. 2. 3. 4. 16-byte transfer because of a cache miss During copyback operation for the cache Between the read and write cycles of a TAS instruction Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 5. 16-byte transfer by the DMAC The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing the cycles required for master to slave bus mastership transitions streamlines the system design. Master Mode: In master mode, the LSI has the bus mastership until a bus request is received from another device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the slave has released the bus, it negates the BACK signal and resumes the bus usage. The SDRAM issues all bank pre-charge commands (PALLs) when active banks exist and releases the bus after completion of a PALL command. The bus sequence is as follows. 1. The address bus and data bus are placed in a high-impedance state synchronized with the rising edge of CKIO. 2. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of CKIO. 3. The bus control signals (BS, CSn, RAS, CAS, WEn/DQMn, RD, and RD/WR) are placed in the high-impedance state at subsequent rising edges of CKIO. These bus control signals go high one cycle before being placed in the high-impedance state. 4. Bus request signals are sampled at the falling edge of CKIO. The sequence for reclaiming the bus mastership from a slave is described below. Rev. 1.00, 02/04, page 292 of 804 1. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. 2. The bus enable signal is negated at the next falling edge of the clock. The address bus and data bus are started to be driven at the next rising edge of CKIO. 3. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven. Figure 9.33 shows the bus arbitration timing in master mode. In an original slave device designed by the user, multiple bus accesses are generated continuously to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh correctly, the slave device must be designed to release the bus mastership within the refresh interval time. To achieve this, the LSI instructs the REFOUT pin to request the bus mastership while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus mastership is received. If the slave releases the bus, the LSI acquires the bus mastership to execute the SDRAM refresh. The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing the cycles required for master to slave bus mastership transitions streamlines the system design. CKIO BREQ BACK A23 to A0 D15 to D0 CSn Other bus control signals Figure 9.33 Bus Arbitration Timing (Master Mode) Master and Slave Cooperation: Figure 9.34 shows an example of the master and slave devices. To control system resources correctly between master and slave devices, the roles of the master and slave devices must be defined appropriately. The SDRAM must be initialized before using the devices. To use the standby operation to reduce power consumption, the roles of the master and slave devices must also be defined appropriately. This LSI is designed to execute all controls such as initialization, refresh, and standby in a device in master mode. If a master device and a slave device are connected directly in a two-processor configuration, the master device performs all processing other than memory access. In this case, the slave device must not access devices such as an SDRAM that require initialization prior to device initialization. The following methods can be used to prevent this. Rev. 1.00, 02/04, page 293 of 804 1. An external circuit can be connected that releases the slave device reset by the master device. 2. The master can set a flag to the devices such as an SRAM that does not require initialization after initialization and the slave initiates access after checking to see that the flag has been set. 3. An external circuit can be connected to generate an interrupt from the master device to a slave device after initialization. The slave is released from the wait state by the interrupt. If self-refresh mode is specified for the SDRAM, the master device does not release the bus. If a transition is underway to standby mode, or if the master clock stops because of a frequency change, the master device cannot release the bus. To prevent the slave from issuing bus requests in a case such as this, the slave must be put into the sleep state. Master mode CKIO BREQ BACK CSn BS RD/WR RD WEn CKE RAS CAS DQMn WAIT A23 to A0 D15 to D0 Slave mode CKIO BREQ BACK CSn BS RD/WR RD WEn CKE RAS CAS DQMn WAIT A23 to A0 D15 to D0 CS BS RD/WR RD WEn WAIT An Dn CS OE WE An I/On Other devices SRAM Figure 9.34 Master and Slave Connection Example Rev. 1.00, 02/04, page 294 of 804 CLK CKE CS RAS CAS WE DQMxx An DQn SDRAM 9.5.10 Usage Notes Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, the current bus cycle being executed is completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache or if another LSI on-chip bus master module is executed when a manual reset occurs, the current access is cancelled in longword units because the access request is cancelled by the bus master at manual reset. If a manual reset is requested during cache fill operations, the contents of the cache cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. In addition, a bus arbitration request by the BREQ signal can be accepted during manual reset signal assertion. Some flash memories may specify a minimum time from reset release to the first access. To ensure this minimum time, the bus state controller supports a 7-bit counter (RWTCNT). At power-on reset, the RWTCNT is cleared to 0. After power-on reset, RWTCNT is counted up synchronously together with CKIO and an external access will not be generated until RWTCNT is counted up to H007F. At manual reset, RWTCNT is not cleared. Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal buses: a cache bus (L bus), internal bus (I bus), and peripheral bus. The CPU and cache memory are connected to the cache bus. Internal bus masters other than the CPU and bus state controller are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory and debugging modules such as a UBC and AUD are connected bidirectionally to the cache bus and internal bus. Access from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise to the following problems. On-chip bus masters such as DMAC other than the CPU can access internal memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation on the external interface. For a cache-through area, the CPU performs access according to the Rev. 1.00, 02/04, page 295 of 804 actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus. In a write cycle for the cache area, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be rewritten until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. On-Chip Peripheral Module Access: To access an on-chip module register, two or more peripheral module clock (P) cycles are required. Care must be taken in system design. Rev. 1.00, 02/04, page 296 of 804 Section 10 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 10.1 Features * Four channels (One channel can receive an external request) Channel 0 can receive an external request. * 4-GB physical address space * Data transfer unit is selectable: Byte, Word (two bytes), Longword (four bytes), and 16 Bytes (longword x 4) * Maximum transfer count: 16777216 transfers (24 bits) * Address mode: Dual address mode and single address mode are supported. * Transfer requests External request On-chip peripheral module request Auto request The following modules can issue an on-chip peripheral module request. SCIF0, SCIF1, SIOF, and USBF * Selectable bus modes Cycle steal mode (normal mode and intermittent mode) Burst mode * Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. * Interrupt request: An interrupt request can be generated to the CPU at the end of the specified counts of data transfer. * External request detection: There are following four types of DREQ input detection. Low level detection High level detection Rising edge level detection Falling edge level detection * Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. Figure 10.1 shows the block diagram of the DMAC. DMAS302A_000020030200 Rev. 1.00, 02/04, page 297 of 804 DMAC module Iteration control SAR_n On-chip memory On-chip peripheral module DAR_n Register control Peripheral bus Internal bus DMATCR_n Start-up control CHCR_n DMAOR Request priority control DMA transfer request signal DMA transfer acknowledge signal DMARS0~2 Interrupt controller DEIn IARn External ROM External RAM External device (memory mapped) External device (with acknowledgement) Bus interface Bus state controller DACK, TEND DREQ Legend DMA source address register SAR_n: DMA destination address register DAR_n: DMATCR_n: DMA transfer count register DMA channel control register CHCR_n: DMA operation register DMAOR: DMARS0, 1: DMA extension resource selector DMA transfer end interrupt request to the CPU DEIn: DMA initial address register IARn: 0, 1, 2, 3 n: Figure 10.1 Block Diagram of the DMAC Rev. 1.00, 02/04, page 298 of 804 10.2 Input/Output Pins Table 10.1 lists the pin configuration of DMAC. Table 10.1 Pin Configuration Channel 0 Pin Name DREQ DACK I/O Input Output Function DMA transfer request DMA transfer request input from external device to channel 0 DMA transfer request acknowledge Strobe output to an external I/O at DMA transfer request from external device to channel 0 TEND Output DMA transfer end DMA transfer end output for channel 0 Rev. 1.00, 02/04, page 299 of 804 10.3 Register Descriptions Register configuration of DMAC is described below. See section 27, List of Registers, for the addresses of these registers and the state of them in each processing status. In the following description of registers for each channel, for example, SAR for channel 0 is described as SAR_0. Channel 0: * * * * * DMA source address register_0 (SAR_0) DMA destination address register_0 (DAR_0) DMA transfer count register_0 (DMATCR_0) DMA channel control register_0 (CHCR_0) DMA initial address register_0 (IAR_0) Channel 1: * * * * * DMA source address register_1 (SAR_1) DMA destination address register_1 (DAR_1) DMA transfer count register_1 (DMATCR_1) DMA channel control register _1 (CHCR_1) DMA initial address register_1 (IAR_1) Channel 2: * * * * * DMA source address register_2 (SAR_2) DMA destination address register_2 (DAR_2) DMA transfer count register_2 (DMATCR_2) DMA channel control register_2 (CHCR_2) DMA initial address register_2 (IAR_2) Channel 3: * * * * * DMA source address register_3 (SAR_3) DMA destination address register_3 (DAR_3) DMA transfer count register_3 (DMATCR_3) DMA channel control register_3 (CHCR_3) DMA initial address register_3 (IAR_3) Rev. 1.00, 02/04, page 300 of 804 Common: * DMA operation register (DMAOR) * DMA extension resource selector 0 (DMARS0) * DMA extension resource selector 1 (DMARS1) 10.3.1 DMA Source Address Register (SAR) SAR is a 32-bit readable/writable register that specifies the source address of a DMA transfer. During a DMA transfer, this register indicates the next source address. When the data of an external device with DACK is transferred in the single address mode, the SAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. The SAR is undefined at reset and retains the current value in standby or module standby mode. 10.3.2 DMA Destination Address Register (DAR) DAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer. This register includes count functions, and during a DMA transfer, this register indicates the next destination address. When the data of an external device with DACK is transferred in the single address mode, the DAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. The DAR is undefined at reset and retains the current value in standby or module standby mode. 10.3.3 DMA Transfer Count Register (DMATCR) DMATCR is a 32-bit readable/writable register that specifies the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'00000001, 16777215 when H'00FFFFFF is set, and 16777216 (the maximum) when H'00000000 is set. During a DMA transfer, this register indicates the remaining transfer count. The upper eight bits of DMATCR will return 0 if read, and should only be written with 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The DMATCR is undefined at reset and retains the current value in standby or module standby mode. Rev. 1.00, 02/04, page 301 of 804 10.3.4 DMA Channel Control Register (CHCR) CHCR is 32-bit readable/writable register that controls the DMA transfer mode. The CHCR is initialized at reset and retains the current value in the standby or module standby mode. Bit 31 to 27 Bit Name Initial Value All 0 R/W R Descriptions Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 26 RPT 0 R Repeat Mode This bit specifies whether the DMA transfer is carried out in repeat mode or normal mode. 0: DMA transfer is carried out in normal mode 1: DMA transfer is carried out in repeat mode 25 RAS 0 R Repeat Space Set This bit sets repeat space as transfer source or transfer destination 0: Repeat area is transfer destination 1: Repeat area is transfer source 24 DA 0 R DMA Asynchronous This bit specifies whether the DREQ signal is synchronous signal or asynchronous signal This bit is valid only in CHCR_0. In CHCR_1 to CHCR_3, this bit is reserved. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 0: DREQ is an asynchronous signal 1: DREQ is a synchronous signal 23 DO 0 R/W DMA Overrun This bit selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_3. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 Rev. 1.00, 02/04, page 302 of 804 Bit 22 Bit Name TL Initial Value 0 R/W R/W Descriptions Transfer End Level This bit specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_3. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 0: Low-active output of TEND 1: High-active output of TEND 21 to 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 17 AM 0 R/W Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_3. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 0: DACK output in read cycle (Dual address mode) 1: DACK output in write cycle (Dual address mode) 16 AL 0 R/W Acknowledge Level AL specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_3. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 0: Low-active output of DACK 1: High-active output of DACK Rev. 1.00, 02/04, page 303 of 804 Bit 15 14 Bit Name DM1 DM0 Initial Value 0 0 R/W R/W R/W Descriptions Destination Address Mode DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address (setting prohibited in 16-byte transfer) 01: Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16byte transfer) 10: Destination address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) 11: Reserved (setting prohibited) 13 12 SM1 SM0 0 0 R/W R/W Source Address Mode SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (setting prohibited in 16-byte transfer) 01: Source address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Source address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) 11: Reserved (setting prohibited) Rev. 1.00, 02/04, page 304 of 804 Bit 11 10 9 8 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Descriptions Resource Select RS3 to RS0 specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state that DMA enable bit (DE) is set to 0. 0 0 0 0 0 0 0 0 1 0 1 0 External request, dual address mode Setting prohibited External request / Single address mode External address space external device with DACK 0 0 1 1 External request / Single address mode External device with DACK external address space 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Auto request Setting prohibited Setting prohibited Setting prohibited DMA expansion request module selection specification Setting prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Note: External request specification is valid only in CHCR_0; not valid in CHCR_1 to CHCR_3. 7 6 DL DS 0 0 R/W R/W DREQ Level (DL) and DREQ Edge Select (DS) These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0. These bits are reserved in CHCR_1 to CHCR_3. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. In channel 0, also, if the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by this bit is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge Rev. 1.00, 02/04, page 305 of 804 Bit 5 Bit Name TB Initial Value 0 R/W R/W Descriptions Transfer Bus Mode This bit specifies the bus mode when DMA transfers data. 0: Cycle steal mode (Initial Value) 1: Burst mode 4 3 TS1 TS0 0 0 R/W R/W Transfer Size TS1 and TS0 specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte size 01: Word size (two bytes) 10: Longword size (four bytes) 11: 16-byte unit (four longword transfers) 2 IE 0 R/W Interrupt Enable This bit specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Interrupt request is not generated 1: Interrupt request is generated 1 TE 0 R/W* Transfer End Flag This bit shows that DMA transfer ends. TE is set to 1 when data transfer ends when DMATCR becomes to 0. TE bit is not set to 1 in the following cases. * * DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes to 0. DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR). This bit can only be cleared by writing 0 after reading 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been suspended 1: Data transfer ends by the specified count (DMACTR = 0) Clearing condition: Writing 0 after TE = 1 read Rev. 1.00, 02/04, page 306 of 804 Bit 0 Bit Name DE Initial Value 0 R/W R/W Descriptions DMA Enable This bit enabler or disables the DMA transfer. In an auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF in DMAOR, and AE must be 0's. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0's an in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Writing 0 is possible to clear the flag. Rev. 1.00, 02/04, page 307 of 804 10.3.5 DMA Initial Address Register (IAR) IAR is a 32-bit readable/writable register that specifies the initial address of SAR or DAR for repeating the DMA transfer. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. IAR is undefined at reset and retains the current value in standby or module standby mode. 10.3.6 DMA Operation Register (DMAOR) DMAOR is a 32-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. DMAOR is undefined at reset and retains the current value in the standby or module standby mode. Bit 31 30 Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. CMS1 CMS0 0 0 R/W Cycle Steal Mode Select 1, 0 R/W These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermittent mode valid. 00: Normal mode 01: Reserved (setting prohibited) 10: Intermittent mode 16 Executes one DMA transfer in each of 16 clocks of an external bus clock. 11: Intermittent mode 64 Executes one DMA transfer in each of 64 clocks of an external bus clock. 27 26 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 29 28 Rev. 1.00, 02/04, page 308 of 804 Bit 25 24 Initial Bit Name Value R/W PR1 PR0 0 0 R/W R/W Description Priority Mode PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 10: The status of the channel select round-robin mode: RCn bit is reflected to the priority. 11: All channel round-robin mode 23 to 19 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 18 AE 0 R/(W)* Address Error Flag AE indicates that an address error occurred during DMA transfer. When the AE bit is set, the DMA transfer is not enabled even if the DE bit of CHCR and the DME bit of DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error Clear conditions: Writing AE = 0 after AE = 1 read 1: DMAC address error 17 NMIF 0 R/(W)* NMI Flag NMIF indicates that an NMI interrupt occurred. When the NMIF bit is set, the DMA transfer is not enabled even if the DE bit of CHCR and the DME bit of DMAOR are set to 1. Only 0 can be written to clear this bit after 1 is read. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. When the DMAC is not in operational, the NMIF bit is set to 1 even if the NMI interrupt was input. 0: No NMI input Clearing conditions: Writing NMIF = 0 after NMIF = 1 read 1: NMI interrupt occurs Rev. 1.00, 02/04, page 309 of 804 Bit 16 Initial Bit Name Value R/W DME 0 R/W Description DMA Master Enable DME enables or disables DMA transfers on all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is enabled in the corresponding channel. If this bit is cleared during transfer, transfers in all the channels can be suspended. 0: Disable DMA transfers on all channels 1: Enable DMA transfers on all channels 15 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Note: * Writing 0 is possible to clear the flag. 10.3.7 DMA Extension Resource Selector 0 and 1 (DMARS0 and DMARS1) DMARS is a 16-bits readable/writable register that specifies the DMA transfer sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for channels 2 and 3. The DMARS0 and DMARS1 are initialized at reset and retain the current values in standby or module standby mode. Transfer requests from the various modules are specified by the MID and RID as shown in table 10.2. When MID/RID other than the values listed in table 10.2 is set, the operation of this LSI is not guaranteed. The transfer request from the DMARS register is valid only when the resource select bits (RS3 [3:0]) has been set to B'1000 for CHCR0 to CHCR3 registers. Otherwise, even if the DMARS has been set, transfer request source is not accepted. Rev. 1.00, 02/04, page 310 of 804 * DMARS0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Bit Name Value C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 C1RID1 C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request registers ID1 and ID0 for DMA channel 0 (RID) See table 10.2. Transfer request registers ID1 and ID0 for DMA channel 1 (RID) See table 10.2. Transfer request modules ID5 to ID0 for DMA channel 0 (MID) See table 10.2 Description Transfer request modules ID5 to ID0 for DMA channel 1 (MID) See table 10.2. Rev. 1.00, 02/04, page 311 of 804 * DMARS1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Bit Name Value C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer request modules ID1 and ID0 for DMA channel 2 (RID) See table 10.2. Transfer request registers ID1 and ID0 for DMA channel 3 (RID) See table 10.2. Transfer request modules ID5 to ID0 for DMA channel 2 (MID) See table 10.2. Description Transfer request modules ID5 to ID0 for DMA channel 3 (MID) See table 10.2. Table 10.2 DMARS Settings Peripheral Module SCIF0 Setting Value for One Channel (MID + RID) H'21 H'22 SCIF1 H'29 H'2A SIOF H'55 H'56 USBF H'73 H'70 B'011100 B'010101 B'001010 MID B'001000 RID B'01 B'10 B'01 B'10 B'01 B'10 B'11 B'00 Function Transmit Receive Transmit Receive Transmit Receive Transmit and receive 0 Transmit and receive 1 Rev. 1.00, 02/04, page 312 of 804 10.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip module request. The dual address mode has direct address transfer mode and indirect address transfer mode. In the bus mode, the burst mode or the cycle steal mode can be selected. 10.4.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), and DMA extension resource source selector (DMARS) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. If the RPT bit is set to 1, the IAR value is set in SAR or DAR and DMATCR is initialized to the written value. In this case, transfer can be continued only by clearing the TE bit. 4. When an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Rev. 1.00, 02/04, page 313 of 804 Figure 10.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR - 1 DMATCR, SAR and DAR updated No DMATCR = 0? Yes TE = 1 DEI interrupt request (when IE = 1) Yes DMATCR Initialization IQR SAR/DAR NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Repeat mode? No NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Transfer end No No Normal end Transfer aborted Notes: 1 . In auto-request mode, transfer begins when the bits are set as follows: When NMIF and AE are cleared to 0, and TE is cleared to 0, and DE and DME are set to 1 2. DREQ = level detection in burst mode (external request) or cycle-steal mode. 3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 10.2 DMA Transfer Flowchart Rev. 1.00, 02/04, page 314 of 804 10.4.2 Repeat Mode Transfer The repeat mode of DMAC can be used by setting 1 to the RPT bit of the CHCR_n register. When the repeat mode is set and data transfer ends (DMATCR_n becomes 0), the DEI interrupt is generated if the IE bit of CHCR_n is set, and then the value of IAR_n is copied onto SAR_n or DAR_n specified by RAS bit of CHCR_n, and DMATCR_n is restored to an initial value. DMA transfer can be executed continuously when the TE bit of the CHCR_n register is cleared to 0. 10.4.3 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip module request. The request mode is selected in the RS3 to RS0 bits of the DMA channel control registers 0 to 3 (CHCR_0 to CHCR_3), and the DMA extension resource selectors 0 and 1 (DMARS0 and DMARS1). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and the NMIF bit of DMAOR are all 0. External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an external device. This is valid only for DMA channel 0. Choose one of the modes shown in table 10.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Table 10.3 Selecting External Request Modes with the RS Bits RS3 0 0 RS2 0 0 RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Source Any External memory, memory-mapped external device External device with DACK Destination Any External device with DACK External memory, memory-mapped external device 1 Rev. 1.00, 02/04, page 315 of 804 Choose to detect DREQ by either the edge or level of the signal input with the DREQ level (DL) bit and DS bit of CHCR_0 as shown in table 10.4. The source of the transfer request does not have to be the data transfer source or destination. Table 10.4 Selecting External Request Detection with DL, DS Bits CHCR DL 0 DS 0 1 1 0 1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun0: Transfer is aborted after the same number of transfer has been performed as requests. Overrun1: Transfer is aborted after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. (Table 10.5) Table 10.5 Selecting External Request Detection with DO Bit CHCR DO 0 1 External Request Overrun 0 Overrun 1 On-Chip Peripheral Module Request: In this mode (table 10.6), the transfer is performed in response to the transfer request signal (interrupt request signal) of an on-chip peripheral module. Transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the SCIF0, SCIF1, SIOF, and USBF. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request signal. Rev. 1.00, 02/04, page 316 of 804 When a transmit data empty transfer request of SCIF is set as the transfer request, the transfer destination must be the SCIF's transmit data register. Likewise, when the SCIF receive data full transfer request is set as the transfer request, the transfer source must be the SCIF's receive data register. These conditions also apply to the SIOF and USBF. Table 10.6 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits CHCR RS[3:0] 1000 DMARS MID 001000 RID 01 10 001010 01 10 010101 01 10 011100 11 DMA Transfer DMA Transfer Request Source Request Signal SCIF0 transmitter SCIF0 receiver SCIF1 transmitter SCIF1 receiver SIOF transmitter SIOF receiver USBF transmitter 0 USBF receiver 0 00 USBF transmitter 1 USBF receiver 1 Bus Mode Cycle steal Cycle steal Cycle steal Cycle steal Source Destination SCFTDR_0 Any SCFTDR_1 Any TDFE(transmit data FIFO Any empty interrupt) RDF (receive data FIFO full interrupt) SCFRDR_0 TDFE (transmit data FIFO Any empty interrupt) RDF (receive data FIFO full interrupt) SCFRDR_1 TDFE (transmit data FIFO Any empty interrupt) RDF (receive data FIFO full interrupt) Transmit data empty request 0 Receive data full request 0 Transmit data empty request 1 Receive data full request 1 SIOF/SITDR_0 Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal Cycle steal SIOF/SIRDR_0 Any Any EPDR2o, 6 Any EPDR2o, 6 EPDR2i, 5 Any EPDR2i, 5 Any Rev. 1.00, 02/04, page 317 of 804 10.4.4 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The four modes (fixed mode 1, fixed mode 2, channel selective round-robin mode, and all-channel round-robin mode) are selected using the bits PR1 and PR0 in DMAOR. Fixed Mode: In these modes, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 Fixed mode 2: CH0 > CH2 > CH3 > CH1 These are selected by the bits PR1 and the PR0 in DMAOR. Round-Robin Mode: Each time one word, byte, longword, or 16-byte is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 10.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after reset. When round-robin mode is selected, cycle steal mode and burst mode should not be mixed as the bus mode of two or more channels. Rev. 1.00, 02/04, page 318 of 804 (1) When channel 0 transfers (highest priority channel transfer) Initial priority order CH0 > CH1 > CH2 > CH3 CH1 > CH2 > CH3 > CH0 Channel 0 becomes bottom priority Priority order after transfer (2) When channel 1 transfers (second highest priority channel transfer) Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted. Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer CH2 > CH3 > CH0 > CH1 (3) When channel 2 transfers (third highest priority channel transfer) CH0 > CH1 > CH2 > CH3 Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately after there is a request to transfer channel 0 only, channel 0 becomes bottom priority and the priority of channel 3, which washigher than channel 0, are also shifted. Initial priority order Priority order after transfer CH3> CH0 > CH1 > CH2 Post-transfer priority order CH1 > CH2 > CH3 > CH0 (4) When channel 3 transfers (lowest highest priority channel transfer) Initial priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 Priority order does not change Figure 10.3 Round-Robin Mode Figure 10.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. Rev. 1.00, 02/04, page 319 of 804 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels 0 and 3 (3) Channel 1 3 (2) Channel 0 transfer start Priority order changes 0>1>2>3 1,3 (4) Channel 0 transfer ends (5) Channel 1 transfer starts 1>2>3>0 3 (6) Channel 1 transfer ends Priority order changes 2>3>0>1 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3 Figure 10.4 Changes in Channel Priority in Round-Robin Mode Rev. 1.00, 02/04, page 320 of 804 10.4.5 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer, they depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 10.7. Table 10.7 Supported DMA Transfers Destination External Device with DACK MemoryMapped External Device On-Chip Peripheral Module Source External Memory X/Y Memory U Memory External device with DACK Not available External memory Memory-mapped external device On-chip peripheral module X/Y memory, U memory Dual, single Dual, single Not available Not available Dual, single Dual, single Not available Not available Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is not available for on-chip peripheral modules. Address Modes: 1. Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selected) by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 10.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Rev. 1.00, 02/04, page 321 of 804 DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 10.5 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit of the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Figure 10.6 shows an example of DMA transfer timing in dual address mode. Rev. 1.00, 02/04, page 322 of 804 CKIO A23 to A0 Transfer source address Transfer destination address CSn D15 to D0 RD WEn DACKn (Active-Low) Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 10.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary memory, Destination: Ordinary memory) 2. Single Address Mode In single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 10.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. Rev. 1.00, 02/04, page 323 of 804 External address bus This LSI DMAC External data bus External memory External device with DACK DACK DREQ Data flow Figure 10.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Figures 10.8 shows an example of DMA transfer timing in single address mode. CKIO A23 to A0 CSn WE D15 to D0 DACK Address output to external memory space Select signal to external memory space Write strobe signal to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK external memory space (ordinary memory) CKIO A23 to A0 CSn RD D15 to D0 DACK Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (ordinary memory) external device with DACK Figure 10.8 Example of DMA Transfer Timing in Single Address Mode Rev. 1.00, 02/04, page 324 of 804 Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of the channel control register (CHCR). 1. Cycle-Steal Mode * Normal mode In the normal mode of cycle-steal, the bus mastership is given to another bus master after a one-transfer-unit (byte, word, long-word, or 16 bytes unit) DMA transfer. When another transfer request occurs, the bus masterships are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. Figure 10.9 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: 1. Dual address mode 2. DREQ low level detection DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC CPU Read Write Figure 10.9 DMA Transfer Example in the Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) * Intermittent Mode 16 and Intermittent Mode 64 In the intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is complete. If the next transfer request occurs after that, DMAC gets the bus mastership from other bus master after waiting for 16 or 64 clocks in B count. DMAC then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal. When DMAC gets again the bus mastership, DMA transfer can be postponed in case of entry updating due to cache miss. This intermittent mode can be used for all transfer section; transfer requester, source, and destination. The bus modes, however, must be cycle steal mode in all channels. Figure 10.10 shows an example of DMA transfer timing in cycle steal intermittent mode. Transfer conditions shown in the figure are: Rev. 1.00, 02/04, page 325 of 804 1. Dual address mode 2. DREQ low level detection DREQ More than 16 or 64B (change by the CPU's condition of using bus) Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU CPU DMAC DMAC Read Write CPU Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual address, DREQ low level detection) 2. Burst Mode Once the bus mastership is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. The burst mode cannot be used for other than CMT00, CMT01, CMT02, and CMT03 when the on-chip peripheral module is the transfer request source. Figure 10.11 shows DMA transfer timing in the burst mode. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC Read Write Read Write CPU Figure 10.11 DMA Transfer Example in the Burst Mode (Dual Address, DREQ low level detection) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 10.9 shows the relationship between request modes and bus modes by DMA transfer category. Rev. 1.00, 02/04, page 326 of 804 Table 10.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category Addres s Mode Transfer Category Dual External device with DACK and external memory External device with DACK and memorymapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module On-chip peripheral module and on-chip peripheral module Request Bus Transfer Mode Mode Size (bits) External External External /auto External /auto External /auto All*1 All*1 All*1 B/C B/C B/C B/C B/C C C C B/C B/C C B/C B/C B/C 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 Usable Channels 0 0 0 to 5*3 0 to 5*3 0 to 5*3 8/16/32/128*2 0 to 5*3 8/16/32/128*2 0 to 5*3 8/16/32/128*2 0 to 5*3 8/16/32/128 8/16/32/128 0 to 5* 3 X/Y memory, U memory and X/Y memory, External U memory /auto X/Y memory, U memory and memorymapped external device X/Y memory, U memory and on-chip peripheral module X/Y memory, U memory and external memory Single External device with DACK and external memory External device with DACK and memorymapped external device External /auto All*1 External /auto External External 0 to 5*3 8/16/32/128*2 0 to 5*3 8/16/32/128 8/16/32/128 8/16/32/128 0 to 5* 0 0 3 B: Burst, C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, transfer source register should be the transfer source or transfer. 2. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 3. If the transfer request is an external request, only channel 0 is available. Rev. 1.00, 02/04, page 327 of 804 Bus Mode and Channel Priority Order: When a given channel 1 is transferring in burst mode and there is a transfer request to a channel 0 with a higher priority in fixed mode (CH0 > CH1), the transfer of channel 0 will begin immediately. At this time, the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in burst mode. When channel 0 is operating in cycle steal mode, 1 will begin operating again without releasing bus mastership after channel 0 with a higher priority completes the transfer of one transfer unit. Then transfer is carried out between the two channels in the order channel 0, channel 1, channel 0, channel 1. In other words, the CPU cycle after transfer in cycle steal mode is switched with transfer in burst mode (hereafter, this is called preferential execution of burst mode). This example is shown in figure 10.12. When more than two channels in burst mode are conflicted, transfer on a channel with highest priority among those channels is executed. When transfers of more than two channels are performed, the bus is not given to the bus master until conflicted transfers in burst mode have been completed. CPU DMA CH1 DMA CH1 DMA CH0 CH0 DMA CH1 CH1 DMA CH0 CH0 DMA CH1 DMA CH1 CPU CPU DMAC CH1 Burst mode DMAC CH0 and CH1 Cycle steal mode DMAC CH1 Burst mode CPU Priority: CH0 > CH1 CH0: Cycle-steal mode CH1: Burst mode Figure 10.12 Bus State when Multiple Channels Are Operating The priority order in round-robin mode is changed as is shown in figure 10.3. Note that in the burst mode, channel for cycle steal and channel for burst mode should not be mixed. 10.4.6 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9, Bus State Controller (BSC). DREQ Pin Sampling Timing: Figures 10.13 to 10.16 show the DREQ input sampling timings in each bus mode. Rev. 1.00, 02/04, page 328 of 804 CKIO Bus cycle DREQ (Rising) DACK (Active-high) Acceptance start CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC 2nd acceptance CPU Acceptance start Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection CKIO Bus cycle DREQ Burst acceptance DACK CPU CPU DMAC DMAC Non sensitive period Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection Rev. 1.00, 02/04, page 329 of 804 CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) Acceptance start CPU 1st acceptance Non sensitive period CPU DMAC 2nd acceptance CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Acceptance start Acceptance start CPU 1st acceptance Non sensitive period CPU DMAC 2nd acceptance DMAC 3rd acceptance Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection Figure 10.17 shows the TEND output timing. CKIO End of DMA transfer Bus cycle DREQ DACK TEND DMAC CPU DMAC CPU CPU Figure 10.17 Example of DMA Transfer End Signal Timing in Cycle Steel Mode Level Detection To execute a long word access to an 8-bit or 16-bit external device or to execute a word access to an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in figure 10.18. Rev. 1.00, 02/04, page 330 of 804 T1 CKIO Address CS RD Data WEn DACK (Active low) TEND (Active low) WAIT T2 Taw T1 T2 Note: TEND is asserted for the last transfer unit of DMA transfers. If a transfer unit is divided into multiple bus cycles and if CS is negated during the bus cycle, TEND is also divided. Figure 10.18 BSC Ordinary Memory Access (No wait, Idle Cycle 1, Longword Access to 16bit Device) Rev. 1.00, 02/04, page 331 of 804 10.5 Usage Notes Rewriting Channel Control Register (CHCR_n): When rewriting a channel control register (CHCR_n) of each DMAC channel, the DE bit of corresponding channel should be cleared to 0 precedently. Shift to Power-Down Mode: Note that shifting to standby mode or module standby state by setting the module standby bit in DMAC should not be performed during DMA transfer. When shifting to software standby mode or module standby state, the DE bit of all channels should be cleared to 0 precedently. Rev. 1.00, 02/04, page 332 of 804 Section 11 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (I), a peripheral clock (P), and a bus clock (B). The CPG consists of an oscillator, PLL circuit, and divider circuit. 11.1 Features * Three clock modes Selection of three clock modes by frequency range, turning on and off the PLL, a direct connection to a crystal unit, and external clock input. * Three clocks generated independently An internal clock for the CPU and cache (I); a peripheral clock (P) for the on-chip circuits; a bus clock (B = CKIO) for the external bus interface. * Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control The clock can be stopped for sleep mode and software standby mode and specific modules can be stopped using the module standby function. Rev. 1.00, 02/04, page 333 of 804 A block diagram of the CPG is shown in figure 11.1. Clock pulse generator Divider 1 x1 x 1/2 x 1/3 x 1/4 x 1/6 x 1/8 x 1/12 PLL circuit 1 ( x 1, 2, 3, 4) Internal clock (I) CKIO Crystal oscillator XTAL EXTAL PLL circuit 2 ( x 2) Bus clock (B = CKIO) Peripheral clock (P) CPG control unit MD2 MD1 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 STBCR3 STBCR4 MCCR Bus interface Internal bus FRQCR STBCR STBCR2 STBCR3 STBCR4 MCCR : Frequency control register : Standby control register : Standby control register 2 : Standby control register 3 : Standby control register 4 : Memory clock control register Figure 11.1 Block Diagram of Clock Pulse Generator Rev. 1.00, 02/04, page 334 of 804 The clock pulse generator blocks function as follows: PLL Circuit 1: PLL circuit 1 multiplies the input clock frequency by 1, 2, 3 or 4 from the CKIO pin. The multiplication rate is set using the frequency control register (FRQCR). When this is done, the phases of the leading edge of the internal clock, bus clock, and peripheral clock are controlled so that those will agree with the phase of the leading edge of the CKIO pin. PLL Circuit 2: PLL circuit 2 doubles the input clock frequency from the crystal oscillator or EXTAL pin. The multiplication rate is fixed according to the clock operating mode. The clock operating mode is specified by the MD1 and MD2 pins. For details on clock operating mode, see table 11.2. Crystal Oscillator: The crystal oscillator is an oscillator circuit in which a crystal resonator is connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating mode 6. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal, bus, or peripheral clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register (FRQCR). * Note: * Internal and peripheral clocks can be selected independently using the frequency control register (FRQCR). However, even though it is the selectable combination, if the number of operation frequencies which surpasses upper limit value of each operating frequency is set, operation of this LSI can not be guaranteed. Since operation frequency of bus clock should be the same as that of the CKIO, the division ratio is automatically set using the multiplication rate of PLL circuit 1. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using the MD1 and MD2 pins and the frequency control register (FRQCR). Standby Control Circuit: The standby control circuit controls the states of the clock pulse generator and other modules during clock switching or sleep, or standby modes. Frequency Control Register: The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Standby Control Register: The standby control registers (STBCR, STBCR2 to STBCR4) have bits for controlling the power-down modes. See section 13, Power-Down Modes, for more information. Memory Clock Control Register: The memory clock control register (MCCR) has the memory clock in sleep and the control bits of 32-k clock oscillator for BT. For more information on MCCR, see section 13, Power-Down Mode. Rev. 1.00, 02/04, page 335 of 804 11.2 Input/Output Pins Table 11.1 lists the CPG pins and their functions. Table 11.1 Clock Pulse Generator Pins Configuration Pin Name MD1 MD2 XTAL EXTAL CKIO I/O Input Input Output Input Input/ Output Function Mode control pin Set the clock operating mode Mode control pin Set the clock operating mode Crystal output pin Connected to the crystal resonator Crystal input pin (clock input pin) Connected to the crystal resonator or used to input an external clock Clock input/output pin Used as the external clock input or output pin Rev. 1.00, 02/04, page 336 of 804 11.3 Clock Operating Modes Table 11.2 shows the relationship between the mode control pins (MD2 and MD1) combinations and the clock operating modes. Table 11.3 shows the usable frequency ranges in the clock operating. Table 11.2 Clock Operating Modes Pin Values Mode 5 6 7 MD2 1 0 1 MD1 0 0 1 Clock I/O Source EXTAL Crystal resonator CKIO Output CKIO CKIO PLL2 On/Off ON (x2) ON (x2) OFF PLL1 On/Off ON (x1, 2, 3, 4) ON (x1, 2, 3, 4) ON (x1, 2, 3, 4) CKIO Frequency (EXTAL) x2 (Crystal resonator) x2 (CKIO) Mode 5: This LSI is supplied with a clock that is doubled by the PLL circuit 2 after receiving an external clock from the EXTAL pin. This reduces the frequency of the externally generated clock. Input clock frequency and CKIO frequency range from 10 MHz to 30 MHz and from 20 MHz to 60 MHz, respectively. Mode 6: This LSI is supplied with a clock that is doubled by the PLL circuit 2 after operating the on-chip crystal oscillator. This reduces the frequency of the externally generated clock. Input clock frequency and CKIO frequency range from 10 MHz to 30 MHz and from 20 MHz to 60 MHz, respectively. Mode 7: In this mode, the CKIO pin functions as an input. This LSI is supplied with a clock that is wave-formed and multiplied by PLL circuit 1 and multiplied after receiving an external clock. This mode is effective for connecting synchronous DRAM because the PLL circuit 1. Input clock frequency (CKIO frequency) range from 20 MHz to 60 MHz. Rev. 1.00, 02/04, page 337 of 804 Table 11.3 Possible Combination of Clock Modes and FRQCR Values FRQCR Register PLL PLL Clock Ratio Circuit 1 Circuit 2 (I:B:P) Mode Value 5, 6 H'1000 H'1001* H'1002 2 Input Clock Frequency Range 10MHz to 15MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 15MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 30MHz 10MHz to 15MHz 10MHz to 30MHz 10MHz to 15MHz 10MHz to 20MHz 10MHz to 20MHz 10MHz to 15MHz 10MHz to 15MHz 10MHz to 15MHz 10MHz to 15MHz 20MHz to 30MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 30MHz 20MHz to 60MHz 20MHz to 60MHz CKIO Pin Frequency Range 20MHz to 30MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 30MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 30MHz 20MHz to 60MHz 20MHz to 30MHz 20MHz to 40MHz 20MHz to 40MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 60MHz 20MHz to 30MHz 20MHz to 60MHz 20MHz to 60MHz ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 2:2:2 2:2:1 2:2:2/3 2:2:1/2 2:2:1/3 2:2:1/4 2:2:1/6 4:2:2 4:2:1 4:2:2/3 4:2:1/2 4:2:1/3 2:2:2 2:2:1 6:2:2 6:2:1 6:2:1/2 8:2:2 8:2:1 8:2:2/3 4:2:2 1:1:1 1:1:1/2 1:1:1/3 1:1:1/4 1:1:1/6 1:1:1/8 1:1:1/12 2:1:1 2:1:1/2 2:1:1/3 H'1003*1 ON (x1) H'1004 H'1005 H'1006 H'1101 H'1103 H'1104 H'1105 H'1106 H'1111 H'1113 H'1202 H'1204 H'1206 H'1303 H'1305 H'1306 H'1313 7 H'1000 H'1001* H'1002 H'1003* H'1004 H'1005 H'1006 H'1101 H'1103 H'1104 1 2 ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) Rev. 1.00, 02/04, page 338 of 804 FRQCR Register PLL PLL Clock Ratio Circuit 1 Circuit 2 (I:B:P) Mode Value 7 H'1105 H'1106 H'1111 H'1202 H'1204 H'1206 H'1303 H'1305 H'1306 H'1313 H'1333 ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 2:1:1/4 2:1:1/6 1:1:1 3:1:1 3:1:1/2 3:1:1/4 4:1:1 4:1:1/2 4:1:1/3 2:1:1 1:1:1 Input Clock Frequency Range 20MHz to 60MHz 20MHz to 60MHz 20MHz to 30MHz 26.7MHz to 30MHz 26.7MHz to 40MHz 26.7MHz to 40MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz CKIO Pin Frequency Range 20MHz to 60MHz 20MHz to 60MHz 20MHz to 30MHz 26.7MHz to 30MHz 26.7MHz to 40MHz 26.7MHz to 40MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz 20MHz to 30MHz Notes: 1. Initial value immediately after reset in each mode. 2. The value is settable when the boot function is used. The boot function should not be used with values other than these values. There is a limitation in the SCIF transfer rate which can be set according to the input clock frequency. Refer to section 17.5.2, Clock Frequency and Data Transfer Rate when Using Boot Function in section 17, Boot Function (BOOT) for detail. Cautions: 1. Input of divider circuit 1 becomes PLL circuit 1 output 2. Input of PLL circuit 1 becomes: CKIO pin input in mode 7 PLL circuit2 output in modes 5 and 6 3. The frequency of the internal clock becomes: The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 Set the internal clock frequency not more 120 MHz (T.B.D). Do not set the internal clock frequency lower than the frequency of the CKIO pin. 4. The frequency of the peripheral clock becomes: The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1. Set the peripheral clock frequency lower than or equal to 30 MHz. Note that the frequency should not be higher than the CKIO pin frequency. 5. x1, x2, x3, or x4 can be used as the multiplication ratio of PLL circuit 1. x1, x1/2, x1/3, x1/4, x1/6, x1/8 and x1/12 can be selected as the division ratios of divider 1. Set the rate using frequency control register (FRQCR). 6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. Use the output frequency not more than 120 MHz (T.B.D). 7. Bus clock frequency is always set to be equal to the frequency of the CKIO pin. 8. Clock ratios in table 11.3 are ratios of each frequency to one input clock frequency. Rev. 1.00, 02/04, page 339 of 804 9. Operation of this LSI cannot be guaranteed using combinations other than those in table 11.3. 11.4 Register Descriptions The CPG has the following registers. Refer the section 27, List of Registers, for the addresses of the registers and the register states in each operating mode. * Frequency control register (FRQCR) * Memory clock control register (MCCR)* * Standby control register (STBCR, STBCR2 to STBCR4)* Note: * For further information on MCCR, STBCR, and STBCR2 to STBCR4, see section 13 Power-Down Mode 11.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin at standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. This register is initialized by power-on reset from the RESETP pin and retains the previous value after manual reset and standby mode. Rev. 1.00, 02/04, page 340 of 804 Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 15 to 13 12 CKOEN 1 R/W Clock Output Enable When the HIZCNT bit in CMNCR is set to 1, CKOEN specifies whether a clock is output from the CKIO pin, or whether the CKIO pin is placed in the level-fixed state during release of the standby mode. If CKOEN is cleared to 0 and HIZCNT in CMNCR is set to 1, the CKIO pin is fixed at low. Therefore, the malfunction of an external circuit because of an unstable CKIO clock during release of the standby mode can be prevented. In clock operating mode 7, the CKIO pin functions as an input regardless of this bit value. 0: CKIO pin goes low during release of the standby mode. 1: Clock is output from CKIO pin 11 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 10 9 8 STC2 STC1 STC0 0 0 0 R/W R/W R/W Frequency Multiplication Ratio 000: x 1 time 001: x 2 times 010: x 3 times 011: x 4 times 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 7 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 341 of 804 Bit 6 5 4 Bit Name IFC2 IFC1 IFC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Internal Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. 000: x 1 time 001: x 1/2 time 010: Setting prohibited 011: x 1/4 time 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 3 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 2 1 0 PFC2 PFC1 PFC0 0 1 1 R/W R/W R/W Peripheral Clock Frequency Division Ratio These bits specify the division ratio of the peripheral clock frequency with respect to the output frequency of PLL circuit 1. 000: x 1 time 001: x 1/2 time 010: x 1/3 time 011: x 1/4 time 100: x 1/6 time 101: x 1/8 time 110: x 1/12 time 110: Setting prohibited 111: Setting prohibited Note: The operations in the prohibited setting are not guaranteed. Rev. 1.00, 02/04, page 342 of 804 11.5 Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are controlled by software through the frequency control register. The methods are described below. 11.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR register TME bit = 0: WDT stops WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and PFC[2:0] bits. 4. The processor pauses internally and the WDT starts incrementing. The internal, bus, and peripheral clocks stop and the WDT is supplied with the clock. The clock will continue to be output at the CKIO pin. 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. Note: When changing the clock frequency multiplication ratio, clear both UMCLKC bit and XYMCLKC bit of memory clock control register (MCCR) to 0. 11.5.2 Changing the Division Ratio The WDT will not count unless the multiplication rate is changed simultaneously. 1. In the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011 2. Set the IFC[2:0] and PFC[2:0] bits to the new division ratio. The values that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio. Rev. 1.00, 02/04, page 343 of 804 11.6 Notes on Board Design Note on Using a Crystal Resonator: When designing the board, place the crystal resonator, capacitors CL1 and CL2, and damping register R as close as possible to the XTAL and EXTAL pins. To prevent inductive interference in oscillation, ensure that the connection points of the capacitor to be connected to the crystal resonator are common and no other signal lines cross the signal lines for these pins. Signal lines prohibited CL1 CL2 R EXTAL XTAL Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. This LSI Figure 11.2 Note on Using a Crystal Resonator Notes on Bypass Capacitor: A multilayer ceramic capacitor must be inserted for each pair of Vss and Vcc as a bypass capacitor. The bypass capacitor must be inserted as close as possible to the power supply pins of the LSI. Note that an appropriate bypass capacitor must be selected according to the capacitance and frequency of the LSI to be used. Rev. 1.00, 02/04, page 344 of 804 Notes on Using a PLL Oscillator Circuit: Circuitry as shown in figure 11.3 is recommended around the PLL. In the Vcc and Vss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. In clock operating mode 7, the EXTAL pin is pulled up and the XTAL pin is left open. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the power supply pins. To prevent such malfunction, the analog power supply pin Vcc and digital power supply pin Vcc should not supply the same resources on the board if at all possible. Please read "Vcc for PLL" above-mentioned as "VDD for PLL" when you do not select a built-in regulator (i.e. VDD external power supply is used). Power supply Vcc(PLL) Vcc Vss(PLL) Vss Figure 11.3 Note on Using a PLL Oscillator Circuit Rev. 1.00, 02/04, page 345 of 804 Rev. 1.00, 02/04, page 346 of 804 Section 12 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), which enables reset on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The watchdog timer (WDT) is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time and is used to clear standby mode and temporary standbys, such as frequency changes. It can also be used as an interval timer. 12.1 Features The WDT has the following features: * Can be used to ensure the clock settling time: Use the WDT to cancel a standby mode and the temporary standbys which occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. * Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. * Choice of eight counter input clocks Eight clocks (x1 to x1/4096) that are obtained by dividing the peripheral clock can be selected. * Power-on reset or manual reset can be selected as a reset Figure 12.1 shows a block diagram of the WDT. WDTS301A_000020030200 Rev. 1.00, 02/04, page 347 of 804 WDT Standby cancellation Standby mode Peripheral clock Internal reset request Reset control Clock selection Clock selector Interrupt request Interrupt control WTCSR Overflow Clock Divider Standby control WTCNT Bus interface Legend WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 12.1 Block Diagram of the WDT Rev. 1.00, 02/04, page 348 of 804 12.2 Register Descriptions The WDT has the following two registers. Refer to the section 27, List of Registers, for the details of the addresses of these registers and the state of registers in each operating mode. * Watchdog timer counter (WTCNT) * Watchdog timer control/status register (WTCSR) 12.2.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval timer mode. The WTCNT counter is initialized to H'00 only by a power-on reset caused by the RESETP pin. Use a word access to write to the WTCNT counter, writing H5A in the upper byte. Use a byte access to read the WTCNT. Note: The WTCNT differs from other registers in the prevention of erroneous writes. See section 12.2.3, Notes on Register Access, for details. 12.2.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, overflow flags and enable bits. The WTCSR register holds its value in an internal reset due to WDT overflow. The WTCSR register is initialized only by a power-on reset via the RESETP pin. When used to count the clock settling time for canceling a standby, it retains its value after counter overflow. Use a word access to write to the WTCSR counter, writing H'A5 in the upper byte. Use a byte access to read the WTCSR. Note: The WTCNT differs from other registers in the prevention of erroneous writes. See section 12.2.3, Notes on Register Access, for details. Rev. 1.00, 02/04, page 349 of 804 Bit 7 Initial Bit Name Value TME 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. 5 RSTS 0 R/W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode Rev. 1.00, 02/04, page 350 of 804 Bit 2 1 0 Initial Bit Name Value CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W R/W Description Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P) is 15 MHz. Bits 2 to 0 Clock Ratio 000 001 010 011 100 101 110 111 1 1/4 1/16 1/32 1/64 1/256 1/1024 1/4096 Overflow Cycle (17 us) (68 us) (273 us) (546 us) (1.09 ms) (4.36 ms) (17.48 ms) (69.91 ms) Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. 12.2.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedures for reading writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 12.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write Address: H'A415FF84 15 H'5A 8 7 Write data 0 WTCSR write Address: H'A415FF86 15 H'A5 8 7 Write data 0 Figure 12.2 Writing to WTCNT and WTCSR Rev. 1.00, 02/04, page 351 of 804 12.3 12.3.1 Operation Canceling Software Standby The WDT can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (The WDT does not operate when resets are used for canceling, so keep the RESETP pin low until the clock stabilizes.) 1. Before transitioning to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. This setting does not depend on a value of the WT/IT bit. 3. Move to standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the edge change of the NMI signal. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF and IOVF flags in WTCSR are not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the LSI again enters the standby mode when the WDT has counted up to H'80. This standby mode can be canceled by power-on resets. 12.3.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. This setting does not depend on a value of the WT/IT bit. 3. When the frequency control register (FRQCR) is written, the processor stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF and IOVF flags in WTCSR are not set when this happens. 5. The counter stops at the values H'00. Rev. 1.00, 02/04, page 352 of 804 6. Before changing the WTCNT after the execution of the frequency change instruction, always confirm that the value of the WTCNT is H'00 by reading the WTCNT. 12.3.3 Using Watchdog Timer Mode 1. Clear the TME bit of WTCSR to 0. If the TME bit is set to 1, the reset or the interval timer interrupt might be generated by error operation at the counter overflow. 2. Set the WT/IT bit in the WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2-CKS0 bits, and set the initial value of the counter in the WTCNT. 3. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 4. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 5. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting. 12.3.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the TME bit of WTCSR to 0. If the TME bit is set to 1, the reset or the interval timer interrupt might be generated by error operation at the counter overflow. 2. Clear the WT/IT bit in the WTCSR to 0, set the type of count clock in the CKS2-CKS0 bits, and set the initial value of the counter in the WTCNT. 3. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 4. When the counter overflows, the WDT sets the IOVF in WTCSR to 1 and an interval timer interrupt request is sent to INTC. The counter then resumes counting. 5. To clear the interval timer interrupt request in the exception handling routine, clear the flag which is set in the IOVF bit in WTCSR. For operation of interrupt exception handling, see section 4, Exception Handling and section 8, Interrupt Controller. Rev. 1.00, 02/04, page 353 of 804 Rev. 1.00, 02/04, page 354 of 804 Section 13 Power-Down Modes This LSI has three types of the power-down modes: sleep mode, software standby mode, and module standby function. In power-down mode, the CPU and some on-chip peripheral modules are halted. The power-down mode is cancelled by reset or interrupt sources. The power dissipation is decreased in addition by stopping a built-in regulator if internal circuit power VDD( = 1.5 V) is supplied from the external power supply. 13.1 1. 2. 3. 4. Features Sleep mode Software standby mode Module standby function VDD ( = 1.5 V) can be supplied from the outside with turning off a built-in regulator. Power-Down Modes 13.1.1 This LSI supports the following power-down modes and function: 1. Sleep mode 2. Software standby mode 3. Module standby function (cache, X/Y memory, U memory, DMAC, UBC, H-UDI and on-chip peripheral module)* Note: * Also the USBH and USBF have the module standby function. However, the USBH and USBF modules have control functions for their own since their clock sources are different from those for other modules. For details, refer to section 18, USB Pin Multiplex Controller (USBPM). Table 13.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. On/off of a built-in regulator does not influence the operation of each mode. Rev. 1.00, 02/04, page 355 of 804 Table 13.1 States of Power-Down Modes State Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR CPU On-Chip Reg- On-Chip Peripheral External CPG CPU ister Memory Modules Pins Memory Runs Halts Held Halts (Contents held) Halts Halts Held Halt (Contents held) Halt Run Canceling Procedure Mode Sleep mode Held Refreshed 1. Interrupt automati- 2. Reset cally * Selfrefreshed 1. NMI, IRQ 2. Reset by RESETP Software Execute SLEEP Standby instruction with STBY bit set to 1 mode in STBCR Module standby function Set MSTP bit to 1 Runs Runs Held in STBCR Specified Specified Held Refreshed 1. Clear module module automatiMSTP bit halts halts cally to 0 (Contents held) 2. Poweron reset Notes: * For details, refer to Appendix, A. Pin States. This state can be cleared by an emulator using the H-UDI command in ASE mode. For details, refer to the manual on emulator. Rev. 1.00, 02/04, page 356 of 804 13.1.2 Reset A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed is terminated and any events not executed are canceled to execute reset processing immediately. In manual reset, processing required to maintain external memory contents is continued. The following shows the conditions in which power-on reset or manual reset occurs. * Power-on reset A. A low level signal is input to the RESETP pin. B. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1 and cleared to 0, respectively. C. An H-UDI reset occurs. (For details on H-UDI reset, refer to section 26, User Debugging Interface (H-UDI).) * Manual reset The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the WTCSR are set to 1. Rev. 1.00, 02/04, page 357 of 804 13.1.3 Input/Output Pins Table 13.2 shows the pins for the on/off control of a built-in regulator. Table 13.2 Pin Configuration Pin Name RESETP Input/Output Input Description Power-on Reset Inputting low level signal to this pin cause a transition to power-on reset processing. TEST_REG Input Built-in regulator selection pin. The built-in power supply regulator is used when this pin is high, external power input is used when this pin is low for the internal power (VDD = 1.5 V). The level of this pin should not be changed during operation Built-in regulator control. This pin should be fixed to high when the external power supply is used for the internal power (VDD = 1.5 V). This pin should be open when the builtin power supply regulator is used. Built-in regulator control. This pin should be fixed to high when the external power supply is used for the internal power (VDD = 1.5 V). This pin should be open when the builtin power supply regulator is used. Built-in regulator control. This pin should be fixed to high when the external power supply is used for the internal power (VDD = 1.5 V). This pin should be open when the builtin power supply regulator is used. REG_PD_MAIN Input/NC REG_PD_BGR Input/NC REG_PD_VREF Input/NC Rev. 1.00, 02/04, page 358 of 804 13.2 Register Descriptions The registers listed below are used in power-down mode. Refer to section 27, List of Registers for the register addresses and register states in each operating mode. * * * * * Standby control register (STBCR) Standby control register 2 (STBCR2) Standby control register 3 (STBCR3) Standby control register 4 (STBCR4) Memory clock control register (MCCR) Rev. 1.00, 02/04, page 359 of 804 13.2.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized at power-on reset but retains the previous value after manual reset. Bit 7 Bit Name STBY Initial Value R/W 0 R/W Description Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode 1: Executing SLEEP instruction puts chip into software standby mode 6, 5 All 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 4 STBXTL 0 R/W Standby Crystal Specifies whether the crystal oscillator stops or continues in standby mode. 0: Stops crystal oscillator in standby mode. 1: Continues crystal oscillator in standby mode. 3 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 2 MSTP2 0 R/W Module Stop 2 Halts the clock supply to the timer unit TMU when the MSTP2 bit has been set to 1. 0: TMU runs 1: Clock supply to TMU halted 1, 0 All 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 360 of 804 13.2.2 Standby Control Register 2 (STBCR2) STBCR2 is a readable/writable 8-bit register that controls the operation of modules in the powerdown mode. The STBCR2 register is initialized at power-on reset but retains the previous value after manual reset. Bit 7 Bit Name MSTP10 Initial Value R/W 0 R/W Description Module Stop 10 When the MSTP10 bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI runs 1: Clock supply to H-UDI halted 6 MSTP9 0 R/W Module Stop 9 When the MSTP9 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs 1: Clock supply to UBC halted 5 MSTP8 0 R/W Module Stop 8 When the MSTP8 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs 1: Clock supply to DMAC halted 4 MSTP7 0 R/W Module Stop 7 When the MSTP7 bit is set to 1, the supply of the clock to the DSP is halted. 0: DSP runs 1: Clock supply to DSP halted 3 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 2 MSTP5 0 R/W Module Stop 5 When the MSTP5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: The cache memory runs 1: Clock supply to the cache memory halted Rev. 1.00, 02/04, page 361 of 804 Bit 1 Bit Name MSTP4 Initial Value R/W 0 R/W Description Module Stop 4 When the MSTP4 bit is set to 1, the supply of the clock to the U memory is halted. 0: The U memory runs 1: Clock supply to the U memory halted 0 MSTP3 0 R/W Module Stop 3 When the MSTP3 bit is set to 1, the supply of the clock to the X/Y memory is halted. 0: The X/Y memory runs 1: Clock supply to the X/Y memory halted 13.2.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in the powerdown mode. STBCR3 is initialized at power-on reset but retains the previous value after manual reset. Bit 7 Bit Name MSTP37 Initial Value R/W 0 R/W Description Module Stop 37 When the MSTP37 bit is set to 1, the supply of the clock to the SIOF is halted. 0: SIOF runs 1: Clock supply to SIOF halted 6 to 0 All 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 362 of 804 13.2.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in the powerdown mode. STBCR4 is initialized at power-on reset but retains the previous value after manual reset. Bit 7 Bit Name Initial Value R/W 0 R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 6 MSTP46 0 R/W Module Stop 46 When the MSTP46 bit is set to 1, the supply of the clock to the USB is halted. 0: USB runs 1: Clock supply to USB halted Note: If this bit is set to 1, it can only be cleared by a power-on reset. Even if 0 is written to this bit, it cannot be cleared to 0. 5, 4 All 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 3 MSTP43 0 R/W Module Stop 43 When the MSTP43 bit is set to 1, the supply of the clock to the BOOT is halted. 0: BOOT runs 1: Clock supply to BOOT halted Note: When this bit is changed from 1 to 0 (when the supply to the BOOT was in a halted state and then changed to a run state), it takes time until access to the BOOT module is possible. When this bit is changed from 1 to 0, accessing the BOOT module should be made after the STBCR4 register is read to secure a time for warm up. 2 MSTP42 0 R/W Module Stop 42 When the MSTP42 bit is set to 1, the supply of the clock to the DAC is halted. 0: DAC runs 1: Clock supply to DAC halted Rev. 1.00, 02/04, page 363 of 804 Bit 1 Bit Name MSTP41 Initial Value R/W 0 R/W Description Module Stop 41 When the MSTP41 bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: The SCIF1 runs 1: Clock supply to the SCIF1 halted 0 MSTP40 0 R/W Module Stop 40 When the MSTP40 bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: The SCIF0 runs 1: Clock supply to the SCIR0 halted Rev. 1.00, 02/04, page 364 of 804 13.2.5 Memory Clock Control Register (MCCR) MCCR is an 8-bit readable/writable register that controls the operation of the memory clock on/off in sleep mode. MCCR is initialized at power-on reset but retains the previous value after manual reset. Bit 7 to 3 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 2 UMCLKC 0 R/W U Memory Clock Control Controls the U memory on/off in sleep mode 0: U memory clock off in sleep mode 1: U memory clock on in sleep mode When this bit is set to 1, it is possible to access the U memory with DMAC and USBH in sleep mode. Note: When changing the clock frequency multiplication ratio, clear UMCLKC bit to 0. There is the restriction on the interrupt processing when this function is used. Refer to section 7, U Memory for details. 1 XYMCLKC 0 R/W X/Y Memory Clock Control Controls the X/Y memory on/off in sleep mode 0: X/Y memory clock off in sleep mode 1: X/Y memory clock on in sleep mode When this bit is set to 1, it is possible to access the X/Y memory with DMAC and USBH in sleep mode. Note: When changing the clock frequency multiplication ratio, clear XYMCLKC bit to 0. There is the restriction on the interrupt processing when this function is used. Refer to section 6, X/Y Memory for details. 0 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 365 of 804 13.3 13.3.1 Operation Sleep Mode 1. Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO pin. 2. Canceling Sleep Mode Sleep mode is canceled by interrupts (NMI, IRQ, and on-chip peripheral module) or reset. Interrupts are accepted in sleep mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. Canceling with an Interrupt When an NMI, IRQ or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. A code indicating the interrupt source is set in the INTEVT2 registers. Canceling with a Reset Sleep mode is canceled by a power-on reset or a manual reset. 13.3.2 Software Standby Mode 1. Transition to Software Standby Mode The LSI switches from a program execution state to a software standby mode by executing the SLEEP instruction when the STBY bit in STBCR register is 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output state from the CKIO pin can be selected by combining the CKOEN bit in the FRQCR register and the HIZCNT bit in the CMNCR register. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Table 13.3 lists the states of on-chip peripheral module registers in a software standby mode. Rev. 1.00, 02/04, page 366 of 804 Table 13.3 Register States in Software Standby Mode Module Interrupt controller (INTC) Bus state controller (BSC) DMAC Clock pulse generator (CPG) Timer Unit (TMU) SIOF, SCIF0, SCIF1 USBPM, USBH, USBF D/A converter (DAC) I/O port User break controller (UBC) H-UDI Registers Initialized TSTR register Registers Retaining Data All registers All registers All registers All registers Except TSTR register All registers All registers All registers All registers All registers All registers The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. 2. Set the WDT's timer counter (WTCNT) to 0 and the CKS2 to CKS0 bits in the WTCSR register to appropriate values to secure the specified oscillation settling time. 3. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed. 2. Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI, IRQ) or a reset. Canceling with an Interrupt The on-chip WDT can be used for hot starts. When the chip detects an NMI or IRQ interrupt, the clock will be supplied to the entire chip and software standby mode canceled after the time set in the WDT's timer control/status register has elapsed. Interrupt handling then begins and a code indicating the interrupt source is set in the INTEVT2 registers. After the branch to the interrupt handling routine, clear the STBY bit in the STBCR register. WTD stops automatically. If the STBY bit is not cleared, WTD continues operation and a transition is made to software standby mode* when the WTCNT reaches H'80. Interrupts are accepted in software standby mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction. Immediately after an interrupt is detected, the phase of the CKIO pin clock output may be unstable, until the software standby mode is canceled when the CKOEN bit in the FRQCR register and the HIZCNT bit in the CMNCR register are set to 1. Note: * This standby mode can be canceled by the reset from the RESETP pin. Rev. 1.00, 02/04, page 367 of 804 Interrupt request Crystal oscillator settling time and PLL synchronization time WTCNT value WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR. STBY is cleared, WTCNT halts automatically. H'FF H'80 Time Figure 13.1 Canceling Standby Mode with STBCR.STBY Canceling with a Reset Software standby mode is canceled by a reset using the RESETP pin. Keep the RESETP pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin except clock operating mode 7. 13.3.3 Module Standby Function 1. Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode as well as sleep mode. The module should be disabled before a transition to the module standby function is made. In module standby state, the functions of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module and port settings. Almost all of the register states are the same as those in standby mode. For details, refer to table 13.3. 2. Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits to 0, or by a poweron reset. To cancel the module standby function by clearing the corresponding MSTP bit to 0, read the MSTP bit to check the MSTP bit was cleared correctly. Rev. 1.00, 02/04, page 368 of 804 13.3.4 State Transitions between Modes Figure 13.2 shows the transition between modes. Power supply off PLL stabilization time Normal operating mode* (PLL on) PLL stabilization time Sleep mode (PLL on) Software standby mode Note: * Normal operating modes (clock operating modes 5, 6, and 7) include the module standby function and changing multiplication rate. Figure 13.2 Transitions between Modes 13.3.5 Method of turning off the built-in regulator (external VDD used) The power dissipation of this LSI can be decreased by turning off the built-in regulator if internal power VDD (= 1.5 V) is supplied from the outside. When TEST_REG pin is low, REG_PD_MAIN pin, REG_PD_BGR pin, and REG_PD_VREF pin are high, the built-in regulator is turned off, and then internal power VDD (= 1.5 V) can be supplied from the outside. As a result, an internal power loss in a built-in regulator can be decreased. Rev. 1.00, 02/04, page 369 of 804 13.4 13.4.1 Usage note Reset by the RESETP pin The RDI_REFCLK_IN pin should be supplied with some clock input although Renesas RF-IC is not used. The RESETP pin has the function to maintain the reset signal internally during specified clock cycles from RDI_REFCLK_IN. Rev. 1.00, 02/04, page 370 of 804 Section 14 Timer Unit (TMU) This LSI includes a three-channel 32-bit timer unit (TMU). 14.1 Features * Each channel is provided with an auto-reload 32-bit down counter * All the channels are provided with 32-bit constant registers and 32-bit down counters for an auto-reload that can be read or written to at any time * All the channels generate interrupt requests when the 32-bit down counter underflows (H'00000000 H'FFFFFFFF) * Allows selection among 4 counter input clocks: P/4, P/16, P/64, and P/256 Figure 14.1 shows a block diagram of the TMU. Rev. 1.00, 02/04, page 371 of 804 P Prescaler Clock controller Channel 0 TSTR TCR_0 Counter controller TCNT_0 TCOR_0 TUNI0 Interrupt controller TCR_1 Counter controller TCNT_1 TUNI1 Interrupt controller Channel 2 TCOR_1 TCR_2 Counter controller TCNT_2 TUNI2 Interrupt controller TCOR_2 TMU Legend TSTR: Timer start register TCR: Timer control register TCNT: Timer counter TCOR: Timer constant register Figure 14.1 TMU Block Diagram Rev. 1.00, 02/04, page 372 of 804 Peripheral bus Channel 1 Internal bus Bus interface 14.2 Register Descriptions The TMU has the following registers. Refer to section 27, List of Registers, for more details of the addresses of these registers and state of these registers in each processor mode. The TMU register names are expressed in the XXX_N form, with XXX indicating the register name and N indicating the channel number. For example, TCOR_0 represents the TCOR for channel 0. Common Timer start register (TSTR) 2. Channel 0 Timer constant register_0 (TCOR_0) Timer counter_0 (TCNT_0) Timer control register_0 (TCR_0) 3. Channel 1 Timer constant register_1 (TCOR_1) Timer counter_1 (TCNT_1) Timer control register_1 (TCR_1) 4. Channel 2 Timer constant register_2 (TCOR_2) Timer counter_2 (TCNT_2) Timer control register_2 (TCR_2) 1. Rev. 1.00, 02/04, page 373 of 804 14.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects whether to run or halt the timer counters (TCNT). Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 2 STR2 0 R/W Counter Start 2 Selects whether to run or halt timer counter 2 (TCNT_2). 0: TCNT_2 count halted 1: TCNT_2 counts 1 STR1 0 R/W Counter Start 1 Selects whether to run or halt timer counter 1 (TCNT_1). 0: TCNT_1 count halted 1: TCNT_1 counts 0 STR0 0 R/W Counter Start 0 Selects whether to run or halt timer counter 0 (TCNT_0). 0: TCNT_0 count halted 1: TCNT_0 counts 7 to 3 14.2.2 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers that control the timer counters (TCNT) and interrupts. The TCR registers control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out counter clock selection. Rev. 1.00, 02/04, page 374 of 804 Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 15 to 9 8 UNF 0 R/(W)* Underflow Flag Status flag that indicates occurrence of a TCNT underflow. 0: TCNT has not underflowed [Clearing condition] 0 is written to UNF 1: TCNT has underflowed [Setting condition] TCNT underflows 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 5 UNIE 0 R/W Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT underflow has been set to 1. 0: Interrupt due to UNF (TUNI) is disabled 1: Interrupt due to UNF (TUNI) is enabled 4 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 1 0 TPSC1 TPSC0 0 0 R/W R/W Timer Prescaler 1 and 0 Select the TCNT count clock. 00: Count on P/4 01: Count on P/16 10: Count on P/64 11: Count on P/256 Note: * Only 0 can be written for flag clearing. Rev. 1.00, 02/04, page 375 of 804 14.2.3 Timer Constant Registers (TCOR) The TCOR registers set the value to be set in TCNT when TCNT underflows. The TCOR registers are 32-bit readable/writable registers. Their initial value is H'FFFFFFFF. 14.2.4 Timer Counters (TCNT) TCNT counts down upon input of a clock. The clock input is selected using the TPSC1 and TPSC0 bits in the timer control register (TCR). When a TCNT count-down results in an underflow (H'00000000 H'FFFFFFFF), the underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is simultaneously set in TCNT itself and the count-down continues from that value. Initial value of the TCNT is H'FFFFFFFF. Rev. 1.00, 02/04, page 376 of 804 14.3 Operation Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). The TCNT counts down. The auto-reload function enables synchronized counting. 14.3.1 Counter Operation When the STR0-STR2 bits in the timer start register (TSTR) are set to 1, the corresponding timer counter (TCNT) starts counting. When a TCNT underflows, the UNF flag of the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT and the down-count operation is continued. 1. Count Operation Setting Procedure An example of the procedure for setting the count operation is shown in figure 14.2. Select operation Select counter clock (1) (1) Select the counter clock with the TPSC1 to TPSC0 bits in the timer control register (TCR). Set underflow interrupt generation (2) Use the UNIE bit in TCR to set whether to (2) generate an interrupt when TCNT underflows. (3) Set a value in the timer constant register (TCOR) (the cycle is the set value plus 1). Set timer constant register (3) (4) Set the initial value in the timer counter (TCNT). (5) Set the STR bit in the timer start register (TSTR) Initialize timer counter (4) to 1 to start operation. Start counting (5) Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated. Figure 14.2 Setting Count Operation Rev. 1.00, 02/04, page 377 of 804 2. Auto-Reload Count Operation Figure 14.3 shows the TCNT auto-reload operation. TCOR value set to TCNT during underflow TCNT value TCOR H'00000000 Time STR0 to STR2 UNF Figure 14.3 Auto-Reload Count Operation 3. TCNT Count Timing Set the TPSC1 and TPSC0 bits in TCR to select one of the four internal clocks (P/4, P/16, P/64, P/256) that is created by dividing the peripheral module clock. Figure 14.4 shows the timing. P Divided clock TCNT input clock TCNT N+1 N N-1 Figure 14.4 Count Timing when Internal Clock Is Operating Rev. 1.00, 02/04, page 378 of 804 14.4 Interrupts There is one source of TMU interrupts: underflow interrupts (TUNI). 14.4.1 Status Flag Set Timing The UNF bit is set to 1 when the TCNT underflows. Figure 14.5 shows the timing. P TCNT Underflow signal H'00000000 TCOR value UNF TUNI Figure 14.5 UNF Set Timing 14.4.2 Status Flag Clear Timing The status flag can be cleared by writing 0 from the CPU. Figure 14.6 shows the timing. TCR write cycle T1 P T2 T3 Peripheral address bus TCR address UNF Figure 14.6 Status Flag Clear Timing Rev. 1.00, 02/04, page 379 of 804 14.4.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event register 2 (INTEVT2) for these interrupts and interrupt processing occurs according to the codes. The relative priorities of channels can be changed using the interrupt controller (see section 4, Exception Handling, and section 8, Interrupt Controller (INTC)). Table 14.1 lists TMU interrupt sources. Table 14.1 TMU Interrupt Sources Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Low Priority High 14.5 Usage Notes Writing to Registers: Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in the timer start register (TSTR) to halt timer counting. Reading Registers: Synchronization processing is performed for timer counting during register reads. When timer counting and register read processing are performed simultaneously, the register value before TCNT counting down (with synchronization processing) is read. Rev. 1.00, 02/04, page 380 of 804 Section 15 Serial I/O with FIFO (SIOF) This LSI includes a clock-synchronized serial I/O module with FIFO (SIOF)(Serial Input/Output with FIFO). The SIOF can perform serial communication with a serial peripheral interface bus (SPI). 15.1 Features * Serial transfer 16-stage 32-bit FIFOs (transmission is independent) Supports 8-bit data/16-bit data/16-bit stereo audio output MSB first for data transmission Supports a maximum of 48-kHz sampling rate Synchronization by either frame synchronization pulse or left/right channel switch Supports CODEC control data interface Connectable to linear, audio, or A-Law or -Law CODEC chip Supports both master and slave modes * Serial clock An external pin input or internal clock (P) can be selected as the clock source. * Interrupts: One type * DMA transfer Supports DMA transfer by a transfer request for transmission * SPI mode Fixed master mode can perform the full-duplex communication with the SPI slave devices continuously. Selects the falling/rising edge of the SCK as data sampling. Selects the clock phase of the SCK as a transmit timing. Selects three slave devices. The length of transmit/receive data is fixed to 8 bits. SCIS3F2D_000020020800 Rev. 1.00, 02/04, page 381 of 804 Figure 15.1 shows a block diagram of the SIOF. SIOF interrupt request Bus interface Peripheral bus Control registers Transmit FIFO (32 bits x16 stages) Receive FIFO (32 bits x16 stages) P Transmit control data Receive control data Baud rate generator 1/nMCLK Timing control P/S S/P SIOFMCLK SIOFSCK SIOFSYNC SIOFTXD SIOFRXD Figure 15.1 Block Diagram of SIOF Rev. 1.00, 02/04, page 382 of 804 15.2 Input/Output Pins The pin configuration in this module is shown in table 15.1. Table 15.1 Pin Configuration Pin Name SIOF_MCLK SIOF_SCK (SCK) SIOF_SYNC (SIOF_SS0) Abbreviation* SIOFMCLK SIOFSCK (SCK) I/O Input I/O Function Master clock input Serial clock (common to transmission/reception) In SPI mode, fixed to output. SIOFSYNC (SS0) I/O Frame synchronous signal (common to transmission/reception) In SPI mode, fixed to output, and selects slave device 0. SIOF_SS1 SIOF_SS2 SIOF_TXD (MOSI) SIOF_RXD (MISO) Note: * (SS1) (SS2) Output Output In SPI mode, selects slave device 1. In SPI mode, selects slave device 2. Transmit data Receive data SIOFTXD (MOSI) Output SIOFRXD (MISO) Input The pins are collectively called SIOFMCLK, SIOFSCK, SIOFSYNC, SIOFTXD, and SIOFRXD in the following descriptions. In SPI mode, the pins are called SCK, SS0, SS1, SS2, MOSI, and MISO. Rev. 1.00, 02/04, page 383 of 804 15.3 Register Descriptions The SIOF has the following registers. For the addresses of these registers and the register states in each operating state, refer to section 27, List of Registers. * * * * * * * * * * * * * * Mode register (SIMDR) Control register (SICTR) Transmit data register (SITDR) Receive data register (SIRDR) Transmit control data register (SITCR) Receive control data register (SIRCR) Status register (SISTR) Interrupt enable register (SIIER) FIFO control register (SIFCTR) Clock select register (SISCR) Transmit data assign register (SITDAR) Receive data assign register (SIRDAR) Control data assign register (SICDAR) SPI control register (SPICR) Mode Register (SIMDR) 15.3.1 SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode. Bit 15 14 Bit Name TRMD1 TRMD0 Initial Value 1 0 R/W R/W R/W Description Transfer Mode Select transfer mode as shown in table 15.2. 00: Slave mode 1 01: Slave mode 2 10: Master mode 1 11: Master mode 2 13 SYNCAT 0 R/W SIOFSYNC Pin Valid Timing Indicates the position of the SIOFSYNC signal to be output as a synchronization pulse. 0: At the start-bit data of frame 1: At the last-bit data of slot Rev. 1.00, 02/04, page 384 of 804 Bit 12 Bit Name REDG Initial Value 0 R/W R/W Description Receive Data Sampling Edge 0: The SIOFRXD signal is sampled at the falling edge of SIOFSCK. (The SIOFTXD signal is output at the rising edge of SIOFSCK). 1: The SIOFRXD signal is sampled at the rising edge of SIOFSCK. (The SIOFTXD signal is output at the falling edge of SIOFSCK). Note: This bit is valid only in master mode. 11 10 9 8 FL3 FL2 FL1 FL0 0 0 0 0 R/W R/W R/W R/W Frame Length 00xx: Data length is 8 bits and frame length is 8 bits. 0100: Data length is 8 bits and frame length is 16 bits. 0101: Data length is 8 bits and frame length is 32 bits. 0110: Data length is 8 bits and frame length is 64 bits. 0111: Data length is 8 bits and frame length is 128 bits. 10xx: Data length is 16 bits and frame length is 16 bits. 1100: Data length is 16 bits and frame length is 32 bits. 1101: Data length is 16 bits and frame length is 64 bits. 1110: Data length is 16 bits and frame length is 128 bits. 1111: Data length is 16 bits and frame length is 256 bits. Note: When data length is specified as 8 bits, control data cannot be transmitted or received. x: Don't care 7 TXDIZ 0 R/W SIOFTXD Pin Output when Transmission is Invalid* 0: High output (1 output) when invalid 1: High-impedance state when invalid Note: Invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 RCIM 0 R/W Receive Control Data Interrupt Mode 0: Sets the RCRDY bit in SISTR when the contents of SIRCR change. 1: Sets the RCRDY bit in SISTR each time when the SIRCR receives the control data. Rev. 1.00, 02/04, page 385 of 804 Bit 5 Bit Name SYNCAC Initial Value 0 R/W R/W Description SIOFSYNC Pin Polarity Valid when the SIOFSYNC signal is output as synchronous pulse in master mode. 0: Active-high 1: Active-low 4 SYNCDL 0 R/W Data Pin Bit Delay for SIOFSYNC Pin Valid when the SIOFSYNC signal is output as synchronous pulse. Only one-bit delay is valid for transmission in slave mode. 0: No bit delay 1: 1-bit delay 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation cannot be guaranteed. Table 15.2 shows the operation in each transfer mode. Table 15.2 Operation in Each Transfer Mode Transfer Mode Master/Slave Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 Note: * Slave Slave Master Master SIOFSYNC Bit Delay Control Data Method* Slot position Secondary FS Slot position No Not supported Synchronous pulse SYNCDL bit Synchronous pulse Synchronous pulse L/R The control data method is valid only when the FL bit is specified as 1xxx. (x: Don't care) Rev. 1.00, 02/04, page 386 of 804 15.3.2 Control Register (SICTR) SICTR is a 16-bit readable/writable register that sets the SIOF operating state. Bit 15 Bit Name SCKE Initial Value 0 R/W R/W Description Serial Clock Output Enable This bit is valid in master mode. 0: Disables the SIOFSCK output (outputs 0) 1: Enables the SIOFSCK output * If this bit is set to 1, the SIOF initializes the baud rate generator and initiates the operation. At the same time, the SIOF outputs the clock generated by the baud rate generator to the SIOFSCK pin. This bit is initialized in module stop mode. 14 FSE 0 R/W Frame Synchronous Signal Output Enable This bit is valid in master mode. 0: Disables the SIOFSYNC output (outputs 0) 1: Enables the SIOFSYNC output * If this bit is set to 1, the SIOF initializes the frame counter and initiates the operation. This bit is initialized in module stop mode. 13 to 10 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 387 of 804 Bit 9 Bit Name TXE Initial Value 0 R/W R/W Description Transmit Enable 0: Disables data transmission from the SIOFTXD pin 1: Enables data transmission from the SIOFTXD pin * * This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal). When the 1 setting for this bit becomes valid, the SIOF issues a transmit transfer request according to the setting of the TFWM bit in SIFCTR. When transmit data is stored in the transmit FIFO, transmission of data from the SIOFTXD pin begins. This bit is initialized upon a transmit reset. * 8 RXE 0 R/W This bit is initialized in module stop mode. Receive Enable 0: Disables data reception from SIOFRXD 1: Enables data reception from SIOFRXD * * This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal). When the 1 setting for this bit becomes valid, the SIOF begins the reception of data from the SIOFRXD pin. When receive data is stored in the receive FIFO, the SIOF issues a reception transfer request according to the setting of the RFWM bit in SIFCTR. This bit is initialized upon receive reset. * 7 to 2 -- All 0 R This bit is initialized in module stop mode. Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 388 of 804 Bit 1 Bit Name TXRST Initial Value 0 R/W R/W Description Transmit Reset 0: Does not reset transmit operation 1: Resets transmit operation * This bit setting becomes valid immediately. This bit should be cleared to 0 before setting the register to be initialized. When the 1 setting for this bit becomes valid, the SIOF immediately sets transmit data from the SIOFTXD pin to 1, and initializes the transmit data register and transmit-related status. The following are initialized. SITDR SITCR Transmit FIFO write pointer TCRDY, TFEMP, and TDREQ bits in SISTR This bit is automatically cleared by SIOF after completes a reset, to be always read as 0. * 0 RXRST 0 R/W Receive Reset 0: Does not reset receive operation 1: Resets receive operation * This bit setting becomes valid immediately. This bit should be cleared to 0 before setting the register to be initialized. When the 1 setting for this bit becomes valid, the SIOF immediately disables reception from the SIOFRXD pin, and initializes the receive data register and receive-related status. The following are initialized. SIRDR SIRCR Receive FIFO read pointer RCRDY, RFFUL, and RDREQ bits in SISTR This bit is automatically cleared by SIOF after completes a reset, to be always read as 0. * Rev. 1.00, 02/04, page 389 of 804 15.3.3 Transmit Data Register (SITDR) SITDR is a 32-bit write-only register that specifies the SIOF transmit data. SITDR is initialized by the conditions specified in section 27, List of Registers, or by a transmit reset caused by the TXRST bit in SICTR. SITDR is initialized in module stop mode. Bit Bit Name Initial Value R/W Description W Left-Channel Transmit Data Specify data to be output from the SIOFTXD pin as left-channel data. The position of the left-channel data in the transmit frame is specified by the TDLA bit in SITDAR. * 15 to 0 SITDR15 to SITDR0 All 0 W These bits are valid only when the TDLE bit in SITDAR is set to 1. 31 to 16 SITDL15 to SITDL0 All 0 Right-Channel Transmit Data Specify data to be output from the SIOFTXD pin as right-channel data. The position of the right-channel data in the transmit frame is specified by the TDRA bit in SITDAR. * These bits are valid only when the TDRE bit and TLREP bit in SITDAR are set to 1 and cleared to 0, respectively. Rev. 1.00, 02/04, page 390 of 804 15.3.4 Receive Data Register (SIRDR) SIRDR is a 32-bit read-only register that reads receive data of the SIOF. SIRDR stores data in the receive FIFO and is initialized by the conditions specified in section 27, List of Registers, or by a receive reset caused by the RXRST bit in SICTR. Bit Bit Name Initial Value R/W Description R Left-Channel Receive Data Store data received from the SIOFRXD pin as leftchannel data. The position of the left-channel data in the receive frame is specified by the RDLA bit in SIRDAR. * 15 to 0 SIRDR15 to SIRDR 0 All 0 R These bits are valid only when the RDLE bit in SIRDAR is set to 1. 31 to 16 SIRDL15 to SIRDL 0 All 0 Right-Channel Receive Data Store data received from the SIOFRXD pin as rightchannel data. The position of the right-channel data in the receive frame is specified by the RDRA bit in SIRDAR. * These bits are valid only when the RDRE bit in SIRDAR is set to 1. Rev. 1.00, 02/04, page 391 of 804 15.3.5 Transmit Control Data Register (SITCR) SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. SITCR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care). SITCR is initialized by the conditions specified in section 27, List of Registers, or by a transmit reset caused by the TXRST bit in SICTR. SITCR is initialized in module stop mode. Bit Bit Name Initial Value R/W Description All 0 R/W Control Channel 0 Transmit Data Specify data to be output from the SIOFTXD pin as control channel 0 transmit data. The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR. * 15 to 0 SITC115 to SITC10 All 0 These bits are valid only when the CD0E bit in SICDAR is set to 1. 31 to 16 SITC015 to SITC00 R/W Control Channel 1 Transmit Data Specify data to be output from the SIOFTXD pin as control channel 1 transmit data. The position of the control channel 1 data in the transmit or receive frame is specified by the CD1A bit in SICDAR. * These bits are valid only when the CD1E bit in SICDAR is set to 1. Rev. 1.00, 02/04, page 392 of 804 15.3.6 Receive Control Data Register (SIRCR) SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care). SIRCR is initialized by the conditions specified in section 27, List of Registers, or by a receive reset caused by the RXRST bit in SICTR. Bit Bit Name Initial Value R/W Description R/W Control Channel 0 Receive Data Store data received from the SIOFRXD pin as control channel 0 receive data. The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR. * 15 to 0 SIRC115 to SIRC10 All 0 These bits are valid only when the CD0E bit in SICDAR is set to 1. 31 to 16 SIRC015 to SIRC00 All 0 R/W Control Channel 1 Receive Data Store data received from the SIOFRXD pin as control channel 1 receive data. The position of the control channel 1 data in the transmit or receive frame is specified by the CD1A bit in SICDAR. * These bits are valid only when the CD1E bit in SICDAR is set to 1. Rev. 1.00, 02/04, page 393 of 804 15.3.7 Status Register (SISTR) SISTR is a 16-bit read-only register that shows the SIOF state. Each bit in this register becomes an SIOF interrupt source when the corresponding bit in SIIER is set to 1. SISTR is initialized in module stop mode. Bit 15 Bit Name -- Initial Value 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, the operation is not guaranteed. 14 TCRDY 0 R Transmit Control Data Ready 0: Indicates that a write to SITCR is disabled 1: Indicates that a write to SITCR is enabled * If SITCR is written when this bit is cleared to 0, SITCR is over-written and the previous contents of SITCR are not output from the SIOFTXD pin. This bit is valid when the TXE bit in SITCR is set to 1. This bit indicates a state of the SIOF. If SITCR is written, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. * * * 13 TFEMP 0 R Transmit FIFO Empty 0: Indicates that transmit FIFO is not empty 1: Indicates that transmit FIFO is empty * * * This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state; if SITDR is written, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 1.00, 02/04, page 394 of 804 Bit 12 Bit Name TDREQ Initial Value 0 R/W R Description Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO does not exceed the size specified by the TFWM bit in SIFCTR. 1: Indicates that the size of empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. A transmit data transfer request is issued when the empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. When using transmit data transfer through the DMAC, this bit is always cleared by one DMAC access. After DMAC access, when conditions for setting this bit are satisfied, the SIOF again indicates 1 for this bit. * * This bit is valid when the TXE bit in SICTR is 1. This bit indicates a state; if the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. * 11 -- 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to this bit, the operation is not guaranteed. 10 RCRDY 0 R Receive Control Data Ready 0: Indicates that the SIRCR stores no valid data. 1: Indicates that the SIRCR stores valid data. * * * * If SIRCR is written when this bit is set to 1, SIRCR is modified by the latest data. This bit is valid when the RXE bit in SICTR is set to 1. This bit indicates a state of the SIOF. If SIRCR is read, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 1.00, 02/04, page 395 of 804 Bit 9 Bit Name RFFUL Initial Value 0 R/W R Description Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full * * * This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state; if SIRDR is read, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 8 RDREQ 0 R Receive Data Transfer Request 0: Indicates that the size of valid space in the receive FIFO does not exceed the size specified by the RFWM bit in SIFCTR. 1: Indicates that the size of valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. A receive data transfer request is issued when the valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. When using receive data transfer through the DMAC, this bit is always cleared by one DMAC access. After DMAC access, when conditions for setting this bit are satisfied, the SIOF again indicates 1 for this bit. * * This bit is valid when the RXE bit in SICTR is 1. This bit indicates a state; if the size of valid space in the receive FIFO is less than the size specified by the RFWM bit in SIFCTR, the SIOF clears this bit. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. * 7, 6 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 396 of 804 Bit 5 Bit Name SAERR Initial Value 0 R/W R/W Description Slot Assign Error 0: Indicates that no slot assign error occurs 1: Indicates that a slot assign error occurs A slot assign error occurs when the specifications in SITDAR, SIRDAR, and SICDAR overlap. If a slot assign error occurs, the SIOF does not transmit data to the SIOFTXD pin and does not receive data from the SIOFRXD pin. Note that the SIOF does not clear the TXE bit or RXE bit in SICTR at a slot assign error. * * * This bit is valid when the TXE bit or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 4 FSERR 0 R/W Frame Synchronization Error 0: Indicates that no frame synchronization error occurs 1: Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. If a frame synchronization error occurs, the SIOF performs transmission or reception for slots that can be transferred. * * * This bit is valid when the TXE or RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 1.00, 02/04, page 397 of 804 Bit 3 Bit Name TFOVF Initial Value 0 R/W R/W Description Transmit FIFO Overflow 0: No transmit FIFO overflow 1: Transmit FIFO overflow A transmit FIFO overflow means that there has been an attempt to write to SITDR when the transmit FIFO is full. When a transmit FIFO overflow occurs, the SIOF indicates overflow, and writing is invalid. * * * This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 2 TFUDF 0 R/W Transmit FIFO Underflow 0: No transmit FIFO underflow 1: Transmit FIFO underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty. When a transmit FIFO underflow occurs, the SIOF repeatedly sends the previous transmit data. * * * This bit is valid when the TXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 1 RFUDF 0 R/W Receive FIFO Underflow 0: No receive FIFO underflow 1: Receive FIFO underflow A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed. * * * This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. Rev. 1.00, 02/04, page 398 of 804 Bit 0 Bit Name RFOVF Initial Value 0 R/W R/W Description Receive FIFO Overflow 0: No receive FIFO overflow 1: Receive FIFO overflow A receive FIFO overflow means that writing has occurred when the receive FIFO is full. When a receive FIFO overflow occurs, the SIOF indicates overflow, and receive data is lost. * * * This bit is valid when the RXE bit in SICTR is 1. When 1 is written to this bit, the contents are cleared. Writing 0 to this bit is invalid. If the issue of interrupts by this bit is enabled, an SIOF interrupt is issued. 15.3.8 Interrupt Enable Register (SIIER) SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an interrupt. Bit 15 Bit Name TDMAE Initial Value 0 R/W R/W Description Transmit Data DMA Transfer Request Enable Transmits an interrupt as an interrupt to the CPU/DMA transfer request. The TDREQE bit can be set as transmit interrupts. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the DMAC 14 TCRDYE 0 R/W Transmit Control Data Ready Enable 0: Disables interrupts due to transmit control data ready 1: Enables interrupts due to transmit control data ready 13 TFEMPE 0 R/W Transmit FIFO Empty Enable 0: Disables interrupts due to transmit FIFO empty 1: Enables interrupts due to transmit FIFO empty Rev. 1.00, 02/04, page 399 of 804 Bit 12 Bit Name TDREQE Initial Value 0 R/W R/W Description Transmit Data Transfer Request Enable 0: Disables interrupts due to transmit data transfer requests 1: Enables interrupts due to transmit data transfer requests 11 RDMAE 0 R/W Receive Data DMA Transfer Request Enable Transmits an interrupt as an interrupt to the CPU/DMA transfer request. The RDREQE bit can be set as receive interrupts. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the DMAC 10 RCRDYE 0 R/W Receive Control Data Ready Enable 0: Disables interrupts due to receive control data ready 1: Enables interrupts due to receive control data ready 9 RFFULE 0 R/W Receive FIFO Full Enable 0: Disables interrupts due to receive FIFO full 1: Enables interrupts due to receive FIFO full 8 RDREQE 0 R/W Receive Data Transfer Request Enable 0: Disables interrupts due to receive data transfer requests 1: Enables interrupts due to receive data transfer requests 7, 6 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. 5 SAERRE 0 R/W Slot Assign Error Enable 0: Disables interrupts due to slot assign error 1: Enables interrupts due to slot assign error 4 FSERRE 0 R/W Frame Synchronization Error Enable 0: Disables interrupts due to frame synchronization error 1: Enables interrupts due to frame synchronization error 3 TFOVFE 0 R/W Transmit FIFO Overflow Enable 0: Disables interrupts due to transmit FIFO overflow 1: Enables interrupts due to transmit FIFO overflow Rev. 1.00, 02/04, page 400 of 804 Bit 2 Bit Name TFUDFE Initial Value 0 R/W R/W Description Transmit FIFO Underflow Enable 0: Disables interrupts due to transmit FIFO underflow 1: Enables interrupts due to transmit FIFO underflow 1 RFUDFE 0 R/W Receive FIFO Underflow Enable 0: Disables interrupts due to receive FIFO underflow 1: Enables interrupts due to receive FIFO underflow 0 RFOVFE 0 R/W Receive FIFO Overflow Enable 0: Disables interrupts due to receive FIFO overflow 1: Enables interrupts due to receive FIFO overflow 15.3.9 FIFO Control Register (SIFCTR) SIFCTR is a 16-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer. Bit 15 14 13 Bit Name TFWM2 TFWM1 TFWM0 Initial Value 0 0 0 R/W R/W R/W R/W Description Transmit FIFO Watermark 000: Issue a transfer request when 16 stages of the transmit FIFO are empty. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 12 or more stages of the transmit FIFO are empty. 101: Issue a transfer request when 8 or more stages of the transmit FIFO are empty. 110: Issue a transfer request when 4 or more stages of the transmit FIFO are empty. 111: Issue a transfer request when 1 or more stages of transmit FIFO are empty. * * A transfer request to the transmit FIFO is issued by the TDREQE bit in SISTR. The transmit FIFO is always used as 16 stages of the FIFO regardless of these bit settings. Rev. 1.00, 02/04, page 401 of 804 Bit 12 11 10 9 8 7 6 5 Bit Name TFUA4 TFUA3 TFUA2 TFUA1 TFUA0 RFWM2 RFWM1 RFWM0 Initial Value 1 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Description Transmit FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'00000 (full) to B'10000 (empty). Receive FIFO Watermark 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 4 or more stages of the receive FIFO are valid. 101: Issue a transfer request when 8 or more stages of the receive FIFO are valid. 110: Issue a transfer request when 12 or more stages of the receive FIFO are valid. 111: Issue a transfer request when 16 stages of the receive FIFO are valid. * * A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR. The receive FIFO is always used as 16 stages of the FIFO regardless of these bit settings. 4 3 2 1 0 RFUA4 RFUA3 RFUA2 RFUA1 RFUA0 0 0 0 0 0 R R R R R Receive FIFO Usable Area Indicate the number of words that can be transferred by the CPU or DMAC as B'00000 (empty) to B'10000 (full). Rev. 1.00, 02/04, page 402 of 804 15.3.10 Clock Select Register (SISCR) SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the master clock. SISCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are specified as B'10 or B'11. Bit 15 Bit Name MSSEL Initial Value 1 R/W R/W Description Master Clock Source Selection 0: Uses the input signal of the SIOFMCLK pin as the master clock 1: Uses P as the master clock The master clock is the clock input to the baud rate generator. 14 MSIMM 1 R/W Master Clock Direct Selection 0: Uses the output clock of the baud rate generator as the serial clock 1: Uses the master clock itself as the serial clock 13 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, the operation is not guaranteed. 12 11 10 9 8 7 to 3 BRPS4 BRPS3 BRPS2 BRPS1 BRPS0 -- 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R Prescaler Setting Set the master clock division ratio according to the count value of the prescaler of the baud rate generator. The range of settings is from B'00000 (x 1/1) to B'11111 (x 1/32). Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 403 of 804 Bit 2 1 0 Bit Name BRDV2 BRDV1 BRDV0 Initial Value 0 0 0 R/W R/W R/W R/W Description Baud Rate Generator's Division Ratio Setting Set the frequency division ratio for the output stage of the baud rate generator. 000: Prescaler output x 1/2 001: Prescaler output x 1/4 010: Prescaler output x 1/8 011: Prescaler output x 1/16 100: Prescaler output x 1/32 101: Setting prohibited 110: Setting prohibited 111: Prescaler output x 1/1* The final frequency division ratio of the baud rate generator is determined by BRPS x BRDV (maximum 1/1024). Note: * This setting is valid only when the BRPS4 to BRPS0 bits are set to B'00000. 15.3.11 Transmit Data Assign Register (SITDAR) SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a frame (slot number). Bit 15 Bit Name TDLE Initial Value 0 R/W R/W Description Transmit Left-Channel Data Enable 0: Disables left-channel data transmission 1: Enables left-channel data transmission 14 to 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. 11 10 9 8 TDLA3 TDLA2 TDLA1 TDLA0 0 0 0 0 R/W R/W R/W R/W Transmit Left-Channel Data Assigns 3 to 0 Specify the position of left-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Transmit data for the left channel is specified in the SITDL bit in SITDR. Rev. 1.00, 02/04, page 404 of 804 Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Right-Channel Data Enable 0: Disables right-channel data transmission 1: Enables right-channel data transmission 6 TLREP 0 R/W Transmit Left-Channel Repeat 0: Transmits data specified in the SITDR bit in SITDR as right-channel data 1: Repeatedly transmits data specified in the SITDL bit in SITDR as right-channel data * * This bit setting is valid when the TDRE bit is set to 1. When this bit is set to 1, the SITDR bit settings are ignored. 5, 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. 3 2 1 0 TDRA3 TDRA2 TDRA1 TDRA0 0 0 0 0 R/W R/W R/W R/W Transmit Right-Channel Data Assign Specify the position of right-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Transmit data for the right channel is specified in the SITDR bit in SITDR. 15.3.12 Receive Data Assign Register (SIRDAR) SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a frame (slot number). Bit 15 Bit Name RDLE Initial Value 0 R/W R/W Description Receive Left-Channel Data Enable 0: Disables left-channel data reception 1: Enables left-channel data reception 14 to 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 405 of 804 Bit 11 10 9 8 Bit Name RDLA3 RDLA2 RDLA1 RDLA0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Receive Left-Channel Data Assign Specify the position of left-channel data in a receive frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Receive data for the left channel is stored in the SIRDL bit in SIRDR. 7 RDRE 0 R/W Receive Right-Channel Data Enable 0: Disables right-channel data reception 1: Enables right-channel data reception 6 to 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. 3 2 1 0 RDRA3 RDRA2 RDRA1 RDRA0 0 0 0 0 R/W R/W R/W R/W Receive Right-Channel Data Assign Specify the position of right-channel data in a receive frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * Receive data for the right channel is stored in the SIRDR bit in SIRDR. 15.3.13 Control Data Assign Register (SICDAR) SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a frame (slot number). SICDAR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care). Bit 15 Bit Name CD0E Initial Value 0 R/W R/W Description Control Channel 0 Data Enable 0: Disables transmission and reception of control channel 0 data 1: Enables transmission and reception of control channel 0 data 14 to 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 406 of 804 Bit 11 10 9 8 Bit Name CD0A3 CD0A2 CD0A1 CD0A0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Control Channel 0 Data Assign Specify the position of control channel 0 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * * Transmit data for the control channel 0 data is specified in the SITD0 bit in SITCR. Receive data for the control channel 0 data is stored in the SIRD0 bit in SIRCR. 7 CD1E 0 R/W Control Channel 1 Data Enable 0: Disables transmission and reception of control channel 1 data 1: Enables transmission and reception of control channel 1 data 6 to 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. 3 2 1 0 CD1A3 CD1A2 CD1A1 CD1A0 0 0 0 0 R/W R/W R/W R/W Control Channel 1 Data Assign Specify the position of control channel 1 data in a receive or transmit frame as B'0000 (0) to B'1110 (14). 1111: Setting prohibited * * Transmit data for the control channel 1 data is specified in the SITD1 bit in SITCR. Receive data for the control channel 1 data is stored in the SIRD1 bit in SIRCR. Rev. 1.00, 02/04, page 407 of 804 15.3.14 SPI Control Register (SPICR) SPICR is a 16-bit readable/writable register that specifies the operating mode of the SPI. Bit 15 Bit Name SPIM Initial Value 0 R/W R/W Description SPI Mode Selects the SIOF operating mode. 0: Operates as the SIOF. 1: The SIOF operates in master mode of the SPI. 14 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, the operation is not guaranteed. 13 CPHA 0 R/W SPI Clock Phase Selects the SPI clock phase. 0: Samples data at the first edge of the SCK. 1: Samples data at the second edge of the SCK. 12 CPOL 0 R/W SPI Clock Polarity Selects the SPI clock polarity. 0: The SCK is high-active, and goes low in the idle state. 1: The SCK is low-active, and goes high in the idle state. 11 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, the operation is not guaranteed. 10 SS2E* 0 R/W Slave Device 2 (SS2) Enable 0: Not select slave device 2. 1: Selects slave device 2. 9 SS1E* 0 R/W Slave Device 1 (SS1) Enable 0: Not select slave device 1. 1: Selects slave device 1. 8 SS0E* 0 R/W Slave Device 0 (SS0) Enable 0: Not select slave device 0. 1: Selects slave device 0. 7, 6 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, the operation is not guaranteed. Rev. 1.00, 02/04, page 408 of 804 Bit 5 4 Bit Name SSAST1 SSAST0 Initial Value 0 0 R/W R/W R/W Description Setting of SS Assert Set the setup timing of the SS for the SCK. * CPHA = 0 SSAST[1:0] 00 01 10 11 * CPHA = 1 SSAST[1:0] 00 01 10 11 SS Setup 0 clock 0.5 clock 1 clock 1.5 clock SS Setup 0.5 clock 1 clock 1.5 clock 2 clock (Unit: SCK clock) SS Hold 0 clock 0.5 clock 1 clock 1.5 clock (Unit: SCK clock) SS Hold 0.5 clock 1 clock 1.5 clock 2 clock 3, 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 1 0 FLD1 FLD0 0 0 R/W R/W Frame Delay Specify the minimum time of the idle state between frames in terms of the clock number of the SCK. 00: No delay. The continuous communication of the SPI is performed when the SS pin asserts low continuously. 01: Delay for 1 clock of the SCK. 10: Delay for 2 clocks of the SCK. 11: Delay for 3 clocks of the SCK. Note: * The SS0E, SS1E, and SS2E bits must not be simultaneously set to 1. Rev. 1.00, 02/04, page 409 of 804 15.4 15.4.1 Operation Serial Clocks Master/Slave Modes: The following 2 modes are available as the SIOF clock mode. * Slave mode: SIOFSCK, SIOFSYNC input * Master mode: SIOFSCK, SIOFSYNC output Baud Rate Generator: In SIOF master mode, the baud rate generator (BRG) is used to generate the serial clock. The division ratio is from 1/1 to 1/1024. Figure 15.2 shows connections for supply of the serial clock. MCLK BRG 1/1 to 1/1024 MCLK SIOFMCLK P Timing control SCKE Master SIOFSCK Figure 15.2 Serial Clock Supply Table 15.3 shows an example of serial clock frequency. Table 15.3 SIOF Serial Clock Frequency Sampling Rate Frame Length 32 bits 64 bits 128 bits 256 bits 8 kHz 256 kHz 512 kHz 1.024 MHz 2.048 MHz 44.1 kHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 11.289 MHz 48 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.289 MHz Rev. 1.00, 02/04, page 410 of 804 15.4.2 Serial Timing SIOFSYNC: The SIOFSYNC is a frame synchronous (FS) signal. Depending on the transfer mode, it has the following two functions. * Synchronous pulse: 1-bit-width pulse indicating the start of the frame * L/R: 1/2-frame-width pulse indicating the left-channel stereo data (L) in high level and the right-channel stereo data (R) in low level Figure 15.3 shows the SIOFSYNC synchronization timing. (a) Synchronous pulse 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD Start bit data 1-bit delay (b) L/R 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD Start bit of left channel data (1/2 frame length) No delay Start bit of right channel data (1/2 frame length) MSB MSB MSB Figure 15.3 Serial Data Synchronization Timing Transmit/Receive Timing: The SIOFTXD transmit timing and SIOFRXD receive timing relative to the SIOFSCK can be set as the sampling timing in the following two ways. The transmit/receive timing is set using the REDG bit in SIMDR. * Falling-edge sampling * Rising-edge sampling Figure 15.4 shows the transmit/receive timing. Rev. 1.00, 02/04, page 411 of 804 (a) Falling-edge sampling SIOFSCK SIOFSYNC SIOFTXD SIOFRXD Receive timing Transmit timing (a) Rising-edge sampling SIOFSCK SIOFSYNC SIOFTXD SIOFRXD Receive timing Transmit timing Figure 15.4 SIOF Transmit/Receive Timing 15.4.3 Transfer Data Format The SIOF performs the following transfer. * Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data * Control data: Transfer of 16-bit data (uses the specific register as interface) Transfer Mode: The SIOF supports the following four transfer modes as listed in table 15.4. The transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR. Table 15.4 Serial Transfer Modes Transfer Mode Slave mode 1 Slave mode 2 Master mode 1 Master mode 2 SIOFSYNC Synchronous pulse Synchronous pulse Synchronous pulse L/R No Bit Delay SYNCDL bit Control Data Slot position Secondary FS Slot position Not supported Rev. 1.00, 02/04, page 412 of 804 Frame Length: The length of the frame to be transferred by the SIOF is specified by the FL3 to FL0 bits in SIMDR. Table 15.5 shows the relationship between the FL3 to FL0 bit settings and frame length. Table 15.5 Frame Length FL3 to FL0 00xx 0100 0101 0110 0111 10xx 1100 1101 1110 1111 Slot Length 8 8 8 8 8 16 16 16 16 16 Number of Bits in a Frame 8 16 32 64 128 16 32 64 128 256 Transfer Data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 8-bit monaural data 16-bit monaural data 16-bit monaural/stereo data 16-bit monaural/stereo data 16-bit monaural/stereo data 16-bit monaural/stereo data Note: x: Don't care Slot Position: The SIOF can specify the position of transmit data, receive data, and control data in a frame (common to transmission and reception) by slot numbers. The slot number of each data is specified by the following registers. * Transmit data: SITDAR * Receive data: SIRDAR * Control data: SICDAR Only 16-bit data is valid for control data. In addition, control data is always assigned to the same slot number both in transmission and reception. 15.4.4 Register Allocation of Transfer Data Transmit/Receive Data: Writing and reading of transmit/receive data is performed for the following registers. * Transmit data writing: SITDR (32-bit access) * Receive data reading: SIRDR (32-bit access) Rev. 1.00, 02/04, page 413 of 804 Figure 15.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment. (a) 16-bit stereo data 31 24 23 L-channel data 16 15 87 R-channel data 0 (b) 16-bit monaural data 31 24 23 Data 16 15 87 0 (c) 8-bit monaural data 31 24 23 Data 16 15 87 0 (d) 16-bit stereo data (left and right same audio output) data 31 24 23 16 15 87 Data 0 Figure 15.5 Transmit/Receive Data Bit Alignment Note: In the figure, only the shaded areas are transmitted or received as valid data. Therefore, access must be made in byte units for 8-bit data, and in word units for 16-bit data. Data in unshaded areas is not transmitted or received. Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR. Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR. To achieve left and right same audio output while stereo is specified for transmit data, specify the TLREP bit in SITDAR. Tables 15.6 and 15.7 show the audio mode specification for transmit data and that for receive data, respectively. Table 15.6 Audio Mode Specification for Transmit Data Bit Mode Monaural Stereo Left and right same audio output Note: x: Don't care TDLE 1 1 1 TDRE 0 1 1 TLREP x 0 1 Rev. 1.00, 02/04, page 414 of 804 Table 15.7 Audio Mode Specification for Receive Data Bit Mode Monaural Stereo RDLE 1 1 RDRE 0 1 Note: Left and right same audio mode is not supported in receive data. To execute 8-bit monaural transmission or reception, use the left channel. Control Data: Control data is written to or read from by the following registers. * Transmit control data write: SITCR (32-bit access) * Receive control data read: SIRCR (32-bit access) Figure 15.6 shows the control data and bit alignment in SITCR and SIRCR. (a) Control data: One channel 31 24 23 Control data (channel 0) 16 15 87 0 (b) Control data: Two channels 31 24 23 Control data (channel 0) 16 15 87 Control data (channel 1) 0 Figure 15.6 Control Data Bit Alignment The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR. Table 15.8 shows the relationship between the number of channels in control data and bit settings. Table 15.8 The Number of Channels in Control Data Setting Bit Number of Channels 1 2 Note: CD0E 1 1 To use only one channel in control data, use channel 0. CD1E 0 1 Rev. 1.00, 02/04, page 415 of 804 15.4.5 Control Data Interface Control data performs control command output to the CODEC and status input from the CODEC. The SIOF supports the following two control data interface methods. * Control by slot position * Control by secondary FS Control data is valid only when data length is specified as 16 bits. Control by Slot Position (Master Mode 1, Slave Mode 1): Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot position of control data. This method can be used in both SIOF master and slave modes. Figure 15.7 shows an example of the control data interface timing by slot position control. 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD L-channel data Control channel 0 R-channel data Control channel 1 Slot No.0 Slot No.1 Slot No.2 Slot No.3 REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0001, FL[3:0]=1110 (Frame length: 128 bits), TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0010, RDRE=1, CD1A[3:0]=0011 CD1E=1, Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=1, Figure 15.7 Control Data Interface (Slot Position) Control by Secondary FS (Slave Mode 2): The CODEC normally outputs the SIOFSYNC signal as synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to transmit or receive control data. This method is valid for SIOF slave mode. The following summarizes the control data interface procedure by the secondary FS. * Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears 0). * To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1 by writing SITCDR). * The CODEC outputs the secondary FS. * The SIOF transmits or receives (stores in SIRCDR) control data (data specified by SITCDR) synchronously with the secondary FS. Figure 15.8 shows an example of the control data interface timing by the secondary FS. Rev. 1.00, 02/04, page 416 of 804 1 frame 1/2 frame 1/2 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD L-channel data Normal FS Secondary FS Normal FS Slot No.0 LSB=1 (Secondary FS request) REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, Control channel 0 Slot No.0 FL[3:0]=1110 (Frame length: 128 bits), TDRA[3:0]=0000, TDRE=0, RDRA[3:0]=0000, RDRE=0, CD1A[3:0]=0000 CD1E=0, Specifications: TRMD[1:0]=01, TDLE=1, RDLE=1, CD0E=1, Figure 15.8 Control Data Interface (Secondary FS) 15.4.6 FIFO Overview: The transmit and receive FIFOs of the SIOF have the following features. * 16-stage 32-bit FIFOs for transmission and reception * The FIFO pointer can be updated in one read or write cycle regardless of access size of the CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.) Transfer Request: The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt sources. * FIFO transmit request: TDREQ (transmit interrupt source) * FIFO receive request: RDREQ (receive interrupt source) The request conditions for FIFO transmit or receive can be specified individually. The request conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 15.9 and 15.10 summarize the conditions specified by SIFCTR. Table 15.9 Conditions to Issue Transmit Request TFWM2 to TFWM0 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Transmit Request Empty area is 16 stages Empty area is 12 stages or more Empty area is 8 stages or more Empty area is 4 stages or more Empty area is 1 stage or more Largest Used Areas Smallest Rev. 1.00, 02/04, page 417 of 804 Table 15.10 Conditions to Issue Receive Request RFWM2 to RFWM0 000 100 101 110 111 Number of Requested Stages 1 4 8 12 16 Receive Request Valid data is 1 stage or more Valid data is 4 stages or more Valid data is 8 stages or more Valid data is 12 stages or more Valid data is 16 stages Largest Used Areas Smallest The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled when the above condition is not satisfied even if the FIFO is not empty or full. Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by the following register. * Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits in SIFCTR. * Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in SIFCTR. The above indicate possible data numbers that can be transferred by the CPU or DMAC. Rev. 1.00, 02/04, page 418 of 804 15.4.7 Transmit and Receive Procedures Transmission in Master Mode: Figure 15.9 shows an example of settings and operation for master mode transmission. No. Flow Chart Start SIOF Settings SIOF Operation 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value 2 Set the SCKE bit in SICTR to 1 Set operation start for baud rate generator 3 Start SIOFSCK output Output serial clock 4 Set the FSE and TXE bits in SICTR to 1 frame synchronous Set the start for frame synchronous Outputand issue transmit signal signal output and enable transfer request* transmission 5 TDREQ = 1? Yes No 6 Set SITDR Set transmit data 7 Transmit SITDR from SIOFTXD synchronously with SIOFSYNC Transmit Transfer ended? 8 Yes No Set to disable transmission End transmission Clear the TXE bit in SICTR to 0 End Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the TXE bit should be set to 1. Figure 15.9 Example of Transmit Operation in Master Mode Rev. 1.00, 02/04, page 419 of 804 Reception in Master Mode: Figure 15.10 shows an example of settings and operation for master mode reception. No. Flow Chart Start 1 SIOF Settings SIOF Operation Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value Set operation start for baud rate generator 2 Set the SCKE bit in SICTR to 1 3 Start SIOFSCK output Output serial clock 4 Set the FSE and RXE bits in SICTR to 1 Set the start for frame synchronous Output frame synchronous signal output and enable signal reception 5 Store SIOFRXD receive data in SIRDR synchronously with SIOFSYNC Issue receive transfer request according to the receive FIFO threshold value 6 RDREQ = 1? Yes No Reception 7 Read SIRDR Read receive data Transfer ended? 8 Yes No Set to disable reception End reception Clear the RXE bit in SICTR to 0 End Figure 15.10 Example of Receive Operation in Master Mode Rev. 1.00, 02/04, page 420 of 804 Transmission in Slave Mode: Figure 15.11 shows an example of settings and operation for slave mode transmission. No. Flow Chart Start 1 Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value SIOF Settings SIOF Operation Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR 2 Set the TXE bit in SICTR to 1 Set to enable transmission Issue transmit transfer request to enable transmission when frame synchronous signal is input 3 TDREQ = 1? Yes No 4 Set SITDR Set transmit data 5 Transmit SITDR from SIOFTXD synchronously with SIOFSYNC Transmit Transfer ended? Yes 6 No Set to disable transmission End transmission Clear the TXE bit in SICTR to 0 End Figure 15.11 Example of Transmit Operation in Slave Mode Rev. 1.00, 02/04, page 421 of 804 Reception in Slave Mode: Figure 15.12 shows an example of settings and operation for slave mode reception. No. Flow Chart Start 1 Set SIMDR, SISCR, SITDAR, SIRDAR, SICDAR, and SIFCTR SIOF Settings SIOF Operation Set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and FIFO request threshold value Set to enable reception Enable reception when the frame synchronous signal is input Issue receive transfer request according to the receive FIFO threshold value 2 Set the RXE bit in SICTR to 1 3 Store SIOFRXD receive data in SIRDR synchronously with SIOFSYNC 4 RDREQ = 1? Yes No Reception 5 Read SIRDR Read receive data Transfer ended? 6 Yes No Set to disable reception End reception Clear the RXE bit in SICTR to 0 End Figure 15.12 Example of Receive Operation in Slave Mode Rev. 1.00, 02/04, page 422 of 804 Transmit/Receive Reset: The SIOF can separately reset the transmit and receive units by setting the following bits to 1. * Transmit reset: TXRST bit in SICTR * Receive reset: RXRST bit in SICTR Table 15.11 shows the details of initialization upon transmit or receive reset. Table 15.11 Transmit and Receive Reset Type Transmit reset Objects Initialized SITDR Transmit FIFO write pointer TCRDY, TFEMP, and TDREQ bits in SISTR TXE bit in SICTR Receive reset SIRDR Receive FIFO read pointer RCRDY, RFFUL, and RDREQ bits in SISTR RXE bit in SICTR Module Stop Mode: The SIOF stops the transmit/receive operation in module stop mode. Then the following contents are initialized. * * * * * * SITDR SITCR Read pointer of receive FIFO Write pointer of transmit FIFO SISTR SICTR Rev. 1.00, 02/04, page 423 of 804 15.4.8 Interrupts The SIOF has one type of interrupt. Interrupt Sources: Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR. Table 15.12 lists the SIOF interrupt sources. Table 15.12 SIOF Interrupt Sources No. Classification 1 2 3 4 5 6 7 8 Error Control Reception Transmission Bit Name TDREQ TFEMP RDREQ RFFUL TCRDY RCRDY TFUDF TFOVF Function Name Description Transmit FIFO transfer The transmit FIFO stores data of request specified size or more. Transmit FIFO empty Receive FIFO transfer request Receive FIFO full Transmit control data ready Receive control data ready Transmit FIFO underflow The transmit FIFO is empty. The receive FIFO stores data of specified size or more. The receive FIFO is full. The transmit control register is ready to be written. The receive control data register stores valid data. Serial data transmit timing has arrived while the transmit FIFO is empty. Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full. Receive FIFO overflow Serial data is received while the receive FIFO is full. Receive FIFO underflow FS error The receive FIFO is read while the receive FIFO is empty. A synchronous signal is input before the specified bit number has been passed (in slave mode). The same slot is specified in both serial data and control data. 9 10 11 RFOVF RFUDF FSERR 12 SAERR Slot assign error Whether an interrupt is issued or not as the result of an interrupt source is determined by the SIIER settings. If an interrupt source is set to 1 and the corresponding bit in SIIER is set to 1, an SIOF interrupt issued. Rev. 1.00, 02/04, page 424 of 804 Regarding Transmit and Receive Classification: The transmit sources and receive sources are signals indicating the state; after being set, if the state changes, they are automatically cleared by the SIOF. When the DMA transfer is used, a DMA transfer request is pulled low (0 level) for one cycle at the end of DMA transfer. Processing when Errors Occur: On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the following operations. * Transmit FIFO underflow (TFUDF) The immediately preceding transmit data is again transmitted. * Transmit FIFO overflow (TFOVF) The contents of the transmit FIFO are protected, and the write operation causing the overflow is ignored. * Receive FIFO overflow (RFOVF) Data causing the overflow is discarded and lost. * Receive FIFO underflow (RFUDF) An undefined value is output on the bus. * FS error (FSERR) The internal counter is reset according to the FSYN signal in which an error occurs. * Slot assign error (SAERR) If the same slot is assigned to both serial data and control data, the slot is assigned to serial data. If the same slot is assigned to two control data items, data cannot be transferred correctly. Rev. 1.00, 02/04, page 425 of 804 15.4.9 Transmit and Receive Timing Examples of the SIOF serial transmission and reception are shown in figure 15.13 through figure 15.20. 8-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, a frame length = 8 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD L-channel data SIOFRXD Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=0, REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=0000 (frame length: 8 bits) TDRE=0, TDRA[3:0]=0000, RDRE=0, RDRA[3:0]=0000, CD1E=0, CD1A[3:0]=0000 Figure 15.13 Transmit and Receive Timing (8-Bit Monaural Data (1)) 8-bit Monaural Data (2): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 16 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD L-channel data SIOFRXD Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=0, REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=0100 (frame length: 16 bits) TDRE=0, TDRA[3:0]=0000, RDRE=0, RDRA[3:0]=0000, CD1E=0, CD1A[3:0]=0000 Slot No.1 Figure 15.14 Transmit and Receive Timing (8-Bit Monaural Data (2)) Rev. 1.00, 02/04, page 426 of 804 16-bit Monaural Data (1): Synchronous pulse method, falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 64 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD L-channel data Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=0, REDG=0, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=1101 (frame length: 64 bits) TDRA[3:0]=0000, TDRE=0, RDRA[3:0]=0000, RDRE=0, CD1A[3:0]=0000 CD1E=0, Slot No.1 Slot No.2 Slot No.3 Figure 15.15 Transmit and Receive Timing (16-Bit Monaural Data (1)) 16-bit Stereo Data (1): L/R method, rising edge sampling, slot No.0 used for left channel data, slot No.1 used for right channel data, and frame length = 32 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD L-channel data SIOFRXD No bit delay Specifications: TRMD[1:0]=11, TDLE=1, RDLE=1, CD0E=0, REDG=1, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0000, FL[3:0]=1100 (frame length: 32 bits) TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, CD1A[3:0]=0000 CD1E=0, Slot No.0 R-channel data Slot No.1 Figure 15.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) Rev. 1.00, 02/04, page 427 of 804 16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for right-channel receive data, and frame length = 64 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD L-channel data R-channel data SIOFRXD Slot No.0 No bit delay L-channel data Slot No.1 Slot No.2 R-channel data Slot No.3 Specifications: TRMD[1:0]=01, TDLE=1, RDLE=1, CD0E=0, REDG=1, TDLA[3:0]=0000, RDLA[3:0]=0001, CD0A[3:0]=0000, FL[3:0]=1101 (frame length: 64 bits), TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0011, RDRE=1, CD1A[3:0]=0000 CD1E=0, Figure 15.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) 16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for leftchannel data, slot No.1 used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD L-channel data R-channel data Slot No.0 Slot No.1 Control Control channel 0 channel 1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 1 bit delay Specifications: TRMD[1:0]=00 or 10,REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, CD0A[3:0]=0010, CD0E=1, FL[3:0]=1110 (frame length: 128 bits), TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, CD1A[3:0]=0011 CD1E=1, Figure 15.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) Rev. 1.00, 02/04, page 428 of 804 16-bit Stereo Data (4): Synchronous pulse method, falling edge sampling, slot No.0 used for leftchannel data, slot No.2 used for right-channel data, slot No.1 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD L-channel data R-channel Control Control data channel 0 channel 1 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.0 Slot No.5 Slot No.6 Slot No.7 1 bit delay Specifications: TRMD[1:0]=00 or 10, TDLE=1, RDLE=1, CD0E=1, REDG=1, TDLA[3:0]=0000, RDLA[3:0]=0000, CD0A[3:0]=0001, FL[3:0]=1110 (frame length: 128 bits) TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0010, RDRE=1, CD1A[3:0]=0011 CD1E=1, Figure 15.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1): Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1 used for rightchannel data, slot No.2 used for control channel 0 data, slot No.3 used for control channel 1 data, and frame length = 128 bits In this mode, valid data must be set to slot No. 0. 1 frame SIOFSCK SIOFSYNC SIOFTXD SIOFRXD L-channel data R-channel data Slot No.0 Slot No.1 Control channel 0 Slot No.2 Control channel 1 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 Specifications: TRMD[1:0]=00 or 10,REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, CD0A[3:0]=0010, CD0E=1, FL[3:0]=1110 (frame length: 128 bits), TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, CD1A[3:0]=0011 CD1E=1, Figure 15.20 Transmit and Receive Timing (16-Bit Stereo Data) Rev. 1.00, 02/04, page 429 of 804 15.4.10 SPI Mode SPI-mode operation is selected for the SIOF by the setting in SPICR. Example of Configuration: Figure 15.21 shows an example of the configuration for SPI-mode communications. Master SPI Transmit FIFO P/S MOSI Slave 0 SPI Receive FIFO S/P MISO SS0 SS Baud rate generator SCK Figure 15.21 Example of Configuration in SPI Mode SPI Operation: The states of operation in SPI mode are described in terms of transmission and reception in table 15.13. In SPI mode, the data length is fixed to 8 bits and the values of the upper 8 bits of SITDR and SIRDR are the valid data for transmission and reception, respectively. 31 SITDR/SIRDR Data 24 23 0 The shaded part is the data which is transmitted or received. The only sources of interrupts that should be enabled in SPI-mode transfer are transmit data transfer request (TDREQ), transmit FIFO empty (TFEMP), receive-data transfer request (RDREQ), receive-FIFO full (RFFUL), and receive-FIFO overflow (RFOVF). Enabled or disabled states are selectable by the interrupt enable register (SIIER). Interrupts from other sources must be disabled at all times. For the DMA transfer requests, the enabled sources are transmit-data DMA transfer request (TDMA) and receive-data DMA transfer request (RDMA). Enabled or disabled states are selectable by the interrupt enable register (SIIER). In SPI mode, the baud rate is set by SISCR. Rev. 1.00, 02/04, page 430 of 804 Table 15.13 States of Transmit and Receive Operations in SPI Mode TXE 0 0 RXE 0 1 TDMAE Don't care 0 RDMAE Don't care 1 SPI Transmit/Receive Operation Transmission/reception is disabled Half-Duplex Reception The transmit FIFO does not operate and dummy data is transmitted from the MOSI. Data received at the MISO is stored in the receive FIFO and is transferred by using the DMA. Receive operation continues as long as RE bit = 1; the receive-FIFO overflow (RFOVF) status is set after the receive FIFO has become full and further receive data is ignored. 1 0 0 0 Half-Duplex Transmission The data in the transmit FIFO is transmitted from the MOSI. The receive FIFO does not operate, and data on the MISO is ignored. When the transmit FIFO becomes empty, the transmit operation is completed. 1 0 Half-Duplex Transmission The data which has been transferred by using the DMA to the transmit FIFO is transmitted from the MOSI. The receive FIFO does not operate and data on the MISO is ignored. When the transmit FIFO becomes empty, the transmit operation is completed. 1 1 0 0 Full-Duplex Communication The transmit and receive FIFOs operate at the same time. Data in the transmit FIFO are transmitted or received. When there is no data left in the transmit FIFO, the transmit and receive operations are completed. Note: In SPI mode, settings other than the above are prohibited. In half-duplex reception (transmission is disabled), the value output from the MOSI can be controlled by the TXDIZ bit in SIMDR as follows. TXDIZ = 0: Transmission is disabled, 1 is output on the MOSI. TXDIZ = 1: Transmission is disabled, the MOSI is in the high-impedance state. Rev. 1.00, 02/04, page 431 of 804 Serial Clock Timing: Timing on the data and clock lines in SPI mode is shown in figures 15.22 and 15.23. The user can select from four serial transfer formats, which differ according to the phase and polarity of the serial clock. SCK (CPOL = 0) (CPOL = 1) Sampling MISO/MOSI SSn Ts Th Td MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ts: The setup time for the SCK edge. The minimum value is 1/2 of the period of the SCK. The setting is made by the SSAST1 and SSAST0 bits in SPICR. Th: The hold time for the SCK edge. The minimum value is 0. Td: The idle time. A number of SCK-clock cycles from 0 to 3 is set by the FLD1 and FLD0 bits in SPICR. Figure 15.22 SPI Data/Clock Timing 1 (CPHA = 0) SCK (CPOL = 0) (CPOL = 1) Sampling MISO/MOSI SSn Ts Th Td MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ts: The setup time for the SCK edge. The minimum value is 0. The setting is made by the SSAST1 and SSAST0 bits in SPICR. Th: The hold time for the SCK edge. The minimum value is 1/2 of the period of the SCK. Td: The idle time. A number of SCK-clock cycles from 0 to 3 is set by the FLD1 and FLD0 bits in SPICR. Figure 15.23 SPI Data/Clock Timing 2 (CPHA = 1) Rev. 1.00, 02/04, page 432 of 804 15.5 Usage Notes 1. The transitions to the software standby mode and module standby mode should not be made by setting the module standby bit of the SIOF during data reception and transmission. The transitions to software standby mode and module standby mode should be made after both TXE and RXE bits in the SICTR register have been cleared (transmission/reception disabled). 2. The SIOFTXD pin in SIOF is output pin even when the TXE bit is cleared. The SIOFRXD pin is in the input enabled state even when the RXE bit is cleared. In software standby mode, the SIOFTXD pin is high-impedance and the SIOFRXD pin is fixed to input disable state. Note that the SIOFTXD pin is multiplexed with the port PTA1 and its initial settings after a poweron reset are an input pin and the pull-up MOS is on. The SIOFRXD pin is multiplexed with the port PTA2, and the initial settings after a power-on reset are an input pin and the pull-up MOS is on. Care is required on dealing the signal lines that are connected to the SIOFTXD and SIOFRXD pins. 3. The SIOF has some 32-bit registers that handle two pieces of independent 16-bit data. Note that the order of upper word and lower word on the memory may be switched within the register in a data transfer with above registers when switching the big endian and little endian by using the MD5 pin. 4. When the SIOF is set as a transfer destination or transfer source, a transfer is carried out only in longword units. Rev. 1.00, 02/04, page 433 of 804 Rev. 1.00, 02/04, page 434 of 804 Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has a two-channel serial communication interface with on-chip FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous and clock synchronous serial communication. 64-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1 Features * Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of eight serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none LSB-first transfer Receive error detection: Parity, framing, and overrun errors Break detection: If a framing error is followed by at least one frame at the space "0" (low) level, a break is detected. * Clock synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. Data length: 8 bits LSB-first transfer * Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception. * On-chip baud rate generator allows any bit rate to be selected. * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin. SCIS3C2B_010020030200 Rev. 1.00, 02/04, page 435 of 804 * Six interrupt sources in asynchronous mode There are six interrupt sourcestransmit-data-stop, transmit-FIFO-data-empty, receive-FIFOdata-full, receive-error (framing/parity error), break-receive, and receive-data-ready interrupts. The vectors of each interrupt are the same. * Two interrupt sources in clock synchronous mode There are two interrupt sourcestransmit-FIFO-data-empty and receive-FIFO-data-full interrupts. The vectors of each interrupt are the same. * The DMA controller (DMAC) can be activated to execute a data transfer in the event of a transmit-FIFO-data-empty, transmit-data-stop, or receive-FIFO-data-full interrupt. The DMAC requests of transmit-FIFO-data-empty and transmit-data-stop interrupts are the same. * On-chip modem control functions (CTS and RTS) * On-chip transmit-data-stop functions (only in asynchronous mode) * When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. * The amount of data in the transmit/receive FIFO registers and the number of receive errors in the receive data in the receive FIFO register can be ascertained. Rev. 1.00, 02/04, page 436 of 804 Figure 16.1 shows a block diagram of the SCIF. Bus interface Module data bus Peripheral bus SCFRDR (64-stage) SCFTDR (64-stage) RxD SCRSR SCTSR SCFDR SCFCR SCFER SCSSR SCSCR SCSMR SCTDSR Transmission/ reception control Clock SCBRR Baud rate generator P P/4 P/16 P/64 Parity generation Parity check SCK TxD CTS RTS External clock SCIF interrupt SCIF SCIF4 Note: SCRSR: SCFRDR: SCTSR: SCFTDR: SCSMR: SCSCR: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFER: SCSSR: SCBRR: SCFCR: SCFDR: SCTDSR: FIFO error count register Serial status register Bit rate register FIFO control register FIFO data count register Transit data stop register Figure 16.1 Block Diagram of SCIF Rev. 1.00, 02/04, page 437 of 804 16.2 Input/Output Pins Table 16.1 shows the SCIF pin configuration. Table 16.1 Pin Configuration Channel Pin Name 0 SCIF0_SCK SCIF0_RxD SCIF0_TxD SCIF0_CTS SCIF0_RTS 1 SCIF1_SCK SCIF1_RxD SCIF1_TxD SCIF1_CTS SCIF1_RTS Abbreviation*1 I/O SCK RxD*2 TxD* CTS RTS SCK RxD* TxD* CTS RTS 2 2 Function Input/output Serial clock pin Clock input/output Input Output Input Output Receive data pin Receive data input Transmit data pin Transmit data output Modem control pin Transmission possible Modem control pin Transmit request Input/output Serial clock pin Clock input/output Input Output Input Output Receive data pin Receive data input 2 Transmit data pin Transmit data output Modem control pin Transmission possible Modem control pin Transmit request Notes: 1. The pins are collectively called SCK, RxD, TxD, CTS, and RTS without channel number in the following descriptions. 2. These pins are made to function as serial pins by setting SCIF operation with the TE and RE bits in SCSCR. Rev. 1.00, 02/04, page 438 of 804 16.3 Register Descriptions The SCIF has the following internal registers. For details on register addresses and register states in each processing state, refer to section 27, List of Registers. Channel 0: * * * * * * * * * * Serial mode register_0 (SCSMR_0) Bit rate register_0 (SCBRR_0) Serial control register_0 (SCSCR_0) Transmit data stop register_0 (SCTDSR_0) FIFO error count register_0 (SCFER_0) Serial status register_0 (SCSSR_0) FIFO control register_0 (SCFCR_0) FIFO data count register_0 (SCFDR_0) Transmit FIFO data register_0 (SCFTDR_0) Receive FIFO data register_0 (SCFRDR_0) Channel 1: * * * * * * * * * * Serial mode register_1 (SCSMR_1) Bit rate register_1 (SCBRR_1) Serial control register_1 (SCSCR_1) Transmit data stop register_1 (SCTDSR_1) FIFO error count register_1 (SCFER_1) Serial status register_1 (SCSSR_1) FIFO control register _1(SCFCR_1) FIFO data count register_1 (SCFDR_1) Transmit FIFO data register_1 (SCFTDR_1) Receive FIFO data register_1 (SCFRDR_1) Rev. 1.00, 02/04, page 439 of 804 16.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive serial data. The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO data register, SCFRDR, automatically. SCRSR cannot be directly read or written to by the CPU. 16.3.2 Receive FIFO Data Register (SCFRDR) SCFRDR is a 64-stage 8-bit FIFO register that stores received serial data (receive FIFO). When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO data register is full (64 data bytes). SCFRDR is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO data register, an undefined value will be returned. When the receive FIFO data register is full of receive data, subsequent serial data is lost. Bit 7 to 0 Bit Name Initial Value R/W Description Serial Receive Data FIFO SCFRD7 to SCFRD0 Undefined R 16.3.3 Transmit Shift Register (SCTSR) SCTSR is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data sequentially to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission is started automatically. SCTSR cannot be directly read or written to by the CPU. Rev. 1.00, 02/04, page 440 of 804 16.3.4 Transmit FIFO Data Register (SCFTDR) SCFTDR is an 8-bit 64-stage FIFO data register that stores data for serial transmission (transmit FIFO). If SCTSR is empty when transmit data is written to SCFTDR, the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. SCFTDR is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR is filled with 64 bytes of transmit data. Data written in this case is ignored. Bit 7 to 0 Bit Name SCFTD7 to SCFTD0 Initial Value R/W Description Serial Transmit Data FIFO Undefined W Rev. 1.00, 02/04, page 441 of 804 16.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit readable/writable register used to set the SCIF's serial transfer format and select the baud rate generator clock source and the sampling rate. Bit 15 to 11 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. SRC2 SRC1 SRC0 0 0 0 R/W R/W R/W Sampling Control Select the sampling rate in asynchronous mode. This setting is valid only in asynchronous mode. 000: Sampling rate 1/16 001: Sampling rate 1/5 010: Sampling rate 1/7 011: Sampling rate 1/11 100: Sampling rate 1/13 101: Sampling rate 1/17 110: Sampling rate 1/19 111: Sampling rate 1/27 7 C/A 0 R/W Communication Mode Selects whether the SCI operates in the asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length Selects seven or eight bits as the data length. This setting is only valid in asynchronous mode. In clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When the 7-bit data is selected, the MSB bit (bit 7) in the transmit FIFO data register (SCFTDR) is not transmitted. 10 9 8 Rev. 1.00, 02/04, page 442 of 804 Bit 5 Bit Name PE Initial Value 0 R/W R/W Description Parity Enable Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. This setting is only valid in asynchronous mode. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE setting. 0: Parity bit addition and checking disabled 1: Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. 4 O/E 0 R/W Parity Mode Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. The O/E bit setting is invalid when parity addition and checking is disabled in asynchronous and clock synchronous mode. 0: Even parity* 1: Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. 1 Rev. 1.00, 02/04, page 443 of 804 Bit 3 Bit Name STOP Initial Value 0 R/W R/W Description Stop Bit Length Selects one or two bits as the stop bit length. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. This setting is only valid in asynchronous mode. In clock synchronous mode, this setting is invalid since stop bits are not added. 0: One stop bit* 1 2 1: Two stop bits* Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. 2 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select Select the clock source for the on-chip baud rate generator. 00: P 01: P/4 10: P/16 11: P/64 Rev. 1.00, 02/04, page 444 of 804 16.3.6 Serial Control Register (SCSCR) SCSCR is a 16-bit readable/writable register that enables or disables the SCIF transfer operations and interrupt requests, and selects the serial clock source. Bit 15 Bit Name TDRQE Initial Value 0 R/W R/W Description Transmit Data Transmission Request Enable When transmitting data while TIE = 1 and transmit FIFO data empty has been generated, transmit FIFO data empty interrupt or DMA transfer request is selected. 0: Interrupt request to CPU is performed 1: Transmit data transmission request to the DMA is performed 14 RDRQE 0 R/W Receive Data Transmission Request Enable When receiving data while RIE = 1 and received FIFO data full is generated, received FIFO data full interrupt or DMA transfer request is selected. 0: Interrupt request to CPU is performed 1: Transmit data transmission request to the DMA is performed 13, 12 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 11 TSIE 0 R/W Transmit Data Stop Interrupt Enable Enables or disables generation of a transmit-data-stop interrupt when the TSE bit in SCFCR is enabled and the TSF flag in SCSSR is set to 1. 0: Transmit-data-stop interrupt disabled* 1: Transmit-data-stop interrupt enabled Note: * The interrupt request is cleared by clearing the TSF flag to 0 after reading 1 from it or clearing the TSIE bit to 0. Rev. 1.00, 02/04, page 445 of 804 Bit 10 Bit Name ERIE Initial Value 0 R/W R/W Description Receive Error Interrupt Enable Enables or disables generation of a receive-error (framing or parity error) interrupt when the ER flag in SCSSR is set to 1. 0: Receive-error interrupt disabled* 1: Receive-error interrupt enabled Note: * The interrupt request is cleared by clearing the ER flag to 0 after reading 1 from it or clearing the ERIE bit to 0. 9 BRIE 0 R/W Break Interrupt Enable Enables or disables generation of a break-receive interrupt when the BRK flag in SCSSR is set to 1. 0: Break-receive interrupt disabled* 1: Break-receive interrupt enabled Note: * The interrupt request is cleared by clearing the BRK flag to 0 after reading 1 from it or clearing the BRIE bit to 0. 8 DRIE 0 R/W Receive Data Ready Interrupt Enable Enables or disables generation of a receive-data-ready interrupt when the DR flag in SCSSR is set to 1. 0: Receive-data-ready interrupt disabled* 1: Receive-data-ready interrupt enabled Note: * The interrupt request is cleared by clearing the DR flag to 0 after reading 1 from it or clearing the DRIE bit to 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables generation of a transmit-FIFO-data-empty interrupt request when the TDFE flag in SCSSR is set to 1. 0: Transmit-FIFO-data-empty interrupt request disabled* 1: Transmit-FIFO-data-empty interrupt request enabled Note: * The interrupt request is cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or clearing the TIE bit to 0. Rev. 1.00, 02/04, page 446 of 804 Bit 6 Bit Name RIE Initial Value 0 R/W R/W Description Receive Interrupt Enable Enables or disables generation of a receive-FIFO-data-full interrupt request when the RDF flag in SCSSR is set to 1. 0: Receive-FIFO-data-full interrupt request disabled* 1: Receive-FIFO-data-full interrupt request enabled Note: * The interrupt requests is cleared by reading 1 from the RDF flag, then clearing the flag to 0, or clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable Enables or disables the start of serial transmission by the SCIF. 0: Transmission disabled 1: Transmission enabled* Note: * The serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be made, the transmit format decided, and the transmit FIFO reset, before the TE bit is set to 1. If settings of above registers are changed with the TE bit enabled, the operation cannot be guaranteed. 4 RE 0 R/W Receive Enable Enables or disables the start of serial reception by the SCIF. 0: Reception disabled*1 1: Reception enabled* Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their state. 2. The serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be made, the receive format decided, and the receive FIFO reset, before the RE bit is set to 1. If settings of above registers are changed with the RE bit enabled, the operation cannot be guaranteed. 2 3, 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 447 of 804 Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable Select the SCIF clock source. The CKE1 and CKE0 bits must be set before determining the SCIF operating mode with SCSMR. 00: Internal clock/SCK pin functions as input pin (input signal ignored) 01: Internal clock/SCK pin functions as serial clock output* 10: External clock/SCK pin functions as clock input* 11: External clock/SCK pin functions as clock input* 2 2 1 When data is sampled by the on-chip baud rate generator, set bits CKE1 and CKE0 to B'00 (internal clock/SCK pin functions as input pin (input signal ignored)). When using the SCK pin as a port, set bits CKE1 and CKE0 to B'00. Notes: 1. In synchronous mode, a clock with a frequency equal to the bit rate is output. 2. In asynchronous mode, a clock with a sampling rate should be input. For example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate should be input. When an external clock is not input, set bits CKE1 and CKE0 to B'00 or B'01. Rev. 1.00, 02/04, page 448 of 804 16.3.7 FIFO Error Count Register (SCFER) SCFER is a 16-bit read-only register that indicates the number of receive errors (framing or parity error). Bit Bit Name Initial Value All 0 0 0 0 0 0 0 All 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R Description Reserved These bits are always read as 0. 13 12 11 10 9 8 7, 6 5 4 3 2 1 0 PER5 PER4 PER3 PER2 PER1 PER0 FER5 FER4 FER3 FER2 FER1 FER0 Parity Error Count Indicates the number of data, in which parity errors are generated, in receive data stored in the receive FIFO data register (SCFRDR) in asynchronous mode. After setting the ER bit in SCSSR, the value of bits 13 to 8 indicates the number of parity error generated data. When all 64 bytes of receive data in SCFRDR have parity errors, the PER5 to PER0 bits indicate 0. Reserved These bits are always read as 0. Framing Error Count Indicates the number of data, in which framing errors are generated, in receive data stored in the receive FIFO data register (SCFRDR) in asynchronous mode. After setting the ER bit in SCSSR, the value of bits 5 to 0 indicates the number of framing error generated data. When all 64 bytes of receive data in SCFRDR have framing errors, the FER5 to FER0 bits indicate 0. 15, 14 Rev. 1.00, 02/04, page 449 of 804 16.3.8 Serial Status Register (SCSSR) SCSSR is a 16-bit readable/writable register that indicates the SCIF status. However, 1 cannot be written to the ORER, TSF, ER, TDFE, BRK, RDF, and DR flags. Also note that in order to clear these flags to 0, they must be read as 1 beforehand. The TEND, FER, and PER flags are read-only flags and cannot be modified. Bit Initial Bit Name Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 9 ORER 0 R/(W)* Overrun Error Flag Indicates that an overrun error occurred during reception. This bit is only valid in asynchronous mode. 0: Reception in progress, or reception has ended 1 successfully* [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ORER after reading ORER = 1 15 to 10 1: An overrun error occurred during reception*2 [Setting condition] When serial reception is completed while receive FIFO is full Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Rev. 1.00, 02/04, page 450 of 804 Bit 8 Bit Name TSF Initial Value R/W 0 Description R/(W)* Transmit Data Stop Flag Indicates that the number of transmit data matches the value of SCTDSR. 0: Number of transmit data does not match the value of SCTDSR [Clearing conditions] * * Power-on reset or manual reset When 0 is written to TSF after reading TSF = 1 1: Number of transmit data matches the value of SCTDSR 7 ER 0 R/(W)* Receive Error Indicates that a framing error or parity error occurred during 1 reception in asynchronous mode.* 0: No framing error or parity error occurred during reception [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ER after reading ER = 1 1: A framing error or parity error occurred during reception [Setting conditions] * When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit 2 is 0* * When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR, and reception continues. The FER and PER bits in SCSSR can be used to determine whether there is a receive error in the data read from SCFRDR. 2. When the stop length is two bits, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Rev. 1.00, 02/04, page 451 of 804 Bit 6 Bit Name TEND Initial Value R/W 1 R Description Transmit End Indicates that there is no valid data in SCFTDR when the last bit of the transmit character is sent, and transmission has been ended. 0: Transmission is in progress [Clearing condition] When data is written to SCFTDR 1: Transmission has been ended [Setting condition] When there is no transmit data in SCFTDR on transmission of a 1-byte serial transmit character 5 TDFE 1 R/(W)* Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR), and new transmit data can be written to SCFTDR. 0: A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing condition] When transmit data exceeding the transmit trigger set number is written to SCFTDR, and 0 is written to TDFE after reading TDFE = 1 1: The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number [Setting conditions] * * Power-on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger set number as the result of a 1 transmit operation* Note: 1. As SCFTDR is a 64-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 64 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR is indicated by SCFDR. Rev. 1.00, 02/04, page 452 of 804 Bit 4 Bit Name BRK Initial Value R/W 0 R/(W)* Description Break Detect Indicates that a receive data break signal has been detected in asynchronous mode. 0: A break signal has not been received [Clearing conditions] * Power-on reset or manual reset * When 0 is written to BRK after reading BRK = 1 1 1: A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space 0 level (low level) for at least one frame length Note: 1. When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR. When the break ends and the receive signal returns to mark 1, receive data transfer is resumed. 3 FER 0 R Framing Error Indicates a framing error in the data read from SCFRDR in asynchronous mode. 0: There is no framing error in the receive data read from SCFRDR [Clearing conditions] * Power-on reset or manual reset * When there is no framing error in SCFRDR read data 1: There is a framing error in the receive data read from SCFRDR [Setting condition] When there is a framing error in SCFRDR read data Rev. 1.00, 02/04, page 453 of 804 Bit 2 Bit Name PER Initial Value R/W 0 R Description Parity Error Indicates a parity error in the data read from SCFRDR in asynchronous mode. 0: There is no parity error in the receive data read from SCFRDR [Clearing conditions] * Power-on reset or manual reset * When there is no parity error in SCFRDR read data 1: There is a parity error in the receive data read from SCFRDR [Setting condition] When there is a parity error in SCFRDR read data 1 RDF 0 R/(W)* Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). 0: The number of receive data bytes in SCFRDR is less than the receive trigger set number [Clearing conditions] * * Power-on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number, and 0 is written to RDF after reading RDF = 1 1: The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR contains at least the receive trigger set 1 number of receive data bytes* Note:1. SCFRDR is a 64-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If data is read when SCFRDR is empty, an undefined value will be returned. The number of receive data bytes in SCFRDR is indicated by the lower bits of SCFDR. Rev. 1.00, 02/04, page 454 of 804 Bit 0 Bit Name DR Initial Value R/W 0 Description R/(W)* Receive Data Ready Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR and no further data will arrive in asynchronous mode. 0: Reception is in progress or has ended successfully and there is no receive data left in SCFRDR [Clearing conditions] * * Power-on reset or manual reset When all the receive data in SCFRDR has been read, and 0 is written to DR after reading DR = 1 1: No further receive data has arrived [Setting condition] When SCFRDR contains fewer than the receive trigger set number of receive data bytes and no further data 1 will arrive.* Note: 1. The DR bit is set 15etu after the last data is received at a sampling rate of 1/16 regardless of the setting of the sampling control bits in SCSMR. etu: Elementary time unit (time for transfer of one bit) Note: * Only 0 can be written for clearing the flags. Rev. 1.00, 02/04, page 455 of 804 16.3.9 Bit Rate Register (SCBRR) SCBRR is an 8-bit readable/writable register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. Bit Bit Name Initial Value H'FF R/W R/W Description Bit Rate Setting 7 to 0 SCBRD7 to SCBRD0 The SCBRR setting is found from the following equation. Asynchronous Mode: 1. When sampling rate is 1/16 N= P 32 x 22n-1 x B x 106 - 1 2. When sampling rate is 1/5 N= P 10 x 22n-1 x B x 106 - 1 3. When sampling rate is 1/11 N= P 22 x 22n-1 x B x 106 - 1 4. When sampling rate is 1/13 N= P 26 x 22n-1 x B x 106 - 1 5. When sampling rate is 1/27 N= P 54 x 22n-1 x B x 106 - 1 Rev. 1.00, 02/04, page 456 of 804 Clock Synchronous Mode: N= P 4 x 22n-1 x B x 106 - 1 Where B: N: P: n: Bit rate (bits/s) SCBRR setting for baud rate generator Asynchronous mode: 0 N 255 Clock synchronous mode: 1 N 255 Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR Setting n 0 1 2 3 Clock P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following equation: 1. When sampling rate is 1/16 Error (%) = P x 106 - 1 x 100 (1+N) x B x 32 x 22n-1 2. When sampling rate is 1/5 Error (%) = P x 106 - 1 x 100 (1+N) x B x 10 x 22n-1 3. When sampling rate is 1/11 Error (%) = P x 106 - 1 x 100 (1+N) x B x 22 x 22n-1 4. When sampling rate is 1/13 Error (%) = P x 106 (1+N) x B x 26 x 22n-1 - 1 x 100 Rev. 1.00, 02/04, page 457 of 804 5. When sampling rate is 1/27 Error (%) = P x 106 - 1 x 100 (1+N) x B x 54 x 22n-1 16.3.10 FIFO Control Register (SCFCR) SCFCR is a 16-bit readable/writable register that resets the data count and sets the trigger data number for the transmit and receive FIFO registers, and also contains a loopback test enable bit. Bit 15 Bit Name TSE Initial Value 0 R/W R/W Description Transmit Data Stop Enable Enables or disables the transmit data stop function. This function is enabled only in asynchronous mode. Since this function is not supported in clock synchronous mode, clear this bit to 0 in clock synchronous mode. 0: Transmit data stop function disabled 1: Transmit data stop function enabled 14 TCRST 0 R/W Transmit Count Reset Clears the transmit count to 0. This bit is valid only when the transmit data stop function is used. 0: Transmit count reset disabled* 1: Transmit count reset enabled (clearing to 0) Note:* The transmit count is reset (clearing to 0) is performed in power-on reset or manual reset. 13 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 458 of 804 Bit 10 9 8 Bit Name RSTRG2 RSTRG1 RSTRG0 Initial Value 0 0 0 R/W R/W R/W R/W Description RTS Output Active Trigger The RTS signal goes high when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown in below. 000: 63 001: 1 010: 8 011: 16 100: 32 101: 48 110: 54 111: 60 7 6 RTRG1 RTRG0 0 0 R/W R/W Receive FIFO Data Number Trigger Set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCSSR). The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown in below. 00: 1 01: 16 10: 32 11: 48 5 4 TTRG1 TTRG0 0 0 R/W R/W Transmit FIFO Data Number Trigger Set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCSSR). The TDFE flag is set when, as the result of a transmit operation, the number of transmit data bytes in the transmit FIFO data register (SCFTDR) falls to or below the trigger set number shown in below. 00: 32 (32) 01: 16 (48) 10: 2 (62) 11: 0 (64) Note: The values in parentheses are the number of empty bytes in SCFTDR when the flag is set. Rev. 1.00, 02/04, page 459 of 804 Bit 3 Bit Name MCE Initial Value 0 R/W R/W Description Modem Control Enable Enables modem control signals CTS and RTS. This setting is only valid in asynchronous mode. 0: Modem signal disabled* 1: Modem signal enabled Note: * CTS is disabled regardless of the input value, and RTS is also fixed at 0. 2 TFRST 0 R/W Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * A reset operation is performed in the event of a power-on reset or manual reset. 1 RFRST 0 R/W Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * A reset operation is performed in the event of a power-on reset or manual reset. 0 LOOP 0 R/W Loopback Test Internally connects the transmit output pin (TxD) and receive input pin (RxD), and RTS pin and CTS pin, enabling loopback testing. 0: Loopback test disabled 1: Loopback test enabled Rev. 1.00, 02/04, page 460 of 804 16.3.11 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit read-only register that indicates the number of data bytes stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR). Bits 14 to 8 show the number of transmit data bytes in SCFTDR, and bits 6 to 0 show the number of receive data bytes in SCFRDR. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name T6 T5 T4 T3 T2 T1 T0 R6 R5 R4 R3 R2 R1 R0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Description R R R R R R R R R R R R R R R R Reserved This bit is always read as 0. These bits show the number of receive data bytes in SCFRDR. A value of H'00 means that there is no receive data, and a value of H'40 means that SCFRDR is full of receive data. Reserved This bit is always read as 0. These bits show the number of untransmitted data bytes in SCFTDR. A value of H'00 means that there is no transmit data, and a value of H'40 means that SCFTDR is full of transmit data. 16.3.12 Transmit Data Stop Register (SCTDSR) SCTDSR is an 8-bit readable/writable register that sets the number of transmit data bytes. SCTDSR is valid only when the TSE bit in the FIFO control register (SCFCR) is enabled. Transmit operation is stopped when the number of data bytes set in SCTDSR is transmitted. The setting value should be H'00 (one byte) to H'FF (256 bytes). This function is only enabled in asynchronous mode. SCTDSR is initialized to H'FF. Rev. 1.00, 02/04, page 461 of 804 16.4 16.4.1 Operation Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character, and in clock synchronous mode, in which synchronization is achieved with clock pulses. 64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. 16.4.2 Asynchronous Mode The asynchronous mode is described below. The transfer format is selected using the serial mode register (SCSMR), as shown in table 16.2. The SCIF clock source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR). * Data length: Choice of seven or eight bits * Choice of parity addition and addition of one or two stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing errors, parity errors, overrun errors, receive-FIFO-data-full state, receivedata-ready state, and breaks, during reception * Indication of the number of data bytes stored in the transmit and receive FIFO registers * Choice of internal or external clock as the SCIF clock source When internal clock is selected: the SCIF operates on the baud rate generator clock. When external clock is selected: A clock must be input according to the sampling rate. For example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate must be input (the on-chip baud rate generator is not used.) Rev. 1.00, 02/04, page 462 of 804 Table 16.2 SCSMR Settings for Serial Transfer Format Selection SCSMR Settings Bit 6: CHR 0 Bit 5: PE 0 Bit 3: STOP Mode 0 1 1 0 1 1 0 0 1 1 0 1 Yes 7-bit data No Yes Asynchronous mode SCIF Transfer Format Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Rev. 1.00, 02/04, page 463 of 804 16.4.3 Serial Operation in Asynchronous Mode Data Transfer Format: Table 16.3 shows the transfer formats that can be used in asynchronous mode. Any of eight transfer formats can be selected according to the SCSMR settings. Table 16.3 Serial Transfer Formats SCSMR Settings CHR 0 PE 0 STOP 0 1 1 0 1 1 0 0 1 1 0 1 S: Start bit STOP: Stop bit P: Parity bit 1 S S S S S S S S 2 Serial Transfer Format and Frame Length 3 4 5 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data STOP 6 7 8 9 10 STOP 11 12 STOP STOP P P STOP STOP STOP STOP STOP P P STOP STOP STOP Rev. 1.00, 02/04, page 464 of 804 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1 and CKE0 bits in SCSCR. When an external clock is input at the SCK pin, a clock must be input according to the sampling rate. For example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate must be input. Data Transfer Operations: 1. SCIF Initialization Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the transmit shift register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCSSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND bit in SCSSR has been set to 1. Clearing to 0 can also be performed during transmission, but the data being transmitted will go to the highimpedance state after the clearance. Before setting TE to 1 again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR. When an external clock is used, the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Rev. 1.00, 02/04, page 465 of 804 Figure 16.2 shows a sample SCIF initialization flowchart. Initialization Clear TE and RE bits in SCSCR to 0 1. 2. 3. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0. Set the transmit and receive format in SCSMR. Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) Wait at least one bit interval, then set the TE bit and RE bits in SCSCR to 1. Also set the RIE and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the TxD pin will go to the mark state; when receiving, the RxD pin will go to the idle state. Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR to B'00 (leaving TE and RE bits cleared to 0) 1 4. Clear the C/A bit in SCSMR to 0, and set the transmit/receive format 2 Set value in SCBRR Wait 3 1-bit interval elapsed? Yes Set RTRG1, RTRG0, TTRG1, and TTRG0 bits in SCFCR. Clear TFRST and RFRST bits to 0 No Set TE and RE bits in SCSCR to 1, and set RIE and TIE bits 4 End Figure 16.2 Sample SCIF Initialization Flowchart Rev. 1.00, 02/04, page 466 of 804 2. Serial Data Transmission Figure 16.3 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission Read TDFE bit in SCSSR 1 1. TDFE = 1? Yes Write (64 - transmit trigger set number) bytes of transmit data to SCFTDR, read 1 from TDFE bit in SCSSR, then clear to 0 No SCIF status check and transmit data write: Read the serial status register (SCSSR) and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, read 1 from the TDFE flag, then clear the flag to 0. The number of data bytes that can be written is 64 - (transmit trigger set number). Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE bit to 0. Break output at the end of serial transmission: To output a break in serial transmission, set the port SC data register (SCPDR) and port SC control register (SCPCR), then clear the TE bit in SCSCR to 0. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR. 2. All data transmitted? Yes No 2 3. Read TEND bit in SCSSR TEND = 1? Yes No Break output? Yes Set SCPDR and SCPCR No 3 Clear TE bit in SCSCR to 0 End of transmission Figure 16.3 Sample Serial Transmission Flowchart Rev. 1.00, 02/04, page 467 of 804 In serial transmission, the SCIF operates as described below. A. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 64 - (transmit trigger set number). B. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. When the transmit data stop function is used and the number of data bytes set in the transmit data stop register (SCTDSR) is matched, transmit operation is stopped, and the TSF flag in the serial status register (SCSSR) is set. If the TSIE bit in the serial control register (SCSCR) is set to 1, a transmit-data-stop-interrupt (TDI) request is generated. The vectors of transmit-FIFO-data-empty and transmit-data-stop interrupts are the same. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. A format in which a parity bit is not output can also be selected. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. C. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. Rev. 1.00, 02/04, page 468 of 804 Figure 16.4 shows an example of the operation for transmission in asynchronous mode. 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 and then cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 16.4 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) * Transmit Data Stop Function When a value in the SCTDSR register is matched with the number of transmit data bytes, this function stops the transmit operation. Interrupts can be generated and the DMAC can be activated by setting the TSIE bit (interrupt enable bit). Figure 16.5 shows an example of operation for the transmit data stop function. Transmit data TxD Start bit 0 D0 D1 D6 D7 Parity Stop bit bit 0/1 Start bit 0 D0 D1 D6 D7 0/1 TSF flag Figure 16.5 Example of Transmit Data Stop Function Rev. 1.00, 02/04, page 469 of 804 Figure 16.6 shows a flowchart for the transmit data stop function. Start of transmission 1. Set the transmit data stop number in SCTDSR, then set the TSE bit in SCFCR to 1.When an interrupt is enabled, also set the TSIE bit to 1. 2. If the TSF bit in SCSSR is set to 1, clear it to 0 after reading 1. When transmit data is written to SCFTDR in this state, transmit operation is started. 3. If the TSF bit is set to 1 (transmit data stop number is matched with transmit data number), transmit operation is stopped. If the TSIE bit is set to 1, an interrupt is generated. Serial transmission continuation procedure: Set the TCRST bit in SCFCR to 1, clear transmit count, and clear the TCRST bit to 0. Then follow steps 1, 2, and 3. Set transmit data stop number in SCTDSR 1 Set TSE and TSIE bits in SCFCR to 1 Read TSF bit in SCSSR; if it is 1, clear to 0 after reading 1 from TSF bit 2 TSF = 1 ? Yes End of transmission 3 No Figure 16.6 Transmit Data Stop Function Flowchart Rev. 1.00, 02/04, page 470 of 804 3. Serial Data Reception Figures 16.7 and 16.8 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. SCIF status check and receive data read: Read SCSSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading the lower bits of SCFDR. Start of reception Read DR, ER, and BRK flags in SCSSR 1 2. DR V ER V BRK = 1? No Yes Error handling 2 3. Read RDF flag in SCSSR No RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag in SCSSR to 0 3 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Figure 16.7 Sample Serial Reception Flowchart (1) Rev. 1.00, 02/04, page 471 of 804 Error handling ER = 1? Yes No 1 Receive error handling 1 Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a framing error occurred is stored. BRK = 1? Yes Break handling No 2 2 DR = 1? Yes Read receive data in SCFRDR No Clear DR, ER, and BRK flags in SCSSR to 0 End Figure 16.8 Sample Serial Reception Flowchart (2) Rev. 1.00, 02/04, page 472 of 804 In serial reception, the SCIF operates as described below. A. The SCIF monitors the communication line, and if 0 of a start bit is detected, performs internal synchronization and starts reception. B. The received data is stored in SCRSR in LSB-to-MSB order. C. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: the SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. c. Break check: the SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: Reception continues when a receive error (a framing error or parity error) occurs. D. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-datafull interrupt (RXI) request is generated. If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception interrupt (BRI) request is generated. If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive-data-ready interrupt (DRI) request is generated. The vectors of interrupts generated by each factor are the same. Rev. 1.00, 02/04, page 473 of 804 Figure 16.9 shows an example of the operation for reception in asynchronous mode. 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) RDF FER Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler RXI interrupt request One frame ERI interrupt request generated by receive error Figure 16.9 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. Transmit/receive when using the Modem Function When using a modem function, transmission can be stopped and started again according to the CTS input value. When the CTS is set to 1 during transmission, the data enters a mark state after transmitting one frame. When CTS is set to 0, the next transmit data is output starting with a start bit. Figure 16.10 shows an example of operation for the CTS control. Start bit Transmit data TxD 0 D0 D1 D6 D7 Parity Stop bit bit 0/1 Start bit 0 D0 D1 D6 D7 0/1 CTS Transmission stops when CTS goes high Transmission starts again when CTS goes low Figure 16.10 CTS Control Operation Rev. 1.00, 02/04, page 474 of 804 When using a modem function and the receive FIFO (SCFRDR) is at least the number of the RTS output trigger, the RTS signal goes high. Figure 16.11 shows an example of operation for the RTS control. Start bit Transmit data TxD 0 D0 D1 D6 D7 Parity Stop bit bit 0/1 RTS RTS goes high when receive data is at least number of RTS output trigger RTS goes low when receive data is less than number of RTS output trigger Figure 16.11 RTS Control Operation 16.4.4 Clock Synchronous Mode The clock synchronous mode is described below. 64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. The operating clock source is selected using the serial mode register (SCSMR). The SCIF clock source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR). * Transmit/receive format: Fixed 8-bit data * Indication of the number of data bytes stored in the transmit and receive FIFO registers * Internal clock or external clock used as the SCIF clock source When the internal clock is selected: The SCIF operates on the baud rate generator clock and outputs a serial clock from SCK pin. When the external clock is selected: The SCIF operates on the external clock input through the SCK pin. Rev. 1.00, 02/04, page 475 of 804 16.4.5 Serial Operation in Clock Synchronous Mode One unit of transfer data (character or frame) * * Serial clock LSB MSB Serial data don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 don't care Note: * High except in continuous transmission/reception Figure 16.12 Data Format in Clock Synchronous Communication In clock synchronous serial communication, data on the communication line is output from a falling edge of the serial clock to the next falling edge. Data is guaranteed valid at the rising edge of the serial clock. In serial communication, each character is output starting with the LSB and ending with the MSB. After the MSB is output, the communication line remains in the state of the MSB. In clock synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input through the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1 and CKE0 bits in SCSCR. Eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed, the clock is fixed high. However, when the operation mode is reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the clock high every time one character is transferred, write to the transmit FIFO data register (SCFTDR) the same number of dummy data bytes as the data bytes to be received and set the TE and RE bits to 1 at the same time to transmit the dummy data. When the specified number of data bytes are transmitted, the clock is fixed high. Rev. 1.00, 02/04, page 476 of 804 Data Transfer Operations: 1. SCIF Initialization Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the clock source, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the transmit shift register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCSSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND bit in SCSSR has been set to 1. The TE bit should not be cleared to 0 during transmission; if attempted, the TxD pin will go to the highimpedance state. Before setting TE to 1 again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR. Figure 16.13 shows sample SCIF initialization flowcharts. Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST bit in SCFCR to 1 1 1. Be sure to set the TFRST bit in SCFCR to 1, to reset the FIFOs. 2. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0. 3. Set the clock source selection in SCSMR. 4. Write a value corresponding to the bit rate into SCBRR. 5. Clear the TFRST bit in SCFCR to 0. Set value in SCBRR Clear TFRST bit to 0 4 5 6. Set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the TDFE flag to 0 after reading it. 7. Wait one bit interval. Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) 2 Set C/A bit in SCSMR to 1 Set CKS1 and CKS0 bits 3 Set transmit trigger number in TTRG1 and TTRG0 in SCFCR, write transmit data exceeding transmit trigger setting 6 number, and clear TDFE flag to 0 after reading 1 from it Wait 1-bit interval elapsed? Yes End 7 No Figure 16.13 Sample SCIF Initialization Flowchart (1) (Transmission) Rev. 1.00, 02/04, page 477 of 804 Initialization Clear TE and RE bits in SCSCR to 0 Set RFRST bit in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set C/A bit in SCSMR to 1 Set CKS1 and CKS0 bits Set value in SCBRR Clear RFRST bit in SCFCR to 0 Wait 1-bit interval elapsed? Yes End 6 No 1 1. Be sure to set the RFRST bit in SCFCR to 1, to reset the FIFOs. 2. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0. 3. Set the clock source selection in SCSMR. 4. Write a value corresponding to the bit rate into SCBRR. 5. Clear the RFRST bit in SCFCR to 0. 4 5 6. Wait one bit interval. 2 3 Figure 16.13 Sample SCIF Initialization Flowchart (2) (Reception) Rev. 1.00, 02/04, page 478 of 804 Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 1. Be sure to set the TFRST bit in SCFCR to 1, to reset the FIFOs. 1 2. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0. 3. Set the clock source selection in SCSMR. 4. Write a value corresponding to the bit rate into SCBRR. 5. Clear the TFRST and RFRST bits in SCFCR to 0. 6. Set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the TDFE flag to 0 after reading it. 7. Wait one bit interval. Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) 2 Set C/A bit in SCSMR to 1 Set CKS1 and CKS0 bits 3 Set value in SCBRR Clear TFRST and RFRST bits to 0 4 5 Set transmit trigger number in TTRG1 and TTRG0 in SCFCR, write transmit 6 data exceeding transmit trigger setting number, and clear TDFE flag to 0 after reading 1 from it Wait 1-bit interval elapsed? Yes End 7 No Figure 16.13 Sample SCIF Initialization Flowchart (3) (Simultaneous Transmission and Reception) Rev. 1.00, 02/04, page 479 of 804 2. Serial Data Transmission Figure 16.14 shows sample flowcharts for serial transmission. Start of transmission 1. Write the remaining transmit data to SCFTDR. 2. Transmission is started when the TE bit in SCSCR is set to 1. 3. After the end of transmission, clear the TE bit to 0. Write remaining transmit data to SCFTDR 1 Set TE bit in SCSCR When using transmit FIFO data interrupt, 2 set TIE bit to 1 TEND =1? Yes Clear TE bit in SCSCR to 0 End of transmission No 3 Figure 16.14 Sample Serial Transmission Flowchart (1) (First Transmission after Initialization) Start of transmission Set transmit trigger number in TTRG1 1 and TTRG0 in SCFCR 1. Set the transmit trigger number in SCFCR. 2. Write transmit data to SCFTDR, and clear the TDFE flag to 0 after reading 1 from it. 3. Wait for one bit interval. 4. Transmission is started when the TE bit in SCSCR is set to 1. 5. After the end of transmission, clear the TE bit to 0. Write transmit data exceeding transmit trigger setting number, and clear 2 TDFE flag to 0 after reading 1 from it Wait 3 No 1-bit interval elapsed? Yes Set TE bit in SCSCR When using transmit FIFO data interrupt, set TIE bit to 1 4 TEND =1? Yes No 5 Clear TE bit in SCSCR to 0 End of transmission Figure 16.14 Sample Serial Transmission Flowchart (2) (Second and Subsequent Transmission) Rev. 1.00, 02/04, page 480 of 804 3. Serial Data Reception Figure 16.15 shows sample flowcharts for serial reception. Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR 1 1. Set the receive trigger number in SCFCR. 2. Reception is started when the RE bit in SCSCR is set to 1. 3. Read receive data while the RDF bit is 1. Set RE bit in SCSCR When using receive FIFO data interrupt, 2 set RIE bit to 1 RDF =1? No Yes Read receive trigger number of receive 3 data bytes from SCFRDR Clear RE bit in SCSCR to 0 4 4. After the end of reception, clear the RE bit to 0. End of reception Figure 16.15 Sample Serial Reception Flowchart (1) (First Reception after Initialization) Rev. 1.00, 02/04, page 481 of 804 Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR Set RFRST bit in SCFCR to 1 1 1. Set the receive trigger number in SCFCR. 2 2. Reset the receive FIFO. 3. Wait for one bit interval. 4. Reception is started when the RE bit in SCSCR is set to 1. 3 5. Read receive data while the RDF bit is 1. 6. After the end of reception, clear the RE bit to 0. Clear RFRST bit in SCFCR to 0 Wait 1-bit interval elapsed? Yes No Set RE bit in SCSCR When using receive FIFO data interrupt, 4 set RIE bit to 1 RDF =1? Yes No Read receive trigger number of receive 5 data bytes from SCFRDR Clear RE bit in SCSCR to 0 End of reception 6 Figure 16.15 Sample Serial Reception Flowchart (2) (Second and Subsequent Reception) Rev. 1.00, 02/04, page 482 of 804 4. Simultaneous Serial Data Transmission and Reception Figure 16.16 shows sample flowcharts for simultaneous serial transmission and reception. Start of simultaneous transmission/reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR 1 1. Set the receive trigger number in SCFCR. 2. Write the remaining transmit data to SCFTDR, and if there is receive data in the FIFO, read receive data until there is less than the receive trigger setting number, read the TDFE and RDF bits in SCSSR, and if 1, clear to 0. 3. Transmission/reception is started when the TE and RE bits in SCSCR are set to 1. The TE and RE bits must be set simultaneously. 4. After the end of transmission/reception, clear the TE and RE bits to 0. Set TE and RE bits in SCSCR simultaneously When using transmit FIFO data interrupt, 3 set TIE bit to 1 When using receive FIFO data interrupt, set RIE bit to 1 Write remaining transmit data to SCFTDR 2 Read TDFE and RDF bits in SCSSR TDFE =1? RDF =1? Yes No Write 0 to TDFE and RDF bits in SCSSR after reading 1 from them TDFE =1? RDF =1? Yes No Read receive trigger number of receive data bytes from SCFRDR Clear TE and RE bits in SCSCR to 0 End of transmission/reception 4 Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1) (First Transfer after Initialization) Rev. 1.00, 02/04, page 483 of 804 Start of simultaneous transmission/reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR, and set transmit 1 trigger number in TTRG1 and TTRG0 Set TFRST and RFRST bits in SCFCR to 1 Clear TFRST and RFRST bits in SCFCR to 0 Write transmit data to SCFTDR Read TDFE and RDF bits in SCSSR TDFE =1? RDF =1? Yes 1. Set the receive trigger number and transmit trigger number in SCFCR. 2. Reset the receive FIFO and transmit FIFO. 3. Write transmit data to SCFTDR, and if there is receive data in the FIFO, read receive data until there is less than the receive trigger setting number, read the TDFE and RDF bits in SCSSR, and if 1, clear to 0. 4. Wait for one bit interval. 5. Transmission/reception is started when the TE and RE bits in SCSCR are set to 1. The TE and RE bits must be set simultaneously. 6. After the end of transmission/reception, clear the TE and RE bits to 0. 2 3 No Write 0 to TDFE and RDF bits in SCSSR after reading 1 from them Wait 1-bit interval elapsed? Yes 4 No Set TE and RE bits in SCSCR simultaneously When using transmit FIFO data interrupt, set TIE bit to 1 When using receive FIFO data interrupt, set RIE bit to 1 5 TDFE =1? RDF =1? Yes No Read receive trigger number of receive data bytes from SCFRDR Clear TE and RE bits in SCSCR to 0 End of transmission/reception 6 Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2) (Second and Subsequent Transfer) Rev. 1.00, 02/04, page 484 of 804 16.5 SCIF Interrupt Sources and DMAC The SCIF supports six interrupts in asynchronous mode--transmit-FIFO-data-empty (TXI), transmit-data-stop (TDI), receive-error (ERI), receive-FIFO-data-full (RXI), break-receive (BRI), and receive-data-ready (DRI). In clock synchronous mode, the SCIF supports two interrupts-- transmit-FIFO-data-empty (TXI) and receive-FIFO-data-full (RXI). The vectors of each interrupt are the same. Table 16.4 shows the interrupt sources. The interrupt sources can be enabled or disabled by means of the TIE, RIE, ERIE, BRIE, DRIE, and TSIE bits in SCSCR. When the TDFE flag in SCSSR is set to 1, a TXI interrupt request is generated. When the TSF flag in SCSSR is set to 1, a TDI interrupt request is generated. The DMAC can be activated and data transfer performed on generation of TXI and TDI interrupt requests. The DMAC requests of TXI and TDI are assigned to the same vector. When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed on generation of an RXI interrupt request. When using the DMAC for transmission/reception, set and enable the DMAC before making SCIF settings. See section 10, Direct Memory Access Controller (DMAC), for details of the DMAC setting procedure. When the ER flag in SCSSR is set to 1, an ERI interrupt request is generated. When the BRK flag in SCSSR is set to 1, a BRI interrupt request is generated. When the DR flag in SCSSR is set to 1, a DRI interrupt request is generated. When the TSF flag in SCSSR is set to 1, a TDI interrupt request is generated. The vectors of TXI, TDI, ERI, BRI, RXI and DRI are the same. The DMAC activation and interrupts cannot be generated simultaneously by the same source. The following procedure should be used for the DMAC activation. 1. 2. Set the interrupt enable bits (TIE, RIE and TDIE) corresponding to the generated source to 1. Mask the corresponding interrupt requests by using the interrupt mask register of the interrupt controller. Rev. 1.00, 02/04, page 485 of 804 Table 16.4 SCIF Interrupt Sources Description Interrupt initiated by receive error flag (ER) or break flag (BRK) Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready (DR) Interrupt initiated by transmit FIFO data empty flag (TDFE) or transmit data stop flag (TSF) DMAC Activation Not possible Possible*1 Possible*2 Notes: 1. The DMAC can be activated only by a receive-FIFO-data-full interrupt request. 2. The DMAC can be activated by a transmit-FIFO-data-empty (TDFE) or transmit-datastop (TSF) interrupt request. When the DMAC is activated by the TSF interrupt, it is cleared by either of two cases listed below. (1) The TSF flag is read by the CPU. (2) The transmit FIFO is full. See section 4, Exception Handling, for priorities and the relationship with non-SCIF interrupts. Rev. 1.00, 02/04, page 486 of 804 16.6 Notes on Usage Note the following when using the SCIF. SCFTDR Writing and the TDFE Flag: The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the 14 to 8 bits of the FIFO data count register (SCFDR). SCFRDR Reading and the RDF Flag: The RDF flag in the serial status register (SCSSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is still equal to or greater than the trigger number after a read, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all receive data has been read. The number of receive data bytes in SCFRDR can be found from the 6 to 0 bits of the FIFO data count register (SCFDR). Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues. Rev. 1.00, 02/04, page 487 of 804 Receive Data Sampling Timing and Receive Margin: As an example, when the sampling rate is 1/16, the SCIF operates on a base clock with a frequency of 8 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. Figure 16.17 shows an example of asynchronous mode receive data sampling timing in asynchronous mode. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock - 7.5 clocks Receive data (RxD) Synchronized sampling timing Data sampling timing Start bit + 7.5 clocks D0 D1 Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = 0.5 - 1 - (L - 0.5)F - 2N D - 0.5 (1 + F) N 100% ........................... (1) M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% ............................................. (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 1.00, 02/04, page 488 of 804 Initialize SCIF: The communication format should be changed according to the following procedure after the TE and RE bits are cleared to 0. The transmit shift register (SCTSR) is initialized by clearing the TE bit to 0. The receive shift register (SCRSR) is initialized by clearing the RE bit to 0. The contents of the serial status register (SCSSR), transmit FIFO data register (SCFTDR), and receive FIFO data register (SCFRDR) is retained even when the TE and RE bits are cleared to 0. The TE bit should be cleared after all transmit data have been transmitted and the TEND bit in SCSSR has been set to 1. The TE bit can be cleared while the data transmission is in progress. However, the data go to high-impedance after the TE bit has been cleared to 0. To start transmission again by setting the TE bit to 1, the SCFTDR should be reset by setting the TFRST bit in SCFCR to 1. The external clock should not be halted during the operation including an initialization since the operation becomes unstable. Transition to Power-Down Mode: The transitions to software standby mode and module standby mode should not be made by setting the module standby bit of SCIF during serial transmission and reception. The transitions to software standby mode and module standby mode should be made after both TE and RE bits in the serial control register (SCSCR) have been cleared (transmission/reception disabled). Transmit/Receive Pin in Transmission/Reception Disabled State: The TxD pin of the SCIF is in high-impedance state while the TE bit is cleared. The RxD pin is in input fixed state while the RE bit is cleared. Care is required on dealing a signal line that is connected to the TxD pin. When the connect destination pin is in input state, connect the pull-up register to a signal line. Rev. 1.00, 02/04, page 489 of 804 Rev. 1.00, 02/04, page 490 of 804 Section 17 Boot Function (BOOT) This LSI has a boot function which is used to download, to the on-chip memory, the firmware needed for the initial programming of the external flash memory. This function enables updating programs and dumping contents after the flash memory has been mounted on the board. This function eliminates the need to provide external address and data buses for the programming of the flash memory when this LSI and the flash memory, in bare-chip form, are sealed in a single package. This makes it possible to dramatically reduce the number of pins. 17.1 Features * Automatic downloading of the initial programming program from SCIF0 The operation of downloading, via the SCIF0, the initial programming program of the external flash memory to the on-chip memory (U memory), starts after a power-on reset. This transfer is synchronous and via the UART. This allows the downloading of any initial programming program according to the type of the external flash memory that is connected. If the specification defined in this section is conformed to, programs for purposes other than the initial programming of the external flash memory may be downloaded. The size of the program to be downloaded must be no more than 8,192 bytes and is otherwise freely determined. * Automatic bit-rate adjustment Automatic adjustment of the bit-rate at which the program is downloaded via the SCIF0 is possible. * High-speed execution of the downloaded program in on-chip memory Since the program downloaded from the SCIF0 is expanded in the on-chip RAM, it is executable at high speed. * Execution of the downloaded program starts automatically on completion of downloading After the specific program has been downloaded, processing automatically branches to the start address (H'A55F0000) in the downloaded program. Execution thus automatically starts. Note: Since the boot function is configured as a single circuit module, it is one of the target modules for power control by the module-standby function. The boot function is only necessary for boot processing. If, therefore, power consumption needs to be reduced in normal operation or in the sleep state, we recommend that the supply of the clock signal to the boot-function module be stopped by setting the MSTP43 bit in STBCR4 to 1. For details on the module-standby function, refer to section 13, Power-Down Modes. Figure 17.1 shows the block diagram of the boot function (BOOT). The I/O pins for the bus state controller (BSC) (A23 to A0, D15 to D0, WE1 to WE0, CS0, and RD) are connected to the external flash memory and the I/O pins for the SCIF0 (SCIF0_RxD and SCIF0_TxD) are connected to the external host. Rev. 1.00, 02/04, page 491 of 804 CPU U memory (RAM) This LSI Internal data bus (L-bus) Internal address bus (L-bus) Internal data bus (I-bus) Internal address bus (I-bus) BSC Cache Bus interface A23 to A0 Peripheral data bus Peripheral address bus Address/data control circuit D15 to D0 SCIF0 TMU Boot program ROM Area control circuit of external memory space CSm, WEn, RD BOOT_E Bus state controller m = 0, 3, 4 n = 0, 1 SCIF0 _TxD SCIF0 _RxD RESETP Note: The SCIF0_SCK, SCIF0_RTS, and SCIF0_CST are not used in the boot function. Figure 17.1 Block Diagram of Boot Function Rev. 1.00, 02/04, page 492 of 804 17.2 Input/Output Pin Table 17.1 shows the pin only for the boot function. For details on the pins that are connected to the external flash memory, refer to section 9, Bus State Controller (BSC); for details on the pins that are related to the SCIF0, refer to section 16, Serial Communication Interface with FIFO (SCIF); and, for details on the power-on reset pin (RESETP), refer to section 4, Exception Handling. Table 17.1 Input/Output Pin Pin Name BOOT_E I/O Input Function Boot Enable Input The state of this pin can only be switched during a reset. 17.3 Register Description The BOOT has no registers which are accessible by the CPU. Rev. 1.00, 02/04, page 493 of 804 17.4 17.4.1 Operation Address Space in Boot Mode When the BOOT_E pin is asserted to its low level by a power-on reset (RESETP = low), this LSI enters boot mode at the end of a reset. At this point, processing by this LSI would not normally branch to the reset vector. In boot mode, processing branches to the on-chip boot program instead, to initiate the boot function. Because of the initial state by a reset, the CPU enters privileged mode. For details on privileged mode, refer to section 2.1, Processing States and Processing Modes. In boot mode, which differs from the normal privileged mode, area 0 in the external memory space is divided into the two areas shown in figure 17.2. The area from H'00000000 to H'01FFFFFF is exclusively used for the boot function. Access to locations in this area by the user is thus prohibited. The boot program is placed here. The area from H'02000000 to H'03FFFFFF is an area 0 which is the same as the area 0 of the normal privileged mode. External address space H'00000000 Area 0 H'04000000 Area 1 (on-chip register and on-chip memory) Area 2 (Reserved) Shadow space Area 3 H'10000000 Area 4 H'14000000 Shadow space Area 5 (Reserved) H'03000000 Area 6 (Reserved) Area 7 (Reserved) H'03FFFFFF Normal mode Boot mode Shadow space Shadow space Space for mounting (max. 16Mbytes) H'02000000 Space for mounting (max. 16Mbytes) Area for boot program H'00000000 H'08000000 H'01000000 H'0C000000 H'18000000 H'1C000000 H'1FFFFFFF Figure 17.2 External Memory Space in Boot Mode Rev. 1.00, 02/04, page 494 of 804 In the initial programming of the external flash memory, the reset vector always selects a branch to the address H'A0000000 (a virtual address as seen from the CPU) after the power-on reset signal has been cancelled and area 0 in the external address space is accessed. The programming program must thus be executed from a start address in area 0. In boot mode, however, addresses H'00000000 to H'01FFFFFF are exclusively used for the boot function, so programming is executed from the start address H'02000000. The maximum mounted area for this LSI is 16 Mbytes. Since the address range from H'02000000 to H'02FFFFFF is the shadow space for the range from H'00000000 to H'00FFFFFF, if programming starts at address H'02000000, access can be performed from address H'00000000 after boot mode has been cancelled. Note: The state of the input on the BOOT_E pin input must not be changed except during a reset. If this state is changed, correct operation is not guaranteed. 17.4.2 Procedure for Execution of Boot Processing The initial programming program of the external flash memory must be placed in the external host before the boot function is used. The initial programming program must be prepared in accordance with the programming algorithm for the external flash memory that is to be used. The boot program starts preparing for the transfer of data to and from the external host over channel 0 of the SCIF. After the necessary initial settings for the SCIF0 have been made, the bit rate for use in transmission/reception is automatically adjusted to suit the external host. Figure 17.3 shows the procedure according to which boot processing is executed. Automatic Adjustment Operation for SCIF0 Bit Transfer Rate: This LSI automatically adjusts the bit transfer rate for transmission/reception to a value in the range between 9.6 kbps and 38.4 kbps. When this LSI is activated in boot mode, it measures the period of the low levels in the synchronous data (H'00) which is continuously transmitted from the external host. Channel 0 in the timer unit (TMU) is used for this low-period measurement. Here, the external host must set the format for transfer between this LSI and the SCIF0 as 8-bit data, one stop bit, and no parity bit. After the boot program has calculated the bit rate at which bits are being transferred from the external host by using the measurement of the low period and the optimum setting has been made, a single byte with the value H'00 is transmitted to the external host as notification of the end of the bit-rate adjustment. After the external host has successfully received this notification of the end of bit-rate adjustment, a single byte with the value H'55 must be returned to this LSI. After this LSI has received this byte, it transmits a single byte with the value H'AA. Note: If reception is not successful, execution enters an endless loop and the program will not react. In such a case, reinitiate boot mode after a reset, and repeat the above operations. Rev. 1.00, 02/04, page 495 of 804 Transferring of Initial Programming Program: The boot program starts downloading the initial programming program after the automatic adjustment of the bit transfer rate has been completed. The maximum size of the initial programming program that is downloaded over the SCIF0 channel is 8,192 bytes (H'2000)*1. The downloaded initial programming program is stored in the address range from H'055F0000 to H'055F1FFF (physical addresses) in the on-chip memory (U memory). After the downloading has been completed, the boot program automatically branches to address H'055F0000*2. Therefore the start address of the program that is downloaded must be H'055F0000. Although the boot program uses the address range from H'055FFFFC to H'055FFFFF (physical addresses) as a working area, the downloaded initial programming program is able to use this area after downloading has been completed. Notes: 1. The size setting for the initial programming program must not be H'0000 or greater than H'2001, as normal operation is not possible in such a case. If such a program is used, correct operation is not guaranteed. 2. The initial setting routine of user program that is programmed by the initial programming program in boot mode should be stored from H'02000000 in area 0. The initial setting is enabled since the branch to the first address of area 0 (H'00000000) is made immediately after a power-on reset in normal mode. A maximum of 16 Mbytes may be mounted in area 0, i.e., the address range from H'02000000 to H'02FFFFFF is available (H'00000000 to H'00FFFFFF in normal mode) as shown in figure 17.2. In this LSI, external memory may be mounted in areas 3 and 4 as well as in area 0. The maximum size for each area is 16 Mbytes. Areas 3 and 4 may be used as expansion spaces for the external flash memory, when this is necessary, by preparing a corresponding initial programming program. Rev. 1.00, 02/04, page 496 of 804 Boot-Mode Initiation Bit-Rate Adjustment Transfer of Initial Programming Program n=n+1 No External Host Start This LSI Start Set BOOT_E pin to boot mode and execute start-up from a power-on reset Execute SCIF0-related and other initial settings Transmit 10 continuous bytes of H'00 data at prescribed bit rate H'00,H'00, ... Measure low period in data (H'00) being transmitted by external host Calculate bit rate and set value in bit-rate register (SCBRR) After bit-rate adjustment, transmit one byte of data (H'00) to notify external host of completion of adjustment Confirm successful reception of notification of end of bit-rate adjustment (H'00), and transmit one byte of data (H'55) H'00 H'55 After receiving data (H'55), transmit one byte of data (H'AA) to external host After receiving data (H'AA), go to next step H'AA Transmit two bytes to indicate size of initial programming program (number of bytes: N); upper byte followed by lower byte Receive echo-back data (n = 1) Upper bytes Lower bytes (*) Echo-back Transmit received number of bytes (N) to external host as verified data (echo-back) Do transmitted and received data match? No Error n=1 Yes Transmit initial programming program as a sequence of bytes H'xx Transmit received program to external host as verified data (echo-back) Echo-back Receive echo-back data Do transmitted and received data match? Yes No Error Transfer received program to on-chip RAM (U memory) n=n+1 n = N? Yes After receiving data (H'AA), go to next step n = N? Yes H'AA Transmit one byte of data (H'AA) No Transmission/Reception are disabled (SCSCR 0 = H'00) Execute initial programming program Branch to initial programming program in on-chip RAM Note: The setting for the size of the initial programming program must be in the range from H'0001to H'2000. If the size is set to H'0000 or greater than H'2001, normal operation is not possible. Figure 17.3 Procedure for Execution of Boot Processing Rev. 1.00, 02/04, page 497 of 804 17.5 17.5.1 Usage Note Endian when Using Boot Function The boot function is operated by the firmware that is stored in the boot ROM and functions on big endian. Therefore, when the BOOT_E pin is asserted to its low level by a power-on reset (RESETP = low), the MD5 pin should be driven low (big endian mode). After the specific program has been downloaded, the boot function is branched to the start address in the initial programming program for the external flash memory downloaded in the on-chip memory (Umemory). The initial programming program needs to be specified to operate on big endian. To execute normal operation on little endian, pay attention to the code alignment when the flash memory is initially programmed. 17.5.2 Clock Frequency and Data Transfer Rate when Using Boot Function The transfer rate of SCIF which communicates with an external host when the boot function is used has the limitation shown in table 17.2. Note that a proper value should be set for the transfer rate in the program for the external host, such as "exflash". Table 17.2 Clock frequency and data transfer rate of SCIF when boot function is used CPG setting Mode 5 Clock ratio I:B:P = 2:2:1 Mode 7 Clock ratio I:B:P = 1:1:1/2 Input clock frequency 10MHz or more 13MHz or more 16MHz or more 20MHz or more 26MHz or more 32MHz or more SCIF transfer rate 9600bps 19200bps 38400bps 9600bps 19200bps 38400bps Rev. 1.00, 02/04, page 498 of 804 Section 18 USB Pin Multiplex Controller (USBPM) 18.1 Feature The USB pin multiplex controller controls the data path to USB transceiver from USB host controller or USB function controller. This USB pin multiplex controller also incorporates a clock select control function that selects the clock signal to be provided to the USB host controller and USB function controller as either an internally generated clock or externally input clock. Both the USB host controller and the USB function controller are connected to the USB transceiver via multiplexer that is controlled by the EXCPG control register (EXCPGCR). The USB transceiver can be connected to USB host controller or USB function controller. This LSI generates a 48-MHz clock, which is specified by the USB1.1 specifications, by the onchip multiplier circuit using a13-MHz clock input from the RDI_REFCLK_IN pin and provides the clock to the USB host controller and USB function controller. A 48-MHz clock can also be externally provided to the USB host controller and USB function controller. The on-chip multiplier circuit allows the user to receive a stable clock from the RF-IC to be connected to this LSI directly without connecting 48-MHz TCXO externally. Note, however, that a specific length of jitter may occur when the on-chip multiplier circuit is used. Before using a clock provided from the on-chip multiplier circuit, check the connectivity to other USB devices. Figure 18.1 shows the USB pin multiplexer indicating the connection among the on-chip USB host controller, USB function controller, on-chip port 1 analog USB transceiver, and clock control circuit. Rev. 1.00, 02/04, page 499 of 804 USB host controller pwr_en Power Port 1 Transceiver controller USB Pin Multiplex Controller pwr_en/ pull-up pin multiplexer ovr_current/ VBUS pin multiplexer Control ovr_current USB1_PWR_EN/ USB_PULLUP USB1_OVR_CRNT/ USB_VBUS USB function controller Power Port 1 Transceiver controller VBUS USB host/function transceiver signals multiplexer Select Control signals 48-MHz clock USB transceiver Clock Control Circuit USB_P USB_N UCLK (48 MHz) Multiplier Divider RDI_REFCLK_IN (13 MHz) EXCPGCR Figure 18.1 Block Diagram of this USB Rev. 1.00, 02/04, page 500 of 804 18.2 Input/Output Pins USB pin multiplexer controller has pins that are shown in tables 18.1, 18.2, and 18.3 Table 18.1 Pin Configuration (Analog Transceiver Signal) Pin Name USB_P USB_N I/O Description Input/Output P pin D+ port transceiver pin Input/Output D pin D- port transceiver pin Note: The pins shown in table 18.1 can be used as port 1 USB host controller pins, or port 1 USB function controller pins. Ensure these pins are open when not used. Table 18.2 Pin Configuration (Power Control signal) Pin Name USB_PWR_EN/ USB_PULLUP USB_OVR_CRNT/ USB_VBUS I/O Output Input Description Power enable pin/ USB pull-up control pin Enables power supply (USBH)/controls USB pull-up (USBF)* Over-current pin/VBUS pin Detects over-current (USBH)/monitors USB cable connection (USBF)* Note: The pins shown in table 18.2 can be used for power control for USB. Pins indicated by * have multiplexed functions for the USB host controller (USBH) and the USB function controller (USBF). Table 18.3 Pin Configuration (Clock Control signal) Pin Name RDI_REFCLK_IN I/O Input Description Bluetooth interface clock pin Pin for the Bluetooth interface clock (13MHz) input (generates a 48-MHz clock by the on-chip multiplier) UCLK Input External clock pin Pin for the 48-MHz clock input from an external device Note: A 48-MHz clock is provided to the USBH or USBF by using RDI_REFCLK_IN or UCLK. Rev. 1.00, 02/04, page 501 of 804 18.3 Register Description Register configuration of the USB pin multiplexer controller is described below. See section 27, List of Registers, for the addresses of this register and the state of it in each processing status. * EXCPG control register (EXCPGCR) 18.3.1 EXCPG Control Register (EXCPGCR) EXCPGCR controls providing a 48-MHz clock to the USB host controller and USB function controller and performs module reset. Bit Bit Name Initial Value All 0 R/W R Descriptions Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 4 USBVALID 0 R USB Status The USB module status bit that Indicates whether the USB module (both the USB host and USB function controllers) can be used or not. This bit is a read-only bit. A write access to this bit is ignored. Immediately after power-on reset of the USB module, immediately returning from the software standby, or immediately after reset by USBRESET, the USB module cannot be used for a short time. Before using the USB module, check this bit status. Note: Even if the USBHSTP and USBFSTP bits are set, the on-chip multiplier circuit does not stop and this bit remains set to 1. 0: USB module cannot be used. 1: USB module can be used. 7 to 5 Rev. 1.00, 02/04, page 502 of 804 Bit 3 Bit Name Initial Value R/W R/W Descriptions USB Reset The USB module reset bit to be used to reset the USB module (both the USB host and USB function controllers). If this bit is cleared to 0, the USBVALID bit is cleared to 0 after approximately 1 s. After checking that the USBVALID bit is cleared to 0, set the USBRESET bit to 1. After this USBRESET bit is set to 1, the USB module starts the reset sequence. After the reset sequence, the USBVALID bit is set to 1 again. To ensure USB module initialization, follow the above sequence. To provide a clock again to the USB module after the clock has been stopped using the USBHSTP and USBFSTP bits, USB module operation may be unstable. Therefore, use the USB module after resetting by this bit. 0: USB module is reset. 1: USB module is in normal operation. USBRESET 1 2 USBHSTP 0 R/W Module Stop USBH The USB host controller stop bit to be used to provide or stop the USB host controller operating clock. Clearing this bit to 0 provides the clock to the USB host controller. Setting this bit to 1 stops the clock. If both the USBHSTP and USBFSTP bits are set to 1 or cleared to 0, the USB transceiver operation stops. The USB_P and the USB_N outputs pins enter the high-impedance state, and then USB_PWR_EN/USB_PULLUP pin is brought low. Before using the USB host or USB function controller, clear one of USBHSTP or USBFSTP to 0. Note that the USB host controller and USB function controller cannot be used simultaneously. If the USB module control register is accessed while both the USBHSTP and USBFSTP bits are cleared to 0, correct operation cannot be guaranteed. Note that the USB host controller register access is ignored while the clock provided to the USB host controller is stopped. 0: USB host controller operation continues. 1: Stop providing clock to the USB host controller. Rev. 1.00, 02/04, page 503 of 804 Bit 1 Bit Name USBFSTP Initial Value 0 R/W R/W Descriptions Module Stop USBF The USB function controller stop bit to be used to provide or stop the USB function controller operating clock. Clearing this bit to 0 provides the clock to the USB function controller. Setting this bit to 1 stops the clock. If both the USBHSTP and USBFSTP bits are set to 1 or cleared to 0, the USB transceiver operation stops. The USB_P and the USB_N outputs pins enter the highimpedance state, and then the USB_PWR_EN/USB_PULLUP pin is brought low. Before using the USB host or USB function controller, clear one of USBHSTP and USBFSTP to 0. Note that the USB host controller and USB function controller cannot be used simultaneously. If the USB module control register is accessed while both the USBHSTP and USBFSTP bits are cleared to 0, correct operation cannot be guaranteed. Note that the USB function controller register access is ignored while the clock provided to the USB function controller is stopped. 0: USB function controller operation continues. 1: Stop providing clock to the USB function controller. 0 USBCLKSEL 0 R/W USB Clock Select The USB clock source select bit used to select whether the USB clock is internally generated or the USB clock is externally input. After this bit is modified, both the USB host and the USB function controllers must be initialized by the USBRESET bit. 0: The USB clock is generated internally. 1: The USB clock is input by the UCLK pin. Rev. 1.00, 02/04, page 504 of 804 18.4 18.4.1 Examples of External Circuit Example of the Connection between USB Function Controller and External Circuit Figures 18.2 and 18.3 show example connections of USB function controller and external circuit. When the USB function controller is used, a signal must be provided to the cable connection monitor pin (USB_VSBUS). The USB_VBUS pin is multiplexed with the USB_OVR_CRNT pin, and writing 0 to USBFSTP and 1 to USBHSTP in EXCPGCR register selects the USB_VBUS pin functions. According to the status of the USB_VBUS pin, the USB function controller recognizes whether the cable is connected/disconnected. Also, pin D+ must be pulled up in order to notify the USB host/hub that the connection is established. The sample circuits in figures 18.2 and 18.3 use the USB_PULLUP pin for pull-up control. This LSI USB_PULLUP IC allowing voltage application when system power is off 1.5k USB connector 5V IC allowing voltage application when system power is off 27 USB function controller IC1 USB_VBUS USB_P USB_N 3.3V IC2 VBUS D+ 27 D- GND Figure 18.2 Example 1 of Connection between USB Function Controller and External Circuit Rev. 1.00, 02/04, page 505 of 804 This LSI USB_PULLUP USB function controller IC1 USB_VBUS USB_P USB_N 3.3V IC allowing voltage application when system power is off 1.5k USB connector 5V VBUS IC2 IC allowing voltage application when system power is off 27 D+ 27 D- GND Figure 18.3 Example 2 of Connection between USB Function Controller and External Circuit * D+ Pull-up Control Control D+ pull-up via the USB_PULLUP pin in the system in case that the connectionnotification (D+ pull-up) of connection to the USB host controller or hub is to be inhibited (i.e., during high-priority processing or initialization processing). The D+ pull-up control signal and USB_VBUS pin input signal should be controlled via the USB_PULLUP pin and the USB cable VBUS (AND circuit) as shown in the examples in figure 18.2. D+ pull-up is inhibited when the USB_PULLUP pin is low in an example of figure 18.2. (The initial setting of the USB_PWR_EN/USB_PULLUP pin is low.) Pull-up D+ after confirming that USB_VBUS pin became high, when the pull-up control is performed directly by USB_PULLUP pin as is shown in an example of figure 18.3. Use an IC such that allows voltage application when system power is off (for example, HD74LV1G126A) for the pull-up control IC (IC2 in figures 18.2 and 18.3). (The UDC core in this LSI holds the powered state when USB_VBUS pin is low, regardless of the D+/D- state.) Rev. 1.00, 02/04, page 506 of 804 * Detection of USB Cable Connection/Disconnection As USB function controller in this LSI manages the state by hardware, USB_VBUS signal is necessary to recognize connection or disconnection of the USB cable. The power supply signal (VBUS) in the USB cable is used for USB_VBUS. However, if the cable is connected to the USB host or hub when the power of USB function controller (this LSI--installed system) is off, a voltage of 5 V will be applied from the USB host controller or hub. Therefore, use an IC such that allows voltage application when system power is off (for example, HD74LV1G08A) for the IC1 in figures 18.2 to 18.3. 18.4.2 Example of the Connection between USB Host Controller and External Circuit Figure 18.4 shows example connections of the USB host controller and external circuit. When using the USB host controller, a separate LSI must be used for USB power bus control (equivalent to the USB power control LSI's in figure 18.4). Make sure the LSI has the power supply capacity to satisfy the USB standard, and select one that has an overcurrent protection function. Configure the system so that the input to the USB_OVR_CRNT pin is Low on detection of an overcurrent. This LSI USB host controller USB_OVR_CRNT USB_PWR_EN USB power control LSI USB connector 5V GND USB_P 27 15k D+ USB_N 27 15k D- Figure 18.4 Example of Connection USB Host Controller and External Circuit Rev. 1.00, 02/04, page 507 of 804 18.5 Usage Notes About the Examples of External Circuit: These examples of connection with an external circuit in this chapter are for reference only, therefore proper operation is not guaranteed with these circuit examples. If system countermeasures are required for external surges and ESD noise, use a protective diode, etc. About the Clock Input to the USB: When the USB clock is generated internally, the clock source is generated not by an input clock from the EXTAL pin specified as the CPU clock source but an input clock by the RDI_REFCLK_IN pin specified as clock used for data I/O with the RFIC of the Bluetooth and the link controller. To use the USB function of this LSI without being connected to the RF-IC of the Bluetooth, the USB should be input the 13-MHz clock conforming to the USB standard by the RDI_REFCLK_IN pin. To use the USB function of this LSI without being connecting to the RF-IC of the Bluetooth actually, input of 48-MHz clock conforming to the USB standard by means of the UCLK pin is recommended. Problems with Using Non-specified Commercial USB Cable: Some USB cables on the market do not meet the specification, and there are confirmed cases of non-specified USB cable to have problems with connectivity. Use only specified USB cable with this product. Rev. 1.00, 02/04, page 508 of 804 Section 19 USB Host Controller (USBH) The USB host controller module (hereafter referred to as the host controller) incorporated in this LSI supports the Open Host Controller (OpenHCI) Specification for the Universal Serial Bus (USB) as well as the universal serial bus specification ver.1.1. The OpenHCI specification for the USB is a register-level description of the host controller. It is necessary to refer the OpenHCI specification to develop drivers for this host controller and hardware. 19.1 Features The host controller in this LSI has the following features: * * * * * * Conforms to the OpenHCI specification ver.1.0 register set Corresponding to the universal serial bus specification ver.1.1 Supports root hub function Supports low-speed (1.5 Mbps) and full-speed (12 Mbps) modes Supports overcurrent detection Supports 127-endpoint control in maximum IFUSBH0A_000020020800 Rev. 1.00, 02/04, page 509 of 804 19.2 Input/Output Pins Table 19.1 shows the pin configuration of the USB host controller. For the detailed method for setting each pin, refer to section 18, USB Pin Multiplex Controller(USBPM). Table 19.1 Pin Configuration Pin Name UCLK RDI_REFCLK_IN I/O Input Input Function External Clock Pin For direct input to 48MHz clock from an external device External clock input The 13 MHz external clock is input. This signal is multiplied internally, and the clock of 48 MHz is generated. USB_PWR_EN/ USB_PULLUP USB_OVR_CRNT/ USB_VBUS USB_P USB_N Output Input Power Enable Pin/Pull-up Control Pin Enables power supply (USBH)/controls USB pull-up (USBF) Overcurrent Pin/ VBUS Pin Detects over-current (USBH)/monitors USB cable connection (USBF) Input/ Output Input/ Output P Pin D+ port transceiver pin N Pin D- port transceiver pin Note: Either of RDI_REFCLK_IN or UCLK is used for 48MHz clock of the USB. Rev. 1.00, 02/04, page 510 of 804 19.3 Register Descriptions The USB host controller (USBH) has the following registers. For details on register addresses and register states during each processing, refer to section 27, List of Registers. * * * * * * * * * * * * * * * * * * * * * * HcRevision register (HREVR) HcControl register (HCTLR) HcCommandStatus register (HCSR) HcInterruptStatus register (HISR) HcInterruptEnable register (HIER) HcInterruptDisable register (HIDR) HcHCCA register (HHCCAR) HcPeriodCurrentED register (HPCEDR) HcControlHeadED register (HCHEDR) HcControlCurrentED register (HCCEDR) HcBulkHeadED register (HBHEDR) HcBulkCurrentED register (HBCEDR) HcDoneHeadED register (HDHEDR) HcFmInterval register (HFIR) HcFmRemaining register (HFRR) HcFmNumber register (HFNR) HcPeriodicStart register (HPSR) HcLSThreshold register (HLSTR) HcRhDescriptorA register (HRDRA) HcRhDescriptorB register (HRDRB) HcRhStatus register (HRSR) HcRhPortStatus1 register (HRPSR) Rev. 1.00, 02/04, page 511 of 804 19.3.1 HcRevision Register (HREVR) HREVR includes the BCD expression of the HCI specification version implemented for the host controller. The value H'10 corresponds to the version 1.0. All HCI implementation conforming to this specification have the value of H'10. Bit 31 to 8 Initial Bit Name Value -- All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 0 0 0 1 0 0 0 0 R R R R R R R R Revision Version Number (BCD Expression) H'10: Version 1.0 Rev. 1.00, 02/04, page 512 of 804 19.3.2 HcControl Register (HCTLR) HCTLR specifies the operation mode for the host controller. Bit 31 to 9 Initial Bit Name Value -- All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 8 IR 0 R/W Interrupt Routine Determines the issue of interrupts generated by the event registered in the HcInterruptStatus register. The host controller driver clears this bit at the same time as the hardware reset, however, does not clear at the same time as the software reset. The host controller driver uses this bit as a tag to indicate the ownership of the host controller. 0: All interrupts are issued to the interrupt mechanism of the normal host bus. 1: Interrupts are issued to SMI. 7 6 HCFS1 HCFS0 0 0 R/W R/W Host Controller Function Status The host controller driver detects whether the host controller has started to transmit SOF after having read the SF bit in the HcInterruptStatus register. This bit can be changed only in the USB Suspend state by the host controller. The host controller can move from the USB Suspend state to the USB Resume state after having detected the resume signal from the downstream port. In the host controller, USB Suspend is entered after the software reset so that USB Reset is entered after the hardware reset. The former resets the route hub. 00: USB Reset 01: USB Resume 10: USB Operational 11: USB Suspend Rev. 1.00, 02/04, page 513 of 804 Bit 5 Initial Bit Name Value BLE 0 R/W R/W Description Bulk List Enable This bit is set to enable the processing of the bulk list in the next frame. The host controller checks this bit when the processing of the list has been determined. When disabling, the host controller driver can correct the list. When the HcBulkCurrentED register indicates ED* to be deleted, the host controller driver should hasten the pointer by updating the HcBulkCurrentED register before re-enabling the list processing. 0: Bulk list processing is not carried out. 1: Bulk list processing is carried out. 4 CLE 0 R/W Control List Enable This bit is set to enable the processing of the control list in the next frame. If cleared by the host controller driver, the processing of the control list is not carried out after next SOF. The host controller must check this bit whenever the list will be processed. When disabling, the host controller driver can correct the list. When the HcControlCurrentED register indicates ED to be deleted, the host controller driver should hasten the pointer by updating the HcControlCurrentED register before reenabling the list processing. 0: Control list processing is not carried out. 1: Control list processing is carried out. 3 IE 0 R/W Isochronous Enable This bit is used by the host controller driver to enable/disable the processing of isochronous ED. While processing the periodic list in the frame, the host controller will check the status of this bit when it finds an isochronous ED (F = 1). If set (enabled), the host controller continues to process ED. If cleared (disabled), the host controller stops the processing of the periodic list (currently includes only isochronous ED) and starts to process the bulk/control list. Setting this bit is guaranteed to be valid in the next frame (not in the current frame). 0: Isochronous ED processing is not carried out. 1: Isochronous ED processing is carried out. Rev. 1.00, 02/04, page 514 of 804 Bit 2 Initial Bit Name Value PLE 0 R/W R/W Description Periodic List Enable This bit is set to enable the processing of the periodic list in the next frame. If cleared by the host controller driver, no periodic list processing is carried out after next SOF. The host controller must check this bit before the host controller starts to process the list. 0: The periodic list processing is not carried out after next SOF. 1: The periodic list processing is carried out after next SOF. 1 0 CBSR1 CBSR0 0 0 R/W R/W Control Bulk Service Ratio This bit specifies the service ratio of the control and bulk ED. The host controller must compare the ratio specified by the internal calculation whether it has processed control ED in determining whether another control ED is continued to be supplied or switched to bulk ED before any periodic list is processed. The internal calculation is retained when the frame boundary is exceeded. In case of reset, the host controller driver is responsible for restoring this value. 00: 1:1 01: 2:1 10: 3:1 11: 4:1 Note: * ED is Endpoint Descriptor. Rev. 1.00, 02/04, page 515 of 804 19.3.3 HcCommandStatus Register (HCSR) HCSR is used by the host controller not only for reflecting the current status of the host controller, but also for receiving a command issued by the host controller driver. A write is for setting the host controller driver. The host controller must guarantee that the bit to which 1 is written to is set and the bit to which 0 is written to is unchanged. The host controller driver can distribute multiple clear commands to the host controller by a previously issued command. The host controller driver can read all bits normally. The SOC0 and SOC1 bits indicate the number of the frame that has detected the SchedulingOverrun error by the host controller. This occurs when the periodic list has not completed before EOF. When the SchedulingOverrun error is detected, the host controller increments the counter and sets the SO field in the HcInterruptStatus register. Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 17 16 SOC1 SOC0 0 0 R/W R/W Scheduling Overrun Count These bits are incremented when each SchedulingOverrun error occurs. These bits are initially set to B'00 and returned to B'11. These bits are incremented when a SchedulingOverrun error is detected even though the SO bit in the HcInterruptStatus register is set. These bits are used by the host controller driver to monitor any continuous scheduling problem. Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 3 OCR 0 R/W Ownership Change Request This bit is set by the OS host controller driver to request the change of the control of the host controller. When this bit is set, the host controller sets the OC bit in the HcInterruptStatus register. After a change, this bit is cleared and remains until the next request from the OS host controller driver. 0: After a change, this bit is cleared and remains until the next request from the OS host controller driver. 1: Set the OC bit in the HcInterruptStatus register. 31 to 18 -- 15 to 4 -- All 0 R Rev. 1.00, 02/04, page 516 of 804 Bit 2 Initial Bit Name Value BLF 0 R/W R/W Description Bulk List Filled This bit is used to indicate that there are some TDs in the list. This bit is set by the host controller driver to the list when TD* is added to ED. When the host controller starts to process the head of the list, it checks this bit. As long as this bit is 0, the host controller does not start to process the list. When this bit is 1, the host controller starts to process the list to set this bit to 0. When the host controller detects TD in the list, the host controller sets this bit to 1. When TD is never found in the list and the host controller driver does not set this bit, the host controller completes the processing of the list. This bit is still 0 when the bulk list processing is stopped. 0: The list is not processed. 1: The list is processed. 1 CLF 0 R/W Control List Filled This bit is used to indicate that there are some TDs in the control list. This bit is set by the host controller driver when TD is added to ED in the control list. When the host controller starts to process the head of the control list, it checks this bit. As long as this bit is 0, the host controller does not start to process the control list. If this bit is 1, the host controller starts to process the control list and this bit is set to 0. When the host controller detects TD in the list, the host controller sets this bit to 1. When TD is never detected in the control list and the host controller driver does not set this bit, the host controller completes the processing of the control list. This bit is still 0 when the control list processing is stopped. 0: The list is not processed. 1: The list is processed. Rev. 1.00, 02/04, page 517 of 804 Bit 0 Bit Name HCR Initial Value 0 R/W R/W Description Host Controller Request This bit is set by the host controller driver to initiate the software reset of the host controller. The system is moved to the USB Suspend state in which most of the operational registers are reset except for the next state regardless of the functional state of the host controller. For example, an access without the IR field in the HcControl register and host bus are allowed. This bit is cleared by the host controller upon completion of the reset operation. The reset operation must be completed within 10 s. When this bit is set, it does not cause any reset to the route hub and the next reset signal is not output to the downstream port. 0: Cleared by the host controller at the completion of the reset operation 1: USB Suspend state Note: * TD is Transfer Descriptor. 19.3.4 HcInterruptStatus Register (HISR) HISR indicates the status in various events that cause hardware interrupts. When an event occurs, the host controller sets the corresponding bit in this register. When the bit is set to 1, a hardware interrupt is generated while an interrupt is enabled and the MIE bit is set in the HcInterruptEnable register (see section 19.3.5, HcInterruptEnable Register (HIER)). When an interrupt occurs, the exception code (H'A00) of the host controller interrupt (USBHI) is set in the interrupt event register 2 (INTEVT2) and the exception handling is started. For details on the interrupt event register 2 (INTEVT2), see section 4, Exception Handling, and for details on the exception code and interrupt processing of the host controller interrupt (USBHI), see section 8, Interrupt Controller (INTC). The host controller driver clears a specified bit in this register by writing 1 in the bit position to be cleared. The host controller driver cannot set any of these bits. The host controller never clears bits. Rev. 1.00, 02/04, page 518 of 804 Bit 31 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to this bit. 30 OC 0 R/W Ownership Change This bit is set when the OCR bit in the HcCommandStatus register is set by the host controller driver. This event generates a system management interrupt (SMI) at once when not masked. When there is no SMI pin, this bit is cleared to 0. 0: The OCR bit in the HcCommandStatus register is not set. 1: The OCR bit in the HcCommandStatus register is set. 29 to 7 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 6 RHSC 0 R/W Root Hub Status Change This bit is set when the content of the HcRhStatus register or the content of any HcRhPortStatus register [Number of Downstream Port] has changed. 0: The content of the HcRhStatus register or HcRhPortStatus register is not changed. 1: The content of the HcRhStatus register or HcRhPortStatus register is changed. 5 FNO 0 R/W Frame Number Overflow This bit is set when MSB (bit 15) in the HcFmNumber register changes value from 0 to 1 or from 1 to 0 or after HccaFrameNumber is updated. 0: MSB in the HcFmNumber register or HccaFrameNumber is not updated. 1: MSB in the HcFmNumber register or HccaFrameNumber is updated. 4 UE 0 R/W Unrecoverable Error This bit is set when the host controller detects a system error that is not related to USB. The host controller driver clears this bit after the host controller is reset. 0: System error has not generated yet. 1: System error is detected. Rev. 1.00, 02/04, page 519 of 804 Bit 3 Bit Name RD Initial Value 0 R/W R/W Description Resume Detected This bit is set when the host controller detects that the USB device outputs a resume signal. This bit is not set when the host controller driver sets the USB Resume state. 0: The resume signal is not detected. 1: The resume signal is detected. 2 SF 0 R/W Start of Frame This bit is set by the host controller when each frame starts and after HccaFrameNumber is updated. The host controller simultaneously generates the SOF token. 0: Each frame has not initiated or HccaFrameNumber is not updated. 1: Initiation of each frame and updating of HccaFrameNumber 1 WDH 0 R/W Write back Done Head This bit is set immediately after the host controller has written HcDoneHead to HccaDoneHead. HccaDoneHead is not updated until this bit is cleared. The host controller driver should clear this bit only after the content of HccaDoneHead has been stored. 0: When cleared after set to 1. 1: When HcDoneHead is written to HccaDoneHead. 0 SO 0 R/W Scheduling Overrun This bit is set when the USB schedule has overrun after HccaFrameNumber has updated in the current frame. SchedulingOverrun also increments the SOC0 and SOC1 bits in the HcCommandStatus register. 0: The USB schedule has not overrun. 1: The USB schedule has overrun. Rev. 1.00, 02/04, page 520 of 804 19.3.5 HcInterruptEnable Register (HIER) Each enable bit in HIER controls whether to generate an interrupt by an event related to the HcInterruptStatus register. A hardware interrupt is requested to the CPU when an event bit in the HcInterruptStatus register is set, a corresponding bit in the HcInterruptEnable register is set, and the MasterInterruptEnable (MIE) bit is set. As a result, the exception code (H'A00) of the host controller interrupt (USBHI) is set in the interrupt event register 2 (INTEVT2) and the exception handling is started (the USBHI exception code is used in common regardless of the content of the interrupt generation event). Therefore, the USBHI exception code can be used when an interrupt generation is detected by the host controller driver. For details on the interrupt event register 2 (INTEVT2), see section 4, Exception Handling, and for details on the exception code and interrupt processing of the host controller interrupt (USBHI), see section 8, Interrupt Controller (INTC). Writing 1 in this register sets the corresponding bit, while writing 0 does not change it. When the specified bit needs to be set, writing data in which only the corresponding bit is 1 enables the bit to be set independently without checking the states of other bits. HIER is in conjunction with the HcInterruptDisable register which is described later. Therefore when a specific bit needs to be cleared to 0, writing 1 to the corresponding bit in the HcInterruptDisable register automatically clears the corresponding bit in this register. Bit 31 Bit Name MIE Initial Value 0 R/W R/W Description Master Interrupt Enable When this bit is set to 1, an interrupt generation by the event specified in another bit in this register is enabled. This is used by the host controller driver so that the master interrupt is enabled. When 1 is written to the MIE bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the event specified by other bit. 30 OC 0 R/W Ownership Change Interrupt Enable When this bit is set to 1, an interrupt generation by the Ownership Change event is enabled. When 1 is written to the OC bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the Ownership Change event. Rev. 1.00, 02/04, page 521 of 804 Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 29 to 7 -- 6 RHSC 0 R/W Root Hub Status Change Interrupt Enable When this bit is set to 1, an interrupt generation by the Root Hub Status Change event is enabled. When 1 is written to the RHSC bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the Root Hub Status Change event. 5 FNO 0 R/W Frame Number Overflow Interrupt Enable When this bit is set to 1, an interrupt generation by the Frame Number Overflow event is enabled. When 1 is written to the FNO bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the Frame Number Overflow event. 4 UE 0 R/W Unrecoverable Error Interrupt Enable When this bit is set to 1, an interrupt generation by the Unrecoverable Error event is enabled. When 1 is written to the UE bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the Unrecoverable Error event. 3 RD 0 R/W Resume Detected Interrupt Enable When this bit is set to 1, an interrupt generation by the Resume Detected event is enabled. When 1 is written to the RD bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the Resume Detected event. Rev. 1.00, 02/04, page 522 of 804 Bit 2 Bit Name SF Initial Value 0 R/W R/W Description Start of Frame Interrupt Enable When this bit is set to 1, an interrupt generation by the Start of Frame event is enabled. When 1 is written to the SF bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the Start of Frame event. 1 WDH 0 R/W WriteBack Done Head Interrupt Enable When this bit is set to 1, an interrupt generation by the WriteBack Done Head event is enabled. When 1 is written to the WDH bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the WriteBack Done Head event. 0 SO 0 R/W Scheduling Overrun Interrupt Enable When this bit is set to 1, an interrupt generation by the SchedulingOverrun event is enabled. When 1 is written to the SO bit in the HcInterruptDisable register, this bit is cleared to 0. 0: This bit is ignored. 1: Enables interrupt generation due to the SchedulingOverrun event. Rev. 1.00, 02/04, page 523 of 804 19.3.6 HcInterruptDisable Register (HIDR) Each disable bit in HIDR controls whether to mask an interrupt by an event related to the HcInterruptStatus register. A hardware interrupt is not requested to the CPU when an event bit in the HcInterruptStatus register is set and a corresponding bit in the HcInterruptDisable register is set or the MIE bit in the HcInterruptDisable register is set. Writing 1 in this register clears the corresponding bit in the HcInterruptEnable register (disable state), while writing 0 does not change it. When the specified bit is disabled, writing data in which only the corresponding bit is 1 enables the bit to be disabled independently without checking the states of other bits. HIDR is in conjunction with the HcInterruptEnable register which is described before. Therefore when the specified bit needs to be cleared to 0 (enable state), writing 1 in the corresponding bit in the HcInterruptEnable register enables the corresponding bit in this register to be automatically cleared to 0. When this register is read, the current value of the HcInterruptEnable register is returned. Bit 31 Bit Name MIE Initial Value 0 R/W R/W Description Master Interrupt Disable When this bit is set to 1, an interrupt generation by the event specified in another bit in this register is masked. When 1 is written to the MIE bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the event specified by other bit. 30 OC 0 R/W Ownership Change Interrupt Disable When this bit is set to 1, an interrupt generation by the Ownership Change event is masked. When 1 is written to the OC bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the Ownership Change event. 29 to 7 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. Rev. 1.00, 02/04, page 524 of 804 Bit 6 Bit Name RHSC Initial Value 0 R/W R/W Description Root Hub Status Change Interrupt Disable When this bit is set to 1, an interrupt generation by the Root Hub Status Change event is masked. When 1 is written to the RHSC bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the Root Hub Status Change event. 5 FNO 0 R/W Frame Number Overflow Interrupt Disable When this bit is set to 1, an interrupt generation by the Frame Number Overflow event is masked. When 1 is written to the FNO bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the Frame Number Overflow event. 4 UE 0 R/W Unrecoverable Error Interrupt Disable When this bit is set to 1, an interrupt generation by the Unrecoverable Error event is masked. When 1 is written to the UE bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the Unrecoverable Error event. 3 RD 0 R/W Resume Detected Interrupt Disable When this bit is set to 1, an interrupt generation by the Resume Detected event is masked. When 1 is written to the RD bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the Resume Detected event. 2 SF 0 R/W Start of Frame Interrupt Disable When this bit is set to 1, an interrupt generation by the Start of Frame event is masked. When 1 is written to the SF bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the Start of Frame event. Rev. 1.00, 02/04, page 525 of 804 Bit 1 Bit Name WDH Initial Value 0 R/W R/W Description WriteBack Done Head Interrupt Disable When this bit is set to 1, an interrupt generation by the WriteBack Done Head event is masked. When 1 is written to the WDH bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the WriteBack Done Head event. 0 SO 0 R/W Scheduling Overrun Interrupt Disable When this bit is set to 1, an interrupt generation by the SchedulingOverrun event is masked. When 1 is written to the SO bit in the HcInterruptEnable register, this bit is cleared to 0. 0: This bit is ignored. 1: Disables interrupt generation due to the SchedulingOverrun event. 19.3.7 HcHCCA Register (HHCCAR) HHCCAR includes physical addresses in the host controller communication area. The host controller driver determines the alignment limitation by writing 1 to all bits in the HcHCCA register and by reading the content of the HcHCCA register. Alignment is determined by checking the number of 0 in the lower bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must always be 0 when they are read. This area is used to retain the control structure and interrupt table that are accessed by the host controller and host controller driver. Bit Bit Name Initial Value All 0 All 0 R/W R/W R Description These bits are physical addresses in the Host Controller Communication Area. These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 31 to 8 HCCA 7 to 0 -- Rev. 1.00, 02/04, page 526 of 804 19.3.8 HcPeriodCurrentED Register (HPCEDR) HPCEDR includes a physical address of the current isochronous ED or interrupt ED. Bit Bit Name Initial Value All 0 R/W R Description Period Current ED These bits are physical addresses of the current isochronous ED or interrupt ED. 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 31 to 4 PCED 19.3.9 HcControlHeadED Register (HCHEDR) HCHEDR includes a physical address of the first ED in the control list. Bit Bit Name Initial Value All 0 R/W R/W Description Control Head ED These bits are physical addresses of the first ED in the control list. 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 31 to 4 CHED 19.3.10 HcControlCurrentED Register (HCCEDR) HCCEDR includes a physical address of the current ED in the control list. Bit Bit Name Initial Value All 0 R/W R/W Description Control Current ED These bits are physical addresses of the current ED in the control list. 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. Rev. 1.00, 02/04, page 527 of 804 31 to 4 CCED 19.3.11 HcBulkHeadED Register (HBHEDR) HBHEDR includes a physical address of the first ED in the bulk list. Bit Bit Name Initial Value All 0 R/W R/W Description Bulk Head ED These bits are physical addresses of the first ED in the bulk list. 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 31 to 4 BHED 19.3.12 HcBulkCurrentED Register (HBCEDR) HBCEDR includes a physical address of the current ED in the bulk list. When the bulk list is supplied by the round robin method, endpoints are ordered to the list according to these insertions. Bit Bit Name Initial Value All 0 R/W R/W Description Bulk Current ED These bits are physical addresses of the current ED in the bulk list. 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 31 to 4 BCED 19.3.13 HcDoneHeadED Register (HDHEDR) HDHEDR includes a physical address of the finally completed TD added to the done queue. The host controller driver need not read this register so that the content is written to HCCA periodically in normal operation. Bit Bit Name Initial Value All 0 R/W R Description Done Head These bits are physical addresses of the finally completed TD added to the done queue. 31 to 4 DH Rev. 1.00, 02/04, page 528 of 804 Bit 3 to 0 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 19.3.14 HcFmInterval Register (HFIR) HFIR includes a 14-bit value indicating the bit time interval of the frame (i.e., between two serial SOFs) and a 15-bit value indicating the maximum packet size at a full speed that is transmitted and received by the host controller without causing SchedulingOverrun. The host controller driver adjusts the frame interval minutely by writing a new value over the current value in each SOF. Bit 31 Bit Name FIT Initial Value 0 R/W R/W Description Frame Interval Toggle This bit is toggled by the host controller driver whenever it loads a new value into the Frame Interval bits. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15, 14 FSMPS14 0 FSMPS13 0 FSMPS12 0 FSMPS11 0 FSMPS10 0 FSMPS9 FSMPS8 FSMPS7 FSMPS6 FSMPS5 FSMPS4 FSMPS3 FSMPS2 FSMPS1 FSMPS0 -- 0 0 0 0 0 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. FSLargest Data Packet These bits specify a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value expresses the largest data amount of the bit that can be transmitted and received in one transaction by the host controller at any given time without causing SchedulingOverrun. The field value is calculated by the host controller driver. Rev. 1.00, 02/04, page 529 of 804 Bit 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name FI13 FI12 FI11 FI10 FI9 FI8 FI7 FI6 FI5 FI4 FI3 FI2 FI1 FI0 Initial Value 1 0 1 1 1 0 1 1 0 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Frame Interval These bits specify the interval between two serial SOFs with bit times. The nominal value is set to H'2EDF (11999). The host controller driver must store the current value of this field before resetting the host controller. With this procedure, this bit is reset to its nominal value by the host controller by setting the HCR bit in the HcCommandStatus register. The host controller driver can select to restore the stored value at the completion of the reset sequence. Rev. 1.00, 02/04, page 530 of 804 19.3.15 HcFmRemaining Register (HFRR) HFRR is a 14-bit down counter indicating the bit time remaining in the current frame. Bit 31 Bit Name FRT Initial Value 0 R/W R Description Frame Remaining Toggle This bit is always loaded from the FIT bit in the HcFmInterval register when the FR bits reach 0. This bit is used by the host controller driver for synchronization between the FrameInterval and FrameRemaining registers. 30 to 14 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FR13 FR12 FR11 FR10 FR9 FR8 FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R Frame Remaining These counters are decremented at each bit time. When these counters reach 0, these counters are reset by loading the value of the Frame Interval bit specified in the HcFmInterval register at the next bit time boundary. When the host controller transits to the USB Operational state, it reads the FI bits in the HcFmInterval register again and uses the updated value from the next SOF. Rev. 1.00, 02/04, page 531 of 804 19.3.16 HcFmNumber Register (HFNR) HFNR is a 16-bit counter. It indicates the reference of timing between events occurring in the host controller and host controller driver. The host controller driver uses a 16-bit value specified in this register and generates a 32-bit frame number without necessity for a frequent access to the register. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FN15 FN14 FN13 FN12 FN11 FN10 FN9 FN8 FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Frame Number These bits are incremented when the HcFmRemaining register is reloaded. The count will return to H'0 after reaching H'FFFF. When the host controller transits to the USB Operational state, these bits are automatically incremented. After the host controller increments the FN15 to FN0 bits and sends SOF in each frame boundary, the content is written to HCCA before the host controller reads the first ED in the frame. After writing to HCCA, the host controller sets the SF bit in the HcInterruptStatus register. 31 to 16 -- Rev. 1.00, 02/04, page 532 of 804 19.3.17 HcPeriodicStart Register (HPSR) HPSR has a 14-bit programmable value, which determines the earliest time when the host controller should start to process the periodic list. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PS13 PS12 PS11 PS10 PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Periodic Start This field is cleared after the hardware reset. Then this field is set by the host controller driver while the host controller performs initial settings. This value is roughly calculated as 10% off from the HcFmInterval register. The normal value is H '2A2F. When the HcFmRemaining register reaches the specified value, the processing of the periodic list has a higher priority than the control/bulk processing. Consequently, the host controller starts to process the periodic list after the completion of the current control/bulk transaction. 31 to 14 -- Rev. 1.00, 02/04, page 533 of 804 19.3.18 HcLSThreshold Register (HLSTR) HLSTR includes an 12-bit value that is used by the host controller to determine whether or not to authorize the transfer of the LS packed 8 bytes in maximum before EOF. The host controller and host controller driver cannot change this value. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 11 10 9 8 7 6 5 4 3 2 1 0 LST11 LST10 LST9 LST8 LST7 LST6 LST5 LST4 LST3 LST2 LST1 LST0 0 1 1 0 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LSThreshold This field contains a value to be compared with the FR bits prior to the beginning of low-speed transaction. The transaction is started only when the FR bit value is beyond the value of this bit. The value is calculated by the host controller driver considering the transmission and set-up overhead. 31 to 12 -- Rev. 1.00, 02/04, page 534 of 804 19.3.19 HcRhDescriptorA Register (HRDRA) HRDRA is the first register of two registers describing the features of the root hub. The descriptor length (11), descriptor type (T.B.D), and the hub controller current bit (0) of the class descriptor of the hub are emulated by the host controller driver. All other bits are placed in the HcRhDescriptorA register and HcRhDescriptorB register. Bit 31 30 29 28 27 26 25 24 Bit Name POTPGT7 POTPGT6 POTPGT5 POTPGT4 POTPGT3 POTPGT2 POTPGT1 POTPGT0 Initial Value 0 0 0 0 0 0 1 0 All 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 12 NOCP 1 R/W No Over Current Protection This bit selects how the overcurrent status of the root hub port is reported. When this bit is cleared, the OCPM bit specifies global report or report at each port. 0: Overcurrent status is collectively reported for all downstream ports. 1: Overcurrent protection is not supported. 11 OCPM 0 R/W Over Current Protection Mode This bit selects how the overcurrent status in the roothub port is reported. At reset, this bit reflects the same mode as the PSM bit. When the NOCP bit is cleared, this bit is valid. 0: Overcurrent status is collectively reported for all downstream ports. 1: Overcurrent status is reported for each port. 10 DT 0 R DeviceType This bit indicates that the route hub is not a compound device. This bit should always be set to 0. Description Power On To Power Good Time These bits specify the waiting time until a host controller driver access the power-on port of the root hub. These bits are implementation specific. The unit of time is 2 ms. The time is calculated as POTPGT x 2 ms. 23 to 13 -- Rev. 1.00, 02/04, page 535 of 804 Bit 9 Bit Name NPS Initial Value 1 R/W R/W Description No Power Switching This bit selects whether the power switching is supported or ports are always power-supplied. This bit is implementation specific. When this bit is cleared, the PSM bit specifies the global/port switching. Note: Because the initial value is 1, first clear this bit (write 0 with the host controller driver) to enable power switching of the port. 0: Ports can be power-switched. 1: Ports are always powered on when the host controller is powered on. 8 PSM 0 R/W Power Switching Mode This bit specifies how the power switching of the root-hub port is controlled. This bit is implementation specific. This bit is valid only when the NPS bit is cleared. 0: All ports are simultaneously power-supplied. 1: Each port is power-supplied individually. In this mode, the port power is controlled with either of global/port switching. When the PPCM bit in the HcRhDescriptorB register is set, the port is reacted only to the portpower command (set/clear port power). When the port mask is cleared, the port is controlled only by the global power-switch (set/clear global power). 7 6 5 4 3 2 1 0 NDP7 NDP6 NDP5 NDP4 NDP3 NDP2 NDP1 NDP0 0 0 0 0 0 0 1 0 R R R R R R R R Number Downstream Ports These bits specify the number of downstream ports supported by the root hub. These bits are implementation specific. The minimum number of ports is 1. The maximum number of ports which are supported by the OpenHCI is 15. Rev. 1.00, 02/04, page 536 of 804 19.3.20 HcRhDescriptorB Register (HRDRB) HRDRB is the second register of two registers describing the features of the root hub. These bits must be set during the initial setting so as to correspond to the system implementation. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 17 PPCM 0 R/W Port Power Control Mask This bit indicates whether the port is influenced by the global power-control command when the PSM bit in the HcRhDescriptorA register is set. When this bit is set, the power state of the port is affected by the power control at each port (set/clear port power). When this bit is cleared, the port is controlled by the global power switch (set/clear global power). If the device is placed in global switching mode (PSM bit = 0), this bit is not valid. Note: Clear the NPS bit in the HcRhDescriptorA register so that the power to all ports is off (PortPowerStatus = 0), then set this bit. 0: Ports are controlled by the global power switch. 1: Port#1 is affected by the power control at each port. 16 to 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 1 DR 0 R/W Device Removable This bit is dedicated to the ports of the root hub. When this bit is cleared, the set device becomes removable. When this bit is set, do not remove the set device. 0: Device attached to port#1 is removable. 1: Device attached to port#1 is not removable. 0 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to this bit. 31 to 18 -- Rev. 1.00, 02/04, page 537 of 804 19.3.21 HcRhStatus Register (HRSR) HRSR is divided into two parts. The lower word of a longword indicates the hub status bits and the upper word indicates the hub status change bit. The reserved bits should be set to 0. Bit 31 Bit Name CRWE Initial Value 0 R/W W Description Clear Remote Wakeup Enable Writing 1 clears this bit. When this bit is set to 0, this bit is not cleared. 30 to 18 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 17 OCIC 0 R/W Over Current Indicator Change When the OCI field in this register is changed, this bit is set by the host controller. Writing 1 by the host controller driver clears this bit. When this bit is set to 0, this bit is not cleared. 16 LPSC 0 R/W (Read) Local Power Status Change The root hub does not support the local power status function. Therefore, this bit is always read as 0. (Write) Set Global Power This bit is written to 1 to power on (sets the PPS bit in the HcRhPortStatus register) all ports in global power mode (PSM bit in the HcRhDescriptorA register = 0). This bit sets the PPS bit only to the port in which the PPCM bit in the HcRhDescriptorB register is not set in power mode at each port. When 0 is written to, this bit is not cleared. 15 DRWE 0 R/W (Read) Device Remote Wakeup Enable This bit enables the CSC bit in the HcRhPortStatus register as a resume event and generates the state transition from USB Suspend to USB Resume and the Resume Detected interrupt. 0: Connect Status Change is not the Remote Wakeup event. 1: Connect Status Change is the Remote Wakeup event. (Write) Set Remote Wakeup Enable Writing 1 sets this bit. When 0 is written to, this bit is not set. Rev. 1.00, 02/04, page 538 of 804 Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 14 to 2 -- 1 OCI 0 R/W Over Current Indicator This bit reports the overcurrent condition when the global report is performed. When this bit is set, an overcurrent condition exists. When this bit is cleared, all power operations are normal. This bit is always 0 when the overcurrent protection at each port is carried out. 0: All power operations are normal. 1: An overcurrent condition exists. 0 LPS 0 R/W (Read) Local Power Status The root hub does not support the local power status function. Therefore, this bit is always read as 0. (Write) Clear Global Power This bit is written to 1 to power off (clears the PPS bit in the HcRhPortStatus register) all ports in global power mode (PSM bit in the HcRhDescriptorA register = 0). In power mode at each port, the PPS bit is cleared to the port in which the PPCM bit in the HcRhDescriptorB register is not set. When 0 is written to, this bit is invalid. Rev. 1.00, 02/04, page 539 of 804 19.3.22 HcRhPortStatus Register (HRPSR) HRPSR is used for base-controlling each port and to report the port event. The lower word is used to reflect the port status while the upper word reflects the status change. Some status bits have special writing (see below). If the transaction (token that passes the hand shake) is in progress while a write to ChangePortStatus occurs, the resultant port status change must be postponed until the completion of the transaction. Always write reserved bits to 0. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 20 PRSC 0 R/W Port Reset Status Change This bit is set when the 10 ms port reset signal has completed. Writing 1 by the host controller driver clears this bit. When this bit is written to 0, this bit is not cleared. 0: Port reset is not completed. 1: Port reset is completed. 19 OCIC 0 R/W Port Over Current Indicator Change This bit is valid when an overcurrent condition is reported on the base of each port. This bit is set when the root hub changes the POCI bit. Writing 1 by the host controller driver clears this bit. When this bit is written to 0, this bit is not cleared. 0: Port Over Current Indicator has not changed. 1: Port Over Current Indicator has changed. 18 PSSC 0 R/W Port Suspend Status Change This bit is set when all resume sequences have completed. These sequences include 20 ms resume pulse, LS EOP, and 3 ms resychronization delay. Writing 1 by the host controller driver clears this bit. When this bit is written to 0, this bit is not cleared. When the PRSC bit is set, this bit is cleared. 0: Resume sequence has not completed. 1: Resume sequence has completed. 31 to 21 -- Rev. 1.00, 02/04, page 540 of 804 Bit 17 Bit Name PESC Initial Value 0 R/W R/W Description Port Enable Status Change This bit is set when the PES bit is cleared due to a hardware event. This bit is not set by the change of writing of the host controller driver. Writing 1 by the host controller driver clears this bit. When this bit is written to 0, this bit is not cleared. 0: Port Enable Status has not changed. 1: Port Enable Status has changed. 16 CSC 0 R/W Connect Status Change This bit is set whenever the connection or disconnection event occurs. Writing 1 by the host controller driver clears this bit. When this bit is written to 0, this bit is not cleared. If the CCS bit is cleared when Set Port Reset, Set Port Enable, or Set Port Suspend is written to, writing when the power supply of the port is disconnected does not occur, so this bit is set to report the driver to re-evaluate the connection status. Note: If the DR bit in the HcRhDescriptorB register is set, this bit is set only after the root hub reset to report the system that a device can be attached. 0: Current Connect Status has not changed. 1: Current Connect Status has changed. 15 to 10 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. 9 LSDA 0 R/W (Read) Low Speed Device Attached This bit indicates the speed of the device attached to this port. When this bit is set, a low-speed device is attached to this port. When this bit is cleared, a full-speed device is attached to this port. This bit is valid only when the CCS bit is set. 0: A full-speed device is attached. 1: A low-speed device is attached. (Write) Clear Port Power Writing 1 by the host controller driver clears the PPS bit. When this bit is written to 0, this bit is not cleared. Rev. 1.00, 02/04, page 541 of 804 Bit 8 Bit Name PPS Initial Value 1 R/W R/W Description (Read) Port Power Status This bit reflects the power status of the port regardless of power switching mode to be executed. However, because the initial value of the No Power Switching bit in the HcRhDescriptorA register is 1, this bit is first fixed to 1. The No Power Switching bit must first be cleared when power is switched, as shown below. When an overcurrent condition is detected, this bit is cleared. Writing Set Port Power or Set Global Power by the host controller driver sets this bit. Also, writing Clear Port Power or Clear Global Power by the host controller driver clears this bit. The PSM bit in the HcRhDescriptorA register and the PPCM bit in the HcRhDescriptorB register determine which power control switch can be used. Only Set/Clear Global Power controls this bit in global switching mode (PSM bit = 0). If the PPCM bit of that port is set in power switching mode (PSM bit = 1), only the Set/Clear Port Power command is enabled. If the mask is not set, only the Set/Clear Global Power command is enabled. When the port power is disabled, the CCS, PES, PSS, and PRS bits are reset. Note: If power switching mode is not supported, this bit is always read as 1. 0: Port power is off. 1: Port power is on. (Write) Set Port Power Writing 1 by the host controller driver sets the PPS bit. When this bit is written to 0, this bit is not set. 7 to 5 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. The operation is not guaranteed if 1 is written to these bits. Rev. 1.00, 02/04, page 542 of 804 Bit 4 Bit Name PRS Initial Value 0 R/W R/W Description (Read) Port Reset Status When this bit is set by writing to Set Port Reset, the port reset signal is output. This bit is cleared when the PRSC bit is set upon completion of a reset. When the CCS bit is cleared, this bit is not set. 0: Port reset signal is not active. 1: Port reset signal is active. (Write) Set Port Reset Writing 1 by the host controller driver sets the port reset signal. When this bit is written to 0, this bit is not set. When the CCS bit is cleared, this write does not set the PRS bit, instead, sets the CSC bit. This reports a reset of the disconnection port to the driver. 3 POCI 0 R/W (Read) Port Over Current Indicator This bit is valid only when a root hub is placed in such a way that an overcurrent condition is reported on the base of each port. If the overcurrent report at each port is not supported, this bit is cleared to 0. If this bit is cleared, all power controls are normal in this port. If this bit is set, an overcurrent state exists in this port. This bit always reflects an overcurrent input signal. 0: No overcurrent state. 1: Overcurrent state is detected. (Write) Clear Suspend Status Writing 1 by the host controller driver initiates a resume. When this bit is written to 0, this bit is invalid. If the PSS bit is set, a resume is initiated. Rev. 1.00, 02/04, page 543 of 804 Bit 2 Bit Name PSS Initial Value 0 R/W R/W Description (Read) Port Suspend Status This bit indicates that the port is under the process to suspend or during the resume sequence. Writing Set Suspend State sets this bit and setting the PSSC bit clears this bit at the end of the resume interval. If the CCS bit is cleared, this bit cannot be set. When the PRSC bit is set upon completion of the port reset or the host controller is placed in the USB resume state, this bit is cleared. If an upstream resume is in progress, it is transmitted to the host controller. 0: Port is not suspended. 1: Port is suspended. (Write) Set Port Suspend Writing 1 by the host controller driver sets the PSS bit. When this bit is written to 0, this bit is not set. In addition, when the CCS bit is cleared, the PSS bit is not set by this writing. Instead, the CSC bit is set. This reports the suspended state of the disconnection port to the driver. 1 PES 0 R/W (Read) Port Enable Status This bit indicates whether the port is enabled or disabled. The root hub clears this bit when the overcurrent condition and an operational bus error such as disconnect event, power-off switch, or babble are detected. The PESC bit is set by this change. This bit is set by writing Set Port Enable and cleared by writing Clear Port Enable. This bit cannot be set when the CCS bit is cleared. In addition, this bit is set upon completion of the port reset by which the PRSC bit is set, or upon completion of the port suspend by which the PSSC bit is set. 0: Port disabled. 1: Port enabled. (Write) Set Port Enable Writing 1 by the host controller driver sets the PES bit. When this bit is written to 0, this bit is not set. If the CCS bit is cleared, this writing does not set the PES bit, instead, sets the CSC bit. This reports the driver that the disconnection port has been tried to be enabled. Rev. 1.00, 02/04, page 544 of 804 Bit 0 Bit Name CCS Initial Value 0 R/W R/W Description (Read) Current Connect Status This bit indicates the current status of the downstream port. Note: If the set device is not removable (DeviceRemovable), this bit is always read as 1. 0: No device connected. 1: Device connected. (Write) Clear Port Enable Writing 1 by the host controller driver clears the PES bit. When this bit is written to 0, this bit is not cleared. The CCS bit is not affected by any writing. Rev. 1.00, 02/04, page 545 of 804 19.4 19.4.1 Data Storage Format of USB Host Controller Storage Format of Transferred Data The data storage format (endian) of the USB host controller is in conjunction with the CPU endian specification by the MD5 pin. Therefore, when the CPU is operated as big endian, transfer data of the USB host controller must be treated in big-endian order. When the CPU is operated as little endian, transfer data of the USB host controller must be treated in little-endian order. 19.4.2 Storage Format of Descriptor ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of the USB host controller must be aligned so that each Dword corresponds to the longword boundary (addresses 4n to 4n + 3) of the memory. In this case, the difference of endian has no influence. 19.5 19.5.1 Usage Restrictions of USB Host Controller Restriction of Reset Control Following procedure should be used when the software reset is issued ( the HCR bit of the HCSR register is set to 1) while USB state is Operational, or when the USB state is shifted from the Operational state to the Reset state ( the HCFS1/0 bit of the HCTLR register is cleared to 00). 1. Each list processing is discontinued. (The BLE bit, the CLE bit, the IE bit, and the PLE bit of the HCTLR register are cleared to 0. ) 2. Wait until the SOF interrupt from the USB host controller is detected twice. (SF bit interrupt of HISR register) 3. Put the USB into the Suspend state by setting the HCFS1/0 bits of the HCTLR register to 11. 4. The reset processing is executed. Rev. 1.00, 02/04, page 546 of 804 Section 20 USB Function Controller (USBF) This LSI incorporates an USB function controller (USBF). 20.1 Features * UDC (USB device controller) supporting USB 1.1 processes incorporated USB protocol automatically. Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Full-speed An arbitrary endpoint configuration can be set by specifying the endpoint number used by the USB host and the endpoint FIFO number (transfer method and transfer direction are fixed) provided by this USB function controller via the EPIRn0 to EPIRn5 registers. Endpoint Name Endpoint 0 Endpoint FIFO Transfer Type Abbreviation Number EP0s EP0i EP0o Endpoint 1 EP1 H'00 H'00 H'00 H'01 H'02 H'03 H'05 H'06 Setup Control-in Control-out Interrupt-in Bulk-in Bulk-out Isochronous-in FIFO Buffer Capacity DMA Maximum Transfer Application Packet Size (Byte) 8 64 64 16 64 64 64 8 64 64 16 128 128 128 120 -- -- -- -- Possible Possible -- -- AT command control, audio SD/MMC memory card Modem, packet Emulation Endpoint 2i EP2i Endpoint 2o EP2o Endpoint 3i EP3i Endpoint 3o EP3o Isochronous-out 60 Endpoint 4 Endpoint 5 Endpoint 6 EP4 EP5 EP6 H'07 H'08 H'09 Interrupt-in Bulk-in Bulk-out 16 32 32 16 64 64 -- Possible Possible * Interrupt requests: generates various interrupt signals necessary for USB transmission/reception * Clock: Selection of internal system clock/external input (48 MHz) by means of EXCPG * Power-down mode Power consumption can be reduced by stopping UDC internal clock when USB cable is disconnected Automatic transition to/recovery from suspend state * Power mode: Self-powered, bus-powered IFUSBF0A_000020020800 Rev. 1.00, 02/04, page 547 of 804 * Endpoint configuration: An arbitrary endpoint configuration can be set. (Endpoint configuration based on the Bluetooth specification standard is also supported.) EP0 Control (in,out) 64 bytes EP1 Interrupt (in) 16 bytes EP2 Bulk (in) 64 bytes EP2 Bulk (out) 64 bytes Configuration 1 Interface Number 0 Alternate Setting 0 Interface Number 1 Alternate Setting 0 EP3 lsoch (in) 0 byte EP3 lsoch (out) 0 byte EP3 lsoch (in) 9 bytes EP3 lsoch (out) 9 bytes EP3 lsoch (in) 17 bytes EP3 lsoch (out) 17 bytes EP3 lsoch (in) 25 bytes EP3 lsoch (out) 25 bytes EP3 lsoch (in) 33 bytes EP3 lsoch (out) 33 bytes EP3 lsoch (in) 49 bytes EP3 lsoch (out) 49 bytes Alternate Setting 1 Alternate Setting 2 Alternate Setting 3 Alternate Setting 4 Alternate Setting 5 Rev. 1.00, 02/04, page 548 of 804 Figure 20.1 shows the block diagram of USBF. Peripheral bus USB function controller Interrupt requests DMA transfer requests Status and control registers UDC Transceiver USB_P USB_N Clock (48 MHz) FIFO UDC: USB device controller Figure 20.1 Block Diagram of USB Function Controller 20.2 Input/Output Pins Table 20.1 lists the pin configuration of USBF. For further information on pin settings, see section 18, USB Pin Multiplex Controller (USBPM). Table 20.1 Pin Configuration Pin Name UCLK USB_PWR_EN/ USB_PULLUP USB_OVR_CRNT/ USB_VBUS USB_P USB_N I/O Input Output Function External clock pin Pin for directly inputting an external clock of 48 MHz Power enable pin/pull-up control pin Power-supply application enable control for USBH/pull-up control pin for USBF Input Over current pin/VBUS pin Over current detection for USBH/USB-cable connection monitor pin for USBF I/O I/O P pin Port transceiver D + pin N pin Port transceiver D - pin Rev. 1.00, 02/04, page 549 of 804 20.3 Register Descriptions USB has following registers. For the information on the addresses of these registers and the state of the register in each processing condition, see section 27, List of Registers. * * * * * * * * * * * * * * * * * * * * * * * * * * * Interrupt flag register 0 (IFR0) Interrupt select register 0 (ISR0) Interrupt enable register 0 (IER0) EP0i data register (EPDR0i) EP0o data register (EPDR0o) EP0s data register (EPDR0s) EP1 data register (EPDR1) EP2i data register (EPDR2i) EP2o data register (EPDR2o) EP3i data register (EPDR3i) EP3o data register (EPDR3o) EP4 data register (EPDR4) EP5 data register (EPDR5) EP6 data register (EPDR6) EP0o receive data size register (EPSZ0o) EP2o receive data size register (EPSZ2o) EP3o receive data size register (EPSZ3o) EP6 receive data size register (EPSZ6) Trigger register (TRG) Data status register (DASTS) FIFO clear register (FCLR) DMA transfer setting register (DMA) Endpoint stall register (EPSTL) Configuration value register (CVR) Time stamp register (TSR) Control register (CTLR) Endpoint information register (EPIRn0 to EPIRn5) Rev. 1.00, 02/04, page 550 of 804 20.3.1 Interrupt Flag Register 0 (IFR0) IFR0 is an interrupt flag register for EP0i, EP0o, EP1, EP2i, EP2o, EP3i, EP3o, and EP4 to EP6, bus reset, setup command reception, VBUS, SUS/RES, SOF, SETC, and SETI. When each flag is set to 1 and an interrupt is enabled in the corresponding bit of the interrupt enable register 0 (IER0), an interrupt occurs from the INT pin specified by the corresponding bit in the interrupt select register (ISR0). Interrupt requests and interrupt request signals can be specified by ISR0. Clearing is performed by writing 0 to the bit to be cleared. Writing 1 is not valid and nothing is changed. Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 30 BRST 0 R/W Bus reset [Setting condition] * * * 29 SETUP TS 0 R/W When a bus reset signal is detected on the USB bus. At a reset When 0 is written to by CPU [Clearing conditions] Setup command receive complete [Setting condition] * When 8-byte data that decodes the command by the function is normally received and an ACK handshake is returned to the host from the function. At a reset When 0 is written to by CPU [Clearing conditions] * * 28 VBUS MN 0 R* 2 USB Connection Status Status bit to monitor the USB_VBUS pin state. Reflects the state of the USB_VBUS pin. Rev. 1.00, 02/04, page 551 of 804 Bit 27 Initial Bit Name Value VBUSF 0 R/W R/W Description USB Disconnection Detection [Setting condition] * When the function is connected to the USB bus or disconnected from it. Note: The USB_VBUS pin of this module is used for detecting connection/disconnection. [Clearing conditions] * * At a reset When 0 is written to by CPU. 26 SURSS 0 R* 1 Suspend/Resume Status Status bit indicating the state of the bus 1: Suspend state 0: Normal state 25 SURES 0 R/W Suspend /Resume Detection [Setting condition] * When the bus transits from the normal state to the suspend state or from the suspend state to the normal state. At a reset When 0 is written to by CPU [Clearing conditions] * * 24 CFDN 0 R/W Endpoint Information Load Complete [Setting condition] * When setting the endpoint information written in the EPIR register is completed in this module. At a reset When 0 is written to by CPU [Clearing conditions] * * Note: This module operates normally as USB function module after the setting of the endpoint information is completed. Rev. 1.00, 02/04, page 552 of 804 Bit 23 Initial Bit Name Value SOF 0 R/W R/W Description SOF Packet [Setting condition] * * * When the SOF packet is detected. At a reset When 0 is written to by CPU [Clearing conditions] 22 SETC 0 R/W Set Configuration Command Detection [Setting condition] * * * When the Set Configuration command is detected. At a reset When 0 is written to by CPU [Clearing conditions] 21 SETI 0 R/W Set Interface Command Detection [Setting condition] * * * When the Set Interface command is detected. At a reset When 0 is written to by CPU [Clearing conditions] 20 EP6 FULL 0 R* 1 EP6 (Bulk out) FIFO Full [Setting condition] * The FIFO buffer of EP6 has a dual-buffer configuration, and this bit is set when at least one of the FIFO buffer is full. At a reset When both FIFO buffers are empty. [Setting conditions] * * Note: EP6 FULL is a status bit, and cannot be cleared. Rev. 1.00, 02/04, page 553 of 804 Bit 19 Bit Name Initial Value R/W R* 1 Description EP5 (Bulk in) FIFO Empty [Setting conditions] * * At a reset The FIFO buffer of EP5 has a dual-buffer configuration, and this bit is set when at least one of the FIFO buffer is empty. When both of FIFO buffers are not empty. EP5 EMPTY 1 [Clearing condition] * Note: EP5 EMPTY is a status bit, and cannot be cleared. 18 EP5 TR 0 R/W EP5 (Bulk in) Transfer Request [Setting condition] * When an IN token is received from the host to EP5 and both of FIFO buffers are empty. At a reset When 0 is written to by CPU [Clearing conditions] * * 17 EP4 TR 0 R/W EP4 (Int) Transfer Request [Setting condition] * When IN token is issued from the host to EP4 and the FIFO buffer is empty. At a reset When 0 is written to by CPU [Clearing conditions] * * 16 EP4 TS 0 R/W EP4 (Int) Transmit Complete [Setting condition] * When data is normally transferred from the function to the host and an ACK handshake is returned after the data to be transmitted to the host is written in EP4. At a reset When 0 is written to by CPU [Clearing conditions] * * Rev. 1.00, 02/04, page 554 of 804 Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 15, 14 13 EP3o TF 0 R/W EP3o (Iso out) Abnormal Reception Flag indicating the FIFO state of EP3o. Indicates the state of the FIFO buffer that was readable after the data reception is completed and the next SOF packet is received. [Setting condition] * When the transfer data from the host is abnormally received (packet error) by EP3o. At a reset When 0 is written to by CPU [Clearing conditions] * * 12 EP3o TS 0 R/W EP3o (Iso out) Normal Reception Flag indicating the FIFO state of EP3o. Indicates the state of the FIFO buffer that was readable after the data reception is completed and the next SOF packet is received. [Setting condition] * When the transfer data from the host is normally received by EP3o. At a reset When 0 is written to by CPU [Clearing conditions] * * 11 EP3i TR 0 R/W EP3i (Iso in) Transmit Request [Setting condition] * When the FIFO buffer to be transmitted when an IN token is issued from the host to EP3i is empty. At a reset When 0 is written to by CPU [Clearing conditions] * * Rev. 1.00, 02/04, page 555 of 804 Bit 10 Bit Name EP3i TS Initial Value 0 R/W R/W Description EP3i (Iso in) Normal Transmission Flag indicating the FIFO state of EP3i. After the SOF packet is received, the FIFO buffer is switched automatically. The FIFO buffer which has transmitted the data to the host in the previous frame (before SOF reception) can be written to from the CPU. This bit shows the transmitting state in front of this one. [Setting condition] When a transmission was carried out normally in the previous frame. [Clearing conditions] * * At a reset When 0 is written to by CPU 9, 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 7 EP2o FULL 0 R*1 EP2o (Bulk out) FIFO Full [Setting condition] The FIFO buffer of EP2o has a dual-buffer configuration, and this bit is set when at least one of the FIFO buffer is full. [Clearing conditions] * * At a reset When both FIFO buffers are empty. Note: EP2o FULL is a status bit, and cannot be cleared. 6 EP2i EMPTY 1 R*1 EP2i (Bulk in) FIFO Empty [Setting condition] * * At a reset The FIFO buffer of EP2i has a dual-buffer configuration, and this bit is set when at least one of the FIFO buffer is empty. [Clearing condition] When both FIFO buffers are not empty. Note: EP2i EMPTY is a status bit, and cannot be cleared. Rev. 1.00, 02/04, page 556 of 804 Bit 5 Initial Bit Name Value EP2i TR 0 R/W R/W Description EP2i (Bulk in) Transfer Request [Setting condition] * When an IN token is issued from the host to EP2i and both FIFO buffers are empty. At a reset When 0 is written to by CPU [Clearing conditions] * * 4 EP1 TR 0 R/W EP1 (Int) Transfer Request [Setting condition] * When IN token is issued from the host to EP1 and the FIFO buffer is empty. At a reset When 0 is written to by CPU [Clearing conditions] * * 3 EP1 TS 0 R/W EP1 (Int) Transmit Complete [Setting condition] * When data to be transmitted to the host is written to EP1, then data is normally transferred from the function to the host, and an ACK handshake is returned. At a reset When 0 is written to by CPU [Clearing conditions] * * 2 EP0o TS 0 R/W EP0o Receive Complete [Setting condition] * When data is normally received from the host to EP0o and an ACK handshake is returned from the function to the host. At a reset When 0 is written to by CPU [Clearing conditions] * * Rev. 1.00, 02/04, page 557 of 804 Bit 1 Initial Bit Name Value EP0i TR 0 R/W R/W Description EP0i Transfer Request [Setting condition] * When IN token is issued from the host to EP0i and the FIFO buffer is empty. At a reset When 0 is written to by CPU [Clearing conditions] * * 0 EP0i TS 0 R/W EP0i Transmit Complete [Setting condition] * When data to be transmitted to the host is written to EP0i, then data is normally transferred from the function to the host, and an ACK handshake is returned. At a reset When 0 is written to by CPU [Clearing conditions] * * Notes: 1. FIFO full bits of EP2o and EP6 and FIFO empty bits of EP2i and EP5 are status bits indicating the FIFO states, so they cannot be cleared. 2. The USB connection status (bit 28) is a bit indicating the state of the USB_VBUS pin, so it cannot be cleared. Output of an interrupt is not carried out either. 20.3.2 Interrupt Select Register 0 (ISR0) ISR selects the interrupt request pin to output the IFR0 interrupt. The USB function module has two interrupt request signals (INT0N and INT1N) to output an interrupt request to the interrupt controller (INTC). If the corresponding bit in ISR0 is cleared to 0, an INT0N interrupt request will be issued and an interrupt request is issued from the INT1N pin when set to 1. INT0N and INT1N interrupt request signals correspond to USBFI0 and USBFI1 of the interrupt controller (INTC), respectively. In the initial value, each of interrupt source of the interrupt flag register is issued from the INT0N interrupt request signal. Rev. 1.00, 02/04, page 558 of 804 Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 30 BRST IS 0 R/W BRST Interrupt Select 0: Outputs a BRST (bus reset) interrupt request from INT0N 1: Outputs a BRST (bus reset) interrupt request from INT1N 29 SETUP TS IS 0 R/W SETUP Interrupt Select 0: Outputs a SETUP(setup data receive complete) interrupt request from INT0N 1: Outputs a SETUP(setup data receive complete) interrupt request from INT1N 28 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 27 VBUSF IS 0 R/W VBUSF Interrupt Select 0: Outputs a VBUSF interrupt request from INT0N 1: Outputs a VBUSF interrupt request from INT1N 26 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 25 SURES IS 0 R/W SURES Interrupt Select 0: Outputs a SURES interrupt request from INT0N 1: Outputs a SURES interrupt request from INT1N 24 CFDN IS 0 R/W CFDN Interrupt Select 0: Outputs a CFDN interrupt request from INT0N 1: Outputs a CFDN interrupt request from INT1N 23 SOF IS 0 R/W SOF Interrupt Select 0: Outputs a SOF interrupt request from INT0N 1: Outputs a SOF interrupt request from INT1N Rev. 1.00, 02/04, page 559 of 804 Bit 22 Bit Name SETC IS Initial Value 0 R/W R/W Description SETC Interrupt Select 0: Outputs a SETC interrupt request from INT0N 1: Outputs a SETC interrupt request from INT1N 21 SETI IS 0 R/W SETI Interrupt Select 0: Outputs a SETI interrupt request from INT0N 1: Outputs a SETI interrupt request from INT1N 20 EP6 FULL IS 0 R/W EP6 FULL Interrupt Select 0: Outputs an EP6 FULL interrupt request from INT0N 1: Outputs an EP6 FULL interrupt request from INT1N 19 EP5 EMPTY IS 0 R/W EP5 EMPTY Interrupt Select 0: Outputs an EP5 EMPTY interrupt request from INT0N 1: Outputs an EP5 EMPTY interrupt request from INT1N 18 EP5 TR IS 0 R/W EP5 TR Interrupt Select 0: Outputs an EP5 TR (transfer request) interrupt request from INT0N 1: Outputs an EP5 TR transfer request) interrupt request from INT1N 17 EP4 TR IS 0 R/W EP4 TR Interrupt Select 0: Outputs an EP4 TR (transfer request) interrupt request from INT0N 1: Outputs an EP4 TR (transfer request) interrupt request from INT1N 16 EP4 TS IS 0 R/W EP4 TS Interrupt Select 0: Outputs an EP4 TS (receive complete) interrupt request from INT0N 1: Outputs an EP4 TS (receive complete) interrupt request from INT1N 15, 14 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 13 EP3o TF IS 0 R/W EP3o TF Interrupt Select 0: Outputs an EP3o TF interrupt request from INT0N 1: Outputs an EP3o TF interrupt request from INT1N Rev. 1.00, 02/04, page 560 of 804 Bit 12 Bit Name EP3o TS IS Initial Value 0 R/W R/W Description EP3o TS Interrupt Select 0: Outputs an EP3o TS (receive complete) interrupt request from INT0N 1: Outputs an EP3o TS (receive complete) interrupt request from INT1N 11 EP3i TR IS 0 R/W EP3i TR Interrupt Select 0: Outputs an EP3i TR (transfer request) interrupt request from INT0N 1: Outputs an EP3i TR (transfer request) interrupt request from INT1N 10 EP3i TS IS 0 R/W EP3i TS Interrupt Select 0: Outputs an EP3i TS (receive complete) interrupt request from INT0N 1: Outputs an EP3i TS (receive complete) interrupt request from INT1N 9, 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 7 EP2o FULL IS 0 R/W EP2o FULL Interrupt Select 0: Outputs an EP2o FULL interrupt request from INT0N 1: Outputs an EP2o FULL interrupt request from INT1N 6 EP2i EMPTY IS 0 R/W EP2i EMPTY Interrupt Select 0: Outputs an EP2i EMPTY interrupt request from INT0N 1: Outputs an EP2i EMPTY interrupt request from INT1N 5 EP2i TR IS 0 R/W EP2i TR Interrupt Select 0: Outputs an EP2i TR (transfer request) interrupt request from INT0N 1: Outputs an EP2i TR (transfer request) interrupt request from INT1N 4 EP1 TR IS 0 R/W EP1 TR Interrupt Select 0: Outputs an EP1 TR (transfer request) interrupt request from INT0N 1: Outputs an EP1 TR (transfer request) interrupt request from INT1N Rev. 1.00, 02/04, page 561 of 804 Bit 3 Bit Name EP1 TS IS Initial Value 0 R/W R/W Description EP1 TS Interrupt Select 0: Outputs an EP1 TS (receive complete) interrupt request from INT0N 1: Outputs an EP1 TS (receive complete) interrupt request from INT1N 2 EP0o TS IS 0 R/W EP0o TS Interrupt Select 0: Outputs an EP0oTS (receive complete) interrupt request from INT0N 1: Outputs an EP0o TS (receive complete) interrupt request from INT1N 1 EP0i TR IS 0 R/W EP0i TR Interrupt Select 0: Outputs an EP0i TR (transfer request) interrupt request from INT0N 1: Outputs an EP0i TR (transfer request) interrupt request from INT1N 0 EP0i TS IS 0 R/W EP0i TS Interrupt Select 0: Outputs an EP0i TS (receive complete) interrupt request from INT0N 1: Outputs an EP0i TS (receive complete) interrupt request from INT1N Rev. 1.00, 02/04, page 562 of 804 20.3.3 Interrupt Enable Register 0 (IER0) IER0 enables the interrupt requests of IFR0. When an interrupt flag is set to 1 while the corresponding bit of each interrupt enable bit of IFR0 is set to 1, the INT0N or INT1N pin set in the interrupt select register (ISR0) is asserted low and an interrupt request is issued. Bit 31 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 30 BRST IE 0 R/W BRST Interrupt Enable 0: Disables a BRST (bus reset) interrupt request 1: Enables a BRST (bus reset) interrupt request 29 SETUP TS IE 0 R/W SETUP TS Interrupt Enable 0: Disables a SETUP TS (setup data receive complete) interrupt request 1: Enables a SETUP TS (setup data receive complete) interrupt request 28 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 27 VBUSF IE 0 R/W VBUSF Interrupt Enable 0: Disables a VBUSF interrupt request 1: Enables a VBUSF interrupt request 26 0 R Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 25 SURES IE 0 R/W SURES Interrupt Enable 0: Disables a SURES interrupt request 1: Enables a SURES interrupt request 24 CFDN IE 0 R/W CFDN Interrupt Enable 0: Disables a CFDN interrupt request 1: Enables a CFDN interrupt request Rev. 1.00, 02/04, page 563 of 804 Bit 23 Bit Name SOF IE Initial Value 0 R/W R/W Description SOF Interrupt Enable 0: Disables a SOF interrupt request 1: Enables a SOF interrupt request 22 SETC IE 0 R/W SETC Interrupt Enable 0: Disables a SETC interrupt request 1: Enables a SETC interrupt request 21 SETI IE 0 R/W SETI Interrupt Enable 0: Disables a SETI interrupt request 1: Enables a SETI interrupt request 20 EP6 FULL IE 0 R/W EP6 FULL Interrupt Enable 0: Disables an EP6 FULL interrupt request 1: Enables an EP6 FULL interrupt request 19 EP5 EMPTY IE 0 R/W EP5 EMPTY Interrupt Enable 0: Disables an EP5 EMPTY interrupt request 1: Enables an EP5 EMPTY interrupt request 18 EP5 TR IE 0 R/W EP5 TR Interrupt Enable 0: Disables an EP5 TR (transfer request) interrupt request 1: Enables an EP5 TR (transfer request) interrupt request 17 EP4 TR IE 0 R/W EP4 TR Interrupt Enable 0: Disables an EP4 TR (transfer request) interrupt request 1: Enables an EP4 TR (transfer request) interrupt request 16 EP4 TS IE 0 R/W EP4 TS Interrupt Enable 0: Disables an EP4 TS (receive complete) interrupt request 1: Enables an EP4 TS (receive complete) interrupt request 15, 14 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 564 of 804 Bit 13 Bit Name EP3o TF IE Initial Value 0 R/W R Description EP3o TF Interrupt Enable 0: Disables an EP3o TF interrupt request 1: Enables an EP3o TF interrupt request 12 EP3o TS IE 0 R EP3o TS Interrupt Enable 0: Disables an EP3o TS (receive complete) interrupt request 1: Enables an EP3o TS (receive complete) interrupt request 11 EP3i TR IE 0 R/W EP3i TR Interrupt Enable 0: Disables an EP3i TR (transfer request) interrupt request 1: Enables an EP3i TR (transfer request) interrupt request 10 EP3i TS IE 0 R/W EP3i TS Interrupt Enable 0: Disables an EP3i TS (receive complete) interrupt request 1: Enables an EP3i TS (receive complete) interrupt request 9, 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 7 EP2o FULL IE 0 R/W EP2o FULL Interrupt Enable 0: Disables an EP2o FULL interrupt request 1: Enables an EP2o FULL interrupt request 6 EP2i EMPTY IE 0 R/W EP2i EMPTY Interrupt Enable 0: Disables an EP2i EMPTY interrupt request 1: Enables an EP2i EMPTY interrupt request 5 EP2i TR IE 0 R/W EP2i TR Interrupt Enable 0: Disables an EP2i TR (transfer request) interrupt request 1: Enables an EP2i TR (transfer request) interrupt request Rev. 1.00, 02/04, page 565 of 804 Bit 4 Bit Name EP1 TR IE Initial Value 0 R/W R/W Description EP1 TR Interrupt Enable 0: Disables an EP1 TR (transfer request) interrupt request 1: Enables an EP1 TR (transfer request) interrupt request 3 EP1 TS IE 0 R/W EP1 TS Interrupt Enable 0: Disables an EP1 TS (receive complete) interrupt request 1: Enables an EP1 TS (receive complete) interrupt request 2 EP0o TS IE 0 R/W EP0o TS Interrupt Enable 0: Disables an EP0o TS (receive complete) interrupt request 1: Enables an EP0o TS (receive complete) interrupt request 1 EP0i TR IE 0 R/W EP0i TR Interrupt Enable 0: Disables an EP0i TR (transfer request) interrupt request 1: Enables an EP0i TR (transfer request) interrupt request 0 EP0i TS IE 0 R/W EP0i TS Interrupt Enable 0: Disables an EP0i TS (receive complete) interrupt request 1: Enables an EP0i TS (receive complete) interrupt request 20.3.4 EP0i Data Register (EPDR0i) EPDR0i is a 64-byte 8-bit transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in TRG. When an ACK handshake is returned from the host after the data has been transmitted, EP0iTS in IFR0 is set. This FIFO buffer can be initialized by means of EP0iCLR in FCLR. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Data register for control-in transfer Rev. 1.00, 02/04, page 566 of 804 20.3.5 EP0o Data Register (EPDR0o) EPDR0o is a 64-byte 8-bit receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data other than setup commands. When data is received normally, EP0oTS in IFR0is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0oRDFN in TRG enables the next packet to be received. This FIFO buffer can be initialized by means of EP0oCLR in the FIFO clear register (FCLR). Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W R Description Data register for control-out transfer 20.3.6 EP0s Data Register (EPDR0s) EPDR0s is a data register specifically for endpoint 0 setup command. EPDR0s holds 8-byte command data sent in the setup stage. However, only the command to be processed by a microprocessor (firmware) is received. The command data to be processed automatically by this module is not stored. When the reception of data in the setup stage starts during read, the previous data is overwritten unconditionally. When the reception of the next command occurs during command read, the command reception starts and data read during command read is invalid. Note: EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data received in the next setup cannot be read successfully. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W R Description Data register for storing the setup command at the control-out transfer 20.3.7 EP1 Data Register (EPDR1) EPDR1 is a 16-byte 8-bit transmit FIFO buffer for endpoint 1. EPDR1 holds one packet of transmit data for the interrupt transfer of endpoint 1. Transmit data is fixed by writing one packet of data and setting EP1PKTE in TRG. When an ACK handshake is returned from the host after the data has been transmitted, EP1TS in IFR0 is set. This FIFO buffer can be initialized by means of EP1CLR in FCLR. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Data register for endpoint 1 transfer Rev. 1.00, 02/04, page 567 of 804 20.3.8 EP2i Data Register (EPDR2i) EPDR2i is a 128-byte 8-bit transmit FIFO buffer for endpoint 2i. EPDR2i has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and EP2iPKTE in TRG is set, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP2iCLR in FCLR. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Data register for endpoint 2i transfer 20.3.9 EP2o Data Register (EPDR2o) EPDR2o is a 128-byte 8-bit receive FIFO buffer for endpoint 2o. EPDR2o has a dual-buffer configuration, and has a capacity of twice the maximum packet size. The number of receive byte is displayed in the EPSZ2o register. The buffer on read side can be received again by writing EP2oRDFN in TRG to 1 after data is read. The receive data of this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP2oCLR in FCLR. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W R Description Data register for endpoint 2o transfer 20.3.10 EP3i Data Register (EPDR3i) EPDR3i is a 128-byte 8-bit transmit FIFO buffer for endpoint 3i. EPDR3i has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and an SOF packet is received, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. This FIFO buffer can be initialized by means of EP3iCLR in FCLR. Note: When an SOF packet cannot be received, an SOF interrupt is generated by an SOF marker function. However, data in a frame which could not receive an SOF is invalid. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Data register for endpoint 3i transfer Rev. 1.00, 02/04, page 568 of 804 20.3.11 EP3o Data Register (EPDR3o) EPDR3o is a 120-byte 8-bit receive FIFO buffer for endpoint 3o. EPDR3o has a dual-buffer configuration, and has a capacity of twice the maximum packet size. The number of receive byte is displayed in the EPSZ3o register. The receive data is fixed when an SOF packet is received. Accordingly, all receive data must be read until the next SOF packet is received. When the next SOF packet is received, the FIFO side is automatically switched over, and the previous data will not be possible to be read. This FIFO buffer can be initialized by means of EP3o CLR in FCLR. Note: When an SOF packet cannot be received, an SOF interrupt is generated by an SOF marker function. However, data in a frame which could not receive an SOF is invalid. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W R Description Data register for endpoint 3o transfer 20.3.12 EP4 Data Register (EPDR4) EPDR4 is a 16-byte 8-bit transmit FIFO buffer for endpoint 4. EPDR4 holds one packet of transmit data for the interrupt transfer of endpoint 4. Transmit data is fixed by writing one packet of data and setting EP4PKTE in TRG. When an ACK handshake is returned from the host after the data has been transmitted, EP4TS in IFR0 is set. This FIFO buffer can be initialized by means of EP4CLR in FCLR. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Data register for endpoint 4 transfer 20.3.13 EP5 Data Register (EPDR5) EPDR5 is a 64-byte 8-bit transmit FIFO buffer for endpoint 5. EPDR5 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and setting EP5PKTE in the trigger register, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. Data can be transferred to this FIFO buffer by DMA. This FIFO buffer can be initialized by means of EP5CLR in the FCLR register. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Data register for endpoint 5 transfer Rev. 1.00, 02/04, page 569 of 804 20.3.14 EP6 Data Register (EPDR6) EPDR6 is a 64-byte 8-bit receive FIFO buffer for endpoint 6. EPDR6 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. The number of receive byte is displayed in the EPSZ6 receive data size register. The buffer on read side can be received again by writing EP6RDFN in TRG to 1 after data is read. The receive data of this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP6CLR in FCLR. Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W R Description Data register for endpoint 6 transfer 20.3.15 EP0o Receive Data Size Register (EPSZ0o) EPSZ0o is a receive data size resister for endpoint 0o. EPSZ0o indicates the number of bytes received from the host. Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R Description Number of receive data for endpoint 0o 20.3.16 EP2o Receive Data Size Register (EPSZ2o) EPSZ2o is a receive data size resister for endpoint 2o. EPSZ2o indicates the number of bytes received from the host. FIFO of endpoint 2o has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU). Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R Description Number of received bytes for endpoint 2o 20.3.17 EP3o Receive Data Size Register (EPSZ3o) EPSZ3o is a receive data size resister for endpoint 3. EPSZ3o indicates the number of bytes received from the host. FIFO of endpoint 3o has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU). Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R Description Number of received bytes for endpoint 3o Rev. 1.00, 02/04, page 570 of 804 20.3.18 EP6 Receive Data Size Register (EPSZ6) EPSZ6 is a receive data size resister for endpoint 6. EPSZ6 indicates the number of bytes received from the host. FIFO of endpoint 6 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU). Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R Description Number of received bytes for endpoint 6 20.3.19 Trigger Register (TRG) TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2i, EP2o, EP4, EP5, and EP6. The packet enable trigger for the IN FIFO register and read complete trigger for the OUT FIFO register are triggers to be given. If a bit corresponding to each endpoint is set to 1, a trigger is given. Each bit in this register is automatically cleared to 0 after it is set to 1. Bit 15 Bit Name Initial Value 0 R/W Description Reserved The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 14 13 12 11 to 7 EP6 RDFN EP5 PKTE EP4 PKTE 0 0 0 All 0 W W W EP6 Read Complete EP5 Packet Enable EP4 Packet Enable Reserved The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 6 5 4 3 EP2o RDFN 0 EP2i PKTE EP1 PKTE 0 0 0 W W W EP2o Read Complete EP2i Packet Enable EP1 Packet Enable Reserved The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 2 1 0 EP0s RDFN 1 EP0o RDFN 0 EP0i PKTE 0 W W W EP0s Read Complete EP0o Read Complete EP0i Packet Enable Rev. 1.00, 02/04, page 571 of 804 20.3.20 Data Status Register (DASTS) DASTS indicates whether the transmit FIFO data register contains valid data. DASTS is set to 1 when data written to the transmit FIFO is enabled by writing PKTE in TRG to 1, and cleared to 0 when all data has been transmitted to the host. In case of a dual-configuration FIFO for endpoints 2i and 5, this bit is cleared to 0 when both sides are empty. Bit 7 6 5 4 3 2 1 0 Bit Name EP5DE EP4DE EP2iDE EP1DE EP0iDE Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Reserved This bit is always read as 0. EP5 Data Enable EP4 Data Enable Reserved This bit is always read as 0. EP2i Data Enable EP1 Data Enable Reserved This bit is always read as 0. EP0i Data Enable 20.3.21 FIFO Clear Register (FCLR) FCLR is a one shot register to clear the FIFO buffers for each endpoint. Writing 1 to a bit clears the data in the corresponding FIFO buffer. Each bit in this register is automatically cleared to 0 after it is set to 1. In case of the transmit FIFO, by writing data in the FIFO buffer, the data by which PKTE in TRG is not written to 1 and the data enabled by writing 1 can be cleared. In case of the receive FIFO, the unfixed data during reception and the data of which reception has not been completed can be cleared. Both sides of the dual-configuration FIFO buffers for EP2i, EP2o, EP3i, EP3o EP5, and EP6 can be cleared. The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer during transmission. Rev. 1.00, 02/04, page 572 of 804 Bit 15 Bit Name Initial Value R/W Description Reserved The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 14 13 12 11 EP6 CLR EP5 CLR EP4 CLR W W W EP6 Clear EP5 Clear EP4 Clear Reserved The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 10 9 8, 7 EP3o CLR EP3i CLR W W EP3o Clear EP3i Clear Reserved The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 6 5 4 3, 2 EP2o CLR EP2i CLR EP1 CLR W W W EP2o Clear EP2i Clear EP1 Clear Reserved The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 1 0 EP0o CLR EP0i CLR W W EP0o Clear EP0i Clear 20.3.22 DMA Transfer Setting Register (DMA) DMA is set when the dual address transfer of the DMAC is used to the data register for endpoints EP2i, EP2o, EP5, and EP6 to which transfer is possible by DMA. Bit 7 6 5 Bit Name EP6 DMAE EP6 DMAS EP5 DMAE Initial Value 0 0 0 R/W R/W R/W R/W Description EP6DMA Enable Enables DMA transfer for EP6. EP6DMA Request Select Selects DMA transfer request output for EP6. EP5DMA Enable Enables DMA transfer for EP5. Rev. 1.00, 02/04, page 573 of 804 Bit 4 3 2 1 0 Bit Name EP5 DMAS EP2o DMAE EP2o DMAS EP2i DMAE EP2i DMAS Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description EP5DMA Request Select Selects DMA transfer request output for EP5. EP2oDMA Enable Enables DMA transfer for EP2o. EP2oDMA Request Select Selects DMA transfer request output for EP2o. EP2iDMA Enable Enables DMA transfer for EP2i. EP2iDMA Request Select Selects DMA transfer request output for EP2i. 20.3.23 Endpoint Stall Register (EPSTL) EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake to the host from the next transfer when 1 is written to. The stall bit for endpoint 0 is cleared automatically on reception of 8 byte command data for which decoding is performed by the function and the EP0 STL bit is cleared. When the SETUPTS bit in IFR0 is set to 1, a write of the EP0 STL bit to 1 is ignored. For detailed operation, see section 20.6, Stall Operations. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 10 9 8 7 EP6 STL EP5 STL EP4 STL 0 0 0 0 R/W R/W R/W R EP6 Stall Sets EP6 stall EP5 Stall Sets EP5 stall EP4 Stall Sets EP4 stall Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 6 EP3o STL 0 R/W EP3o Stall Sets EP3o stall 15 to 11 Rev. 1.00, 02/04, page 574 of 804 Bit 5 4 Bit Name EP3i STL Initial Value 0 0 R/W R/W R Description EP3i Stall Sets EP3i stall Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 3 2 1 0 EP2o STL EP2i STL EP1 STL EP0 STL 0 0 0 0 R/W R/W R/W R/W EP2o Stall Sets EP2o stall EP2i Stall Sets EP2i stall EP1 Stall Sets EP1 stall EP0 Stall Sets EP0 stall 20.3.24 Configuration Value Register (CVR) CVR is a register to store the Configuration/Interface/Alternate value to be set when the Set Configuration/Set Interface command is normally received from the host. Bit 7 Bit Name CNFV Initial Value 0 R/W R Description Configuration Value The configuration setting value is stored when the Set Configuration command has been received. CNFV is updated when SETC in the interrupt flag register, IFR0, is set to 1. 6 5 4 3 2 1 0 INTV3 INTV2 INTV1 INTV0 ALTV2 ALTV1 ALTV0 0 0 0 0 0 0 0 R R R R R R R Interface Value The interface setting value is stored when the Set Interface command has been received. INTV is updated when SETI in the interrupt flag register, IFR0, is set to 1. Alternate Value The alternate setting value is stored when the Set interface command has been received. ALTV is updated when SETI in the interrupt flag register, IFR0, is set to 1. Rev. 1.00, 02/04, page 575 of 804 20.3.25 Time Stamp Register (TSR) TSR is a register to store the current time stamp value. The time stamp is updated when the SOF bit in IFR0 is set to1. The value of the time stamp when the SOF marker function is enabled and the SOF packet is broken remains as previous one. Bit Bit Name Initial Value R/W All 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R Description Reserved. These bits are always read as 0. 10 9 8 7 6 5 4 3 2 1 0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Time stamp data 15 to 11 20.3.26 Control Register (CLTR) CLTR is a register to make various settings of the USBF. When the isochronous transfer is used, the SOF marker function must be enabled. Bit 7, 6 Bit name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 5 PULLUPE 0 R/W Pull-up Enable Controls the output value of the USB_PULLUP pin. Rev. 1.00, 02/04, page 576 of 804 Bit 4 Bit name RWUPS Initial value 0 R/W R Description Remote Wakeup Status Status bit to indicate that the remote wakeup from the host is enabled/disabled. Indicates 0 when the remote wakeup is disabled with Device Remote Wakeup by the Set Feature/Clear Feature request and indicates 1 when it is enabled. 3 RSME 0 R/W Resume Enable Bit to clear the suspend state (performs the remote wakeup) When this bit is written to 1, a resume register is set. When this bit will be used, be sure to hold to 1 for one clock or more at 12 MHz in minimum and then clear to 0 again. 2 PWMD 0 R/W Power Mode Select 0: USBF is operated in self-powered mode 1: USBF is operated in bus-powered mode 1 ASCE 0 R/W Automatic Stall Clear Enable When this bit is set to 1, the stall handshake is returned to the host and the stall setting bit (EPSTLR/EPxSTL) of the returned endpoint is automatically cleared. Control in a unit of endpoint is disabled as this bit is common for all endpoints. When this bit is set to 0, be sure to clear the stall setting bit of each endpoint by using software. Enable this bit before setting EPSTL to 1. 0 SOFME 0 R/W SOF Marker Function Enable Controls SOF marker function. When this bit is set to 1, the SOF interrupt flag is set to 1 every 1 msec even if an SOF packet is broken. Before setting this bit to 1, check if the SOF interrupt flag of IFR0 register is detected correctly. If a suspension is detected, this bit must be cleared to 0. Before setting this bit to 1 again, check the SOF detection. Rev. 1.00, 02/04, page 577 of 804 20.3.27 Endpoint Information Register (EPIRn0 to EPIRn5) EPIR is a register to set the configuration information for each endpoint. 6 bytes of the information are required for one endpoint. Write the data in order from endpoint 0. Do not write more than 6 (bytes) x 19 (endpoints) = 114 bytes. Write this information once at power-on reset. Do not write it again afterwards. Write data of one endpoint is described below. EPIR writes data in the same address in order. Therefore though there is only one EPIR register, write data for registration number n (n is from 0 to 18) is listed as EPIRn0 to EPIRn5 (EPIR [registration number] [write order]) for the purpose of explaining. Write data in order from EPIR00. * EPIRn0 Bit 7 to 4 Bit Name D7 to D4 Initial value R/W Undefined W Description Endpoint Number Settable range: B'0000 to B0110 Note: B'0111 to B'1111 = Setting prohibited 3 to 0 D3 to D0 Undefined W Configuration number to which endpoint belongs Settable range: B'0000 to B0001 Note: B'0010 to B'1111 = Setting prohibited * EPIRn1 Bit 7 to 4 Bit Name D7 to D4 Initial value R/W Undefined W Description Interface number to which endpoint belongs Settable range: B'0000 to B'0010 Note: B'0011 to B'1111 = Setting prohibited 3 to 0 D3 to D0 Undefined W Alternate number to which endpoint belongs Settable range: Differs based on the interface number (D7 to D4) D7 to D4 = B'0000: D3 to D0 = B'0000 D7 to D4 = B'0001: D3 to D0 = B'0000 to B'0101 D7 to D4 = B'0010: D3 to D0 = B'0000 Note: Other than above = Setting prohibited Rev. 1.00, 02/04, page 578 of 804 * EPIRn2 Bit 7, 6 Bit Name D7, D6 Initial value R/W Undefined W Description Reserved The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Transfer Method of Endpoint [Settable range] B'00: Control B'01: Isochronous B'10: Bulk B'11: Interrupt Transfer Direction of Endpoint [Settable range] B'0: Out B'1: In Reserved The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 5, 4 D5, D4 Undefined W 3 D3 Undefined W 2 to 0 D2 to D0 Undefined W * EPIRn3 Bit 7 to 1 Bit Name D7 to D1 Initial value R/W Undefined W Description Maximum Packet Size of Endpoint Settable range: B'0000000 to B'1000000 Note: B'1000001 to B'1111111= Setting prohibited 0 D0 Undefined W Reserved The write value should always be 0. If 1 is written in this bit, correct operation cannot be guaranteed. * EPIRn4 Bit 7 to 0 Bit Name D7 to D0 Initial value R/W Undefined W Description Reserved The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. Rev. 1.00, 02/04, page 579 of 804 * EPIRn5 Bit 7 to 0 Bit Name D7 to D0 Initial value R/W Undefined W Description Endpoint FIFO Number Settable range: H'00 to H'03, H'05 to H'09 Note: H'04, H'0A to H'FF = Setting prohibited An endpoint number specified by the EPIRn0 register is an endpoint number used by the USB host. The endpoint FIFO number specified by the EPIRn5 register corresponds to the FIFO number which is attached to each endpoint physically supported by this USB function module. For details on correspondence between the endpoint functions and FIFO numbers in this USB function module, refer to section 20.1, Features. Note that the setting values for EPIRn0 to EPIRn5 are limited as described below. 1. Since each endpoint FIFO is optimized by a dedicated hardware corresponding to each transfer method, transfer direction, and maximum packet size, set the endpoint FIFO with a transfer method, transfer direction, and maximum packet size shown in the table 20.2. Example: Endpoint FIFO number 1 cannot be set as other than interrupt transfer and maximum packet size (16 bytes). Although endpoint FIFO number 5 cannot be set as other than isochronous transfer and IN, maximum packet size can be set in the range of 0 to 64 bytes. Endpoint number 0 and endpoint FIFO number 0 must correspond. The maximum packet size of endpoint FIFO number 0 can be set to 64 bytes only. The setting value of endpoint FIFO number 0 can be set to the maximum packet size only and the rest data is all 0. The maximum packet size of endpoint FIFO numbers 1 and 7 can be set to 16 only. The maximum packet size of endpoint FIFO numbers 2 and 3 can be set to 64 only. The maximum packet size of endpoint FIFO numbers 8 and 9 can be set to 32only. The maximum packet size of endpoint FIFO number 5 can be set in the range of 0 to 64. The maximum packet size of endpoint FIFO number 6 can be set in the range of 0 to 60. When the isochronous transfer is set, Alternate can be used in the range of 0 to 5 for the same endpoint. Be sure to allocate the Alternate to the same endpoint FIFO number. Endpoint information can be set up to 19 in maximum. Endpoint information of 19 pieces must be written. All information of endpoints which are not used must be written as 0. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. A list of restrictions of settable transfer method, transfer direction, and maximum packet size is described in table 20.2. Rev. 1.00, 02/04, page 580 of 804 Table 20.2 Restrictions of Settable Values Endpoint FIFO No. 0 1 2 3 5 6 7 8 9 Maximum Packet Size 64 bytes 16 bytes 64 bytes 64 bytes 0 to 64 bytes 0 to 60 bytes 16 bytes 32 bytes 32 bytes Transfer Method Control Interrupt Bulk Bulk Isochronous Isochronous Interrupt Bulk Bulk Transfer Direction IN IN OUT IN OUT IN IN OUT Examples of settings are shown below. Example of Setting 1: This is an example which is recommended by HCI USB TRANSPORT LAYER. Data for definition numbers 16 to 18 must be all 0s. Table 20.3 Example of Endpoint Configuration (1) EP No. 0 1 2 2 3 3 3 3 3 3 3 3 3 3 Conf. 1 1 1 1 1 1 1 1 1 1 1 1 1 Int. 0 0 0 1 1 1 1 1 1 1 1 1 1 Alt. 0 0 0 0 0 1 1 2 2 3 3 4 4 Transfer Method Control Interrupt Bulk Bulk Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Transfer Direction IN/OUT IN IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT Maximum Packet Size 64 bytes 16 bytes 64 bytes 64 bytes 0 byte 0 byte 9 bytes 9 bytes 17 bytes 17 bytes 25 bytes 25 bytes 33 byte 33 bytes EP FIFO No. 0 1 2 3 5 6 5 6 5 6 5 6 5 6 Rev. 1.00, 02/04, page 581 of 804 EP No. 3 3 Conf. 1 1 Int. 1 1 Alt. 5 5 Transfer Method Isochronous Isochronous Transfer Direction IN OUT Maximum Packet Size 49 byte 49 bytes EP FIFO No. 5 6 Config. 1 Int. 0 Alt. 0 EP Number EP FIFO Number Attribute Control (in,out) 64 bytes Interrupt (in) 16 bytes Bulk (in) 64 bytes Bulk (out) 64 bytes Isochronous (in) 0 byte Isochronous (out) 0 byte Isochronous (in) 9 bytes Isochronous (out) 9 bytes Isochronous (in) 17 bytes Isochronous (out) 17 bytes Isochronous (in) 25 bytes Isochronous (out) 25 bytes Isochronous (in) 33 bytes Isochronous (out) 33 bytes Isochronous (in) 49 bytes Isochronous (out) 49 bytes 0 1 2 2 0 1 2 3 5 6 1 0 3 3 1 3 3 2 3 3 3 3 3 4 3 3 5 3 3 Figure 20.2 Example of Endpoint Configuration (1) Rev. 1.00, 02/04, page 582 of 804 Table 20.4 Example of Setting of Endpoint Configuration Information (1) N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 EPIR[N]0 00 11 21 21 31 31 31 31 31 31 31 31 31 31 31 31 00 00 00 EPIR[N]1 00 00 00 00 10 10 11 11 12 12 13 13 14 14 15 15 00 00 00 EPIR[N]2 00 38 28 20 18 10 18 10 18 10 18 10 18 10 18 10 00 00 00 EPIR[N]3 80 20 80 80 00 00 12 12 22 22 32 32 42 42 62 62 00 00 00 EPIR[N]4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EPIR[N]5 00 01 02 03 05 06 05 06 05 06 05 06 05 06 05 06 00 00 00 Rev. 1.00, 02/04, page 583 of 804 Example of Setting 2:This is an example when there is endpoint information which is not used. All data of registration numbers 13 to 18 must be written as 0. Table 20.5 Example of Endpoint Configuration (2) EP No. 0 1 2 2 3 3 3 3 3 3 4 5 6 Conf. 1 1 1 1 1 1 1 1 1 1 1 1 Int. 0 0 0 1 1 1 1 1 1 2 2 2 Alt. 0 0 0 0 0 1 1 2 2 0 0 0 Transfer Method Control Interrupt Bulk Bulk Isochronous Isochronous Isochronous Isochronous Isochronous Isochronous Interrupt Bulk Bulk Transfer Direction IN/OUT IN IN OUT IN OUT IN OUT IN OUT IN IN OUT Maximum Packet Size 64 bytes 16 bytes 64 bytes 64 bytes 0 byte 0 byte 32 bytes 32 bytes 64 bytes 60 bytes 16 bytes 32 bytes 32 bytes EP FIFO No. 0 1 2 3 5 6 5 6 5 6 7 8 9 Rev. 1.00, 02/04, page 584 of 804 Config. 1 Int. 0 Alt. 0 EP Number EP FIFO Number 0 1 2 2 0 1 2 3 5 6 Attribute Control (in,out) 64 bytes Interrupt (in) 16 bytes Bulk (in) 64 bytes Bulk (out) 64 bytes Isochronous (in) 0 byte Isochronous (out) 0 byte Isochronous (in) 32 bytes Isochronous (out) 32 bytes Isochronous (in) 64 bytes Isochronous (out) 60 bytes 1 0 3 3 1 3 3 2 3 3 2 0 4 5 6 7 8 9 Interrupt (in) 16 bytes Bulk (in) 32 bytes Bulk (out) 32 bytes Figure 20.3 Example of Endpoint Configuration (2) Table 20.6 Example of Setting of Endpoint Configuration Information (2) n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 EPIR[n]0 00 11 21 21 31 31 31 31 31 31 41 51 61 00 00 00 00 00 00 EPIR[n]1 00 00 00 00 10 10 11 11 12 12 20 20 20 00 00 00 00 00 00 EPIR[n]2 00 38 28 20 18 10 18 10 18 10 38 28 20 00 00 00 00 00 00 EPIR[n]3 80 20 80 80 00 00 40 40 80 78 20 40 40 00 00 00 00 00 00 EPIR[n]4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 EPIR[n]5 00 01 02 03 05 06 05 06 05 06 07 08 09 00 00 00 00 00 00 Rev. 1.00, 02/04, page 585 of 804 20.4 20.4.1 Operation Cable Connection USB function Cable disconnected VBUS pin = 0 V UDC core reset Application USB module interrupt setting Initial settings As soon as preparations are completed, enable D+ pull-up in general output port USB cable connection No General output port D+ pull-up enabled? Yes IFR0/VBUS = 1 USB bus connection interrupt Interrupt request Clear VBUS flag (IFR0/VBUS) UDC core reset release Firmware preparations for start of USB communication Bus reset reception IFR0/BRST = 1 Bus reset interrupt Interrupt request Clear bus reset flag (IFR0/BRST) Wait for setup command reception complete interrupt Clear FIFOs Wait for setup command reception complete interrupt Figure 20.4 Cable Connection Operation The above flowchart shows the operation in the case of in section 20.7, Example of External Circuitry for USB Function Controller. In applications that do not require USB cable connection to be detected, processing by the USB bus connection interrupt is not necessary. Preparations should be made with the bus reset interrupt. For details, see section 20.7, Example of External Circuitry for USB Function Controller. Rev. 1.00, 02/04, page 586 of 804 20.4.2 Cable Disconnection USB function Cable connected VBUS pin = 1 Application USB cable disconnection USB_VBUS pin = 0 UDC core reset End Figure 20.5 Cable Disconnection Operation The above flowchart shows the operation in section 20.7, Example of External Circuitry for USB Function Controller. For details, see section 20.7, Example of External Circuitry for USB Function Controller. 20.4.3 Control Transfer Control transfer consists of three stages: setup, data (not always included), and status (figure 20.6). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below. Setup stage Control-in SETUP(0) DATA0 Data stage IN(1) DATA1 Status stage ... IN(0/1) DATA0/1 IN(0) DATA0 OUT(1) DATA1 Control-out SETUP(0) DATA0 OUT(1) DATA1 OUT(0) DATA0 ... OUT(0/1) DATA0/1 IN(1) DATA1 No data SETUP(0) DATA0 IN(1) DATA1 Figure 20.6 Transfer Stages in Control Transfer Rev. 1.00, 02/04, page 587 of 804 Setup Stage: USB function SETUP token reception Application Receive 8-byte command data in EP0s Command to be processed by application? Yes Set setup command reception complete flag (IFR0/SETUP TS = 1) No Automatic processing by this module Interrupt request Clear SETUP TS flag (IFR0/SETUP TS = 0) Clear EP0i FIFO (FCLR/EP0iCLR = 1) Clear EP0o FIFO (FCLR/EP0oCLR = 1) To data stage Read 8-byte data from EP0s Decode command data Determine data stage direction*1 Write 1 to EP0s read complete bit (TRG/EP0s RDFN = 1) *2 To control-in data stage To control-out data stage Notes: *1 In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). *2 When the transfer direction is control-out, the EP0i transfer request interrupt required in the status stage should be enabled here. When the transfer direction is control-in, this interrupt is not required and should be disabled. Figure 20.7 Setup Stage Operation Rev. 1.00, 02/04, page 588 of 804 Data Stage (Control-In): USB function IN token reception Application From setup stage 1 written to TRG/EP0s RDFN? Yes Valid data in EP0i FIFO? Yes Data transmission to host ACK Set EP0i transmission complete flag (IFR0/EP0i TS = 1) No NACK Write data to EP0i data register (EPDR0i) No NACK Write 1 to EP0i packet enable bit (TRG/EP0i PKTE = 1) Interrupt request Clear EP0i transmission complete flag (IFR0/EP0i TS = 0) Write data to EP0i data register (EPDR0i) Write 1 to EP0i packet enable bit (TRG/EP0i PKTE = 1) Figure 20.8 Data Stage (Control-In) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (IFR0/EP0i TS = 1). The end of the data stage is identified when the host transmits an OUT token and the status stage is entered. Note: If the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. If the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet. Rev. 1.00, 02/04, page 589 of 804 Data Stage (Control-Out): USB function OUT token reception Application 1 written to TRG/EP0s RDFN? Yes No NACK Data reception from host ACK Set EP0o reception complete flag (IFR0/EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0/EP0o TS = 0) Read data from EP0o receive data size register (EPSZ0o) No NACK OUT token reception 1 written to TRG/EP0o RDFN? Yes Read data from EP0o data register (EPDR0o) Write 1 to EP0o read complete bit (TRG/EP0o RDFN = 1) Figure 20.9 Data Stage (Control-Out) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (IFR0/EP0o TS = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the next data. The end of the data stage is identified when the host transmits an IN token and the status stage is entered. Rev. 1.00, 02/04, page 590 of 804 Status Stage (Control-In): USB function OUT token reception Application 0-byte reception from host ACK Set EP0o reception complete flag (IFR0/EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0/EP0o TS = 0) End of control transfer Write 1 to EP0o read complete bit (TRG/EP0o RDFN = 1) End of control transfer Figure 20.10 Status Stage (Control-In) Operation The control-in status stage starts with an OUT token from the host. The application receives 0-byte data from the host, and ends control transfer. Rev. 1.00, 02/04, page 591 of 804 Status Stage (Control-Out): USB function IN token reception Application Valid data in EP0i FIFO? Yes 0-byte transmission to host ACK Set EP0i transmission complete flag (IFR0/EP0i TS = 1) No NACK Interrupt request Clear EP0i transfer request flag (IFR0/EP0i TR = 0) Write 1 to EP0i packet enable bit (TRG/EP0i PKTE = 1) Interrupt request Clear EP0i transmission complete flag (IFR0/EP0i TS = 0) End of control transfer End of control transfer Figure 20.11 Status Stage (Control-Out) Operation The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be transmitted to the host, and control transfer ends. After the application has finished all processing relating to the data stage, 1 should be written to the EP0i packet enable bit. Rev. 1.00, 02/04, page 592 of 804 20.4.4 EP1, 4 Interrupt-In Transfer USB function Application Is there data for transmission to host? IN token reception Yes Write data to EP1 data register (EPDR1) Valid data in EP1 FIFO? Yes Data transmission to host ACK Set EP1 transmission complete flag (IFR0/EP1 TS = 1) Clear EP1 transmission complete flag (IFR0/EP1 TS = 0) No NACK Write 1 to EP1 packet enable bit (TRG/EP1 PKTE = 1) No Interrupt request Is there data for transmission to host? Yes Write data to EP1 data register (EPDR1) Write 1 to EP1 packet enable bit (TRG/EP1 PKTE = 1) No Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP1 DE bit in the USB data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO. Figure 20.12 EP1 Interrupt-In Transfer Operation Rev. 1.00, 02/04, page 593 of 804 20.4.5 EP2i, 5 Bulk-In Transfer (Dual FIFOs) USB function IN token reception Application Valid data in EP2i FIFO? Yes Data transmission to host ACK No NACK Interrupt request Clear EP2i transfer request flag (IFR0/EP2i TR = 0) Enable EP2i FIFO empty interrupt (IER0/EP2i EMPTY IE = 1) Space in EP2i FIFO? No Yes Set EP2i empty status (IFR0/EP2i EMPTY = 1) Interrupt request IFR0/EP2i EMPTY interrupt Clear EP2i empty status (IFR0/EP2i EMPTY = 0) Write one packet of data to EP2i data register (EPDR2i) Write 1 to EP2i packet enable bit (TRG/EP2i PKTE = 1) Figure 20.13 EP2 Bulk-In Transfer Operation EP2i has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2i/PKTE at one time after consecutively writing 128 bytes of data. EP2i/PKTE must be performed for each 64-byte write. When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first IN token, an IFR0/EP2i TR interrupt is requested. With this interrupt, 1 is written to the IER0/EP2i EMPTY IE bit, and the EP2i FIFO empty interrupt is enabled. At first, both EP2i FIFOs are empty, and so an EP2i FIFO empty interrupt is generated immediately. Rev. 1.00, 02/04, page 594 of 804 The data to be transmitted is written to the data register using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full, IFR0/EP2i EMPTY is cleared to 0. If at least one FIFO is empty, IFR0/EP2i EMPTY is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to IER0/EP2i EMPTY IE and disable interrupt requests. 20.4.6 EP2o, 6 Bulk-Out Transfer (Dual FIFOs) USB function OUT token reception Application Space in EP2o FIFO? Yes Data reception from host ACK Set EP2o FIFO full status (IFR0/EP2o FULL = 1) No NACK Interrupt request Read EP2o receive data size register (EPSZ2o) Read data from EP2o data register (EPDR2o) Write 1 to EP2o read complete bit (TRG/EP2o RDFN = 1) Both EP2o FIFOs empty? Yes Clear EP2o FIFO full status (IFR0/EP2o FULL = 0) No Interrupt request Figure 20.14 EP2o Bulk-Out Transfer Operation Rev. 1.00, 02/04, page 595 of 804 EP2o has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the IFR0/EP2o FULL bit is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately. When both FIFOs are full, NACK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the TRG/EP2o RDFN bit. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet. Rev. 1.00, 02/04, page 596 of 804 20.4.7 EP3i Isochronous-In Transfer USB function SOF reception INTN Firmware Clear Start of Frame packet detection flag (IFR0/SOF = 0) FIFO buffer switch over Modify interrupt flag (IFR0/EP3i TR, TS) Indicate the status of FIFO B side FIFO A side In-token reception Check interrupt flag (IFR0/EP3i TR, TS) Valid data in EP3i FIFO? Yes Data transmission to host EP3i normal transfer Set internal flag (IFR0/EP3i TS = 1) INTN SOF reception Clear Start of Frame packet detection flag (IFR0/SOF = 0) 0 byte data transmission to the host EP3i transfer request Set internal flag (IFR0/EP3i TR = 1) Write data of one packet to endpoint data register 3i (EPDR3i) Read time stamp registers H, L (TSRH, L) FIFO B side No FIFO buffer switch over Modify interrupt flag (IFR0/EP3i TR, TS) Indicate the status of FIFO A side FIFO B side In-token reception Check interrupt flag (IFR0/EP3i TR, TS) Read time stamp registers H, L (TSRH, L) FIFO A side Valid data in EP3i FIFO? Yes Data transfer to host EP3i normal transfer Set internal flag (IFR0/EP3i TS = 1) No EP3i transfer request Set internal flag (IFR0/EP3i TR = 1) 0 byte data transmission to the host Write one packet of data in endpoint data register 3i (EPDR3i) Figure 20.15 Operation of Isochronous-In Transfer Rev. 1.00, 02/04, page 597 of 804 EP3i has two 64-byte FIFOs in maximum, but the user can perform data transmission and write transmit data without being aware of this dual-FIFO configuration. (In figure 20.15, FIFO sides A and B are used for description.) In isochronous transfer, transfer is occurred only once per one frame (1 ms). So, when SOF is received, the FIFO buffer is switched automatically with hardware (the FIFO buffer is switched automatically at a cycle of 1 ms by hardware if the SOF marker function is enabled even in the case that SOF cannot be received by error). FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the USB function module transmits the data to the host and the FIFO buffer in which the firmware writes the transmit data have different buffers, and a read and write of FIFO buffer are not competed. Accordingly, the data written by the firmware is the data to be transmitted in one frame after. The buffers of FIFOs are switched over automatically by the SOF reception, so a write of data must be completed within the frame. The USB function module transmits data to the host and set the TS internal flag to 1 when data to be transmitted to the host exists in FIFO after an in-token is received. If there is no data in the FIFO buffer, set the TR internal flag to 1 and transmit 0-byte data to the host. The internal flag (TR, TS) information is automatically modified as IFR0 flag information (TR, TS) that can be read by the SOF reception from the firmware. In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to check the time stamp. Then one packet data is written to FIFO. This written data is transmitted to the host in the next frame. Whether the previous frame has been transmitted normally or not can be determined by reading the IFR0 flag information (TR, TS). Rev. 1.00, 02/04, page 598 of 804 20.4.8 EP3o Isochronous Out Transfer USB function SOF reception INTN Firmware Clear Start of Frame packet detection flag (IFR0/SOF = 0) Read time stamp registers H, L (TSRH, L) FIFO buffer switch over Modify interrupt flag (IFR0/EP3o TS, TF) Indicate the status of FIFO B side FIFO A side Out-token reception FIFO B side Read EP3o flag (IFR0/EP3o TS, TF) Data reception from host No error in receive data? Yes EP3o normal transmission Set internal status 1 (IFR0/EP3o TS = 1) No Read endpoint reception data register (EPSZ3o) EP4 abnormal transmission Set internal status 1 (IFR0/EP3o TF = 1) Read data from endpoint data register 3o (EPDR3o) SOF reception INTN Clear Start of Frame packet detection flag (IFR0/SOF = 0) Read time stamp registers H, L (TSRH, L) FIFO buffer switch over Modify interrupt flag (IFR0/EP3o TS, TF) Indicate the status of FIFO A side FIFO B side Out-token reception FIFO A side Read EP3o flag (IFR0/EP3o TS, TF) Data reception from host No error in receive data? Yes EP3o normal transmission Set internal status 1 (IFR0/EP3o TF = 1) No Read endpoint receive data size register 3o (EPSZ3o) EP4 abnormal transmission Set internal status 1 (IFR0/EP3o TF = 1) Read data from endpoint data register 3o (EPDR3o) Figure 20.16 Operation of EP3o Isochronous-Out Transfer Rev. 1.00, 02/04, page 599 of 804 EP3o has two 60-byte FIFOs in maximum, but the user can perform data transmission and read transmit data without being aware of this dual-FIFO configuration. (In figure 20.16, FIFO sides A and B are used for description.) In isochronous transfer, transfer is occurred only once per one frame (1 ms). So, when SOF is received the FIFO buffer is switched automatically with hardware (the FIFO buffer is switched automatically at a cycle of 1 ms by hardware if the SOF marker function is enabled even in the case that SOF cannot be received by error). FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the USB function module receives the data from the host and the FIFO buffer in which the firmware reads the receive data have different buffers, and a read and write of FIFO buffer are not competed. Accordingly, the data written by the firmware is the data received in one frame before. The buffers of FIFOs are switched over automatically by the SOF reception, so a read of data must be completed within the frame. The USB function module receives data from the host after an out-token is received. If there is an error in the data, set the TF internal flag to 1. If there is no error in the data, set the TS internal flag to 1. The internal flag (TF, TS) information is automatically modified as IFR0 flag information (TF, TS) that can be read by the SOF reception from the firmware. In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to check the time stamp. Then data is read from the FIFO buffer. IFR0 flag information (TS, TF) is read and decided if the data has an error. The IFR0 flag information at this time represents the status of the currently readable FIFO buffer. Rev. 1.00, 02/04, page 600 of 804 20.5 Processing of USB Standard Commands and Class/Vendor Commands Processing of Commands Transmitted by Control Transfer 20.5.1 A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 20.7 below. Table 20.7 Command Decoding on Application Side Decoding not Necessary on Application Side Clear Feature Get Configuration Get Interface Get Status Set Address Set Configuration Set Feature Set Interface Decoding Necessary on Application Side Get Descriptor Class/Vendor command Synch Frame Set Descriptor If decoding is not necessary on the application side, command decoding, data stage, and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, this module stores the command in the EP0s FIFO. After normal reception is completed, the IFR0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, 8 bytes of data must be read from the EP0s data register (EPDR0s) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation. Rev. 1.00, 02/04, page 601 of 804 20.6 20.6.1 Stall Operations Overview This section describes stall operations in this module. There are two cases in which the USB function module stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. However, the internal status bit to EP0 is automatically cleared only when the setup command is received. 20.6.2 Forcible Stall by Application The application uses the EPSTL register to issue a stall request for the USB function module. When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (11 in figure 20.17). The internal status bits are not changed at this time. When a transaction is sent from the host for the endpoint for which the EPSTL bit was set, the USB function module references the internal status bit, and if this is not set, references the corresponding bit in EPSTL (1-2 in figure 20.17). If the corresponding bit in EPSTL is set, the USB function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 20.17). If the corresponding bit in EPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 20.17), the USB function module continues to return a stall handshake while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 20.17). To clear a stall, therefore, it is necessary for the corresponding bit in EPSTL to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 20.17). Rev. 1.00, 02/04, page 602 of 804 (1) Transition from normal operation to stall (1-1) USB Internal status bit 0 EPSTL 01 1. 1 written to EPSTL by application (1-2) Reference Transaction request Internal status bit 0 EPSTL 1 1. IN/OUT token received from host 2. EPSTL referenced (1-3) Stall STALL handshake Internal status bit 01 To (2-1) or (3-1) (2) When Clear Feature is sent after EPSTL is cleared (2-1) Transaction request Internal status bit 1 EPSTL 10 EPSTL 1 1. 1 set in EPSTL 2. Internal status bit set to 1 3. Transmission of STALL handshake 1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed (2-2) STALL handshake Internal status bit 1 EPSTL 0 1. Transmission of STALL handshake (2-3) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0 Normal status restored (3) When Clear Feature is sent before EPSTL is cleared to 0 (3-1) Clear Feature command Internal status bit 10 To (1-2) EPSTL 1 1. Internal status bit cleared to 0 2. EPSTL not changed Figure 20.17 Forcible Stall by Application Rev. 1.00, 02/04, page 603 of 804 20.6.3 Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 20.18). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. After a bit is cleared by the Clear Feature command, EPSTL is referenced (3-1 in figure 20.18). The USB function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 20.18). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 20.18). If set by the application, EPSTL should also be cleared (2-1 in figure 20.18). (1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 To (2-1) or (3-1) EPSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically (2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 EPSTL 0 1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake (2-2) STALL handshake Internal status bit 1 EPSTL 0 Stall status maintained (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0 2. EPSTL not changed Normal status restored Figure 20.18 Automatic Stall by USB Function Module Rev. 1.00, 02/04, page 604 of 804 20.7 Example of External Circuitry for USB Function Controller D+ Pull-Up Control: In a system where it is wished to disable USB host/hub connection notification (D+ pull-up) (during high-priority processing or initialization processing, for example), D+ pull-up should be controlled using a general output port. However, if a USB cable is already connected to the host/hub and D+ pull-up is prohibited, D+ and D- will both go low (both of D+ and D- pulled down on the host/hub side) and the USB function controller will mistakenly identify this as reception of a USB bus reset from the host. Therefore, the D+ pull-up control signal and USB_VBUS pin input signal should be controlled using an UPLUP output port and the USB cable VBUS (AND circuit) as shown in the circuit example below (The UDC core in this LSI maintains the powered state when the USB_VBUS pin is low, regardless of the D+/D- state.) Detection of USB Cable Connection/Disconnection: As USB states, etc., are managed by hardware in this module, a VBUS signal that recognizes connection/disconnection is necessary. The power supply signal (VBUS) in the USB cable is used for this purpose. However, if the cable is connected to the USB host/hub when the function (system installed in this LSI) power is off, a voltage (5 V) will be applied from the USB host/hub. Therefore, an IC (such as an HD74LV1G08A or 2G08A) that allows voltage application when the system power is off should be connected externally. This LSI USB_PULLUP IC allowing voltage application when system power is off (HD74LV1G(2G)08A, etc.) USB_VBUS USB connector VBUS UCLK USB function controller 48 MHz USB_P USB_N IC allowing voltage application when system power is off (HD74LV1G126A, etc.) GND D+ D- USB cable Note: This example is for reference only, therefore proper operation is not guaranteed with this circuit example. If system countermeasures are required for external surges and ESD noise, use a protective diode, a noise canceller, etc. Figure 20.19 Example of USB Function Module External Circuitry Rev. 1.00, 02/04, page 605 of 804 20.8 20.8.1 Usage Notes Setup Data Reception The following points should be noted on EPDR0s in which reception of 8-byte setup data is performed. 1. Since the setup command must be received in the USB, writing from the USB bus side is prior to reading from the CPU side. While the CPU reads data after completion of reception and reception of the next setup command is started, reading from the CPU side is forcibly invalid in order to give priority to writing. Therefore a value to be read after starting reception is undefined. 2. EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data received in the next setup cannot be read successfully. 20.8.2 FIFO Clear When the USB cable is disconnected during communication, data which is receiving or transmitting may remain in the FIFO. Therefore the FIFO must be cleared immediately after connecting the USB cable again. Note that the FIFO in which data is receiving from the host or transmitting to the host must not be cleared. 20.8.3 Overreading/Overwriting of Data Register The following points should be noted when the data register of the USB function controller is read from or written to. Receive Data Register: The receive data register must not read data which is more than valid receive data bytes. That is, data which is more than bytes indicated in the receive data size register must not be read. In case of the receive data register which has the dual FIFO buffer, the maximum number of data which can be read in a single time is maximum packet size. Write 1 to TRG/RDFN after data in the current valid buffer is read. This writing switches the FIFO buffer. Then, the new number of bytes is reflected in the receive data size and the next data can be read. Transmit Data Register: The transmit data register must not write data which is more than maximum packet size. In case of the transmit data register which has the dual FIFO buffer, the maximum number of data which can be written in a single time is maximum packet size. Write 1 to TRG/PKTE after data is written. This writing switches the FIFO buffer. Then, the next data can be written to another buffer. Therefore data must not be written in both buffers in a single time. Rev. 1.00, 02/04, page 606 of 804 20.8.4 Assigning EP0 Interrupt Sources The EP0 interrupt sources assigned to IFR0 (bits 0, 1, 2, and 29) must be assigned to the same interrupt pins by ISR0. The other interrupt sources have no restrictions. 20.8.5 FIFO Clear when DMA Transfer is Set When the DMA transfer is enabled in endpoints 2o and 6, the data register cannot be cleared. Cancel the DMA transfer before clearing the data register. 20.8.6 Note on Using TR Interrupt The bulk-in transfer has a transfer request interrupt (TR interrupt). The following points should be noted when using a TR interrupt. When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO, the TR interrupt flag is set. However, the TR interrupt is generated continuously at the timing as shown in figure 20.20. In this case, note that erroneous operation should not occur. Note: When the IN token is received and there is no data in the corresponding EP FIFO, an NACK is determined. However, the TR interrupt flag is set after an NACK handshake is transmitted. Therefore when the next IN token is received before TRG/PKTE is written, the TR interrupt flag is set again. Rev. 1.00, 02/04, page 607 of 804 TR interrupt routine CPU TR flag Transmit data TRG clearing writing /PKTE TR interrupt routine Host IN token IN token IN token NACK determination NACK USB TR flag setting NACK determination NACK TR flag setting (TR flag is set again) Data transmission ACK Figure 20.20 Set Timing of TR Interrupt Flag Rev. 1.00, 02/04, page 608 of 804 20.8.7 Note on Clearing and Transition to Software Standby Mode Figure 20.21 shows an example flow of clearing and transition to software standby mode. When accessing the USBF again after software standby mode has been cleared, wait for operation stabilization time of the USB clock (48 MHz). Example flow of transition to software standby mode Example flow of clear software standby mode Interrupt by suspend is enabled ISR0/SURES IS is cleared to 0 or set to 1 IER0/SURES IE is set to 1 USB bus resume is detected IRQ7 is output at low falling edge Detection of USB bus in suspend state Software standby mode is cleared IFR0/SURSS and SURSF are set to 1 Interrupt request by INT0N or INT1N IRR0/IRQ7R is cleared to 0 IFR0/SURSF is cleared to 0 IRQ7 is enabled and set to be detected at falling edge Waiting for USB clock oscillation stabilization time Waiting for EXCPGCR/USBVALID = 1 IFR0/SURSS = 1? NO USB clock oscillation is stabilized EXCPGCR/USBVALID is set to 1 YES Transition to software standby mode (Execution of SLEEP instruction ) IFR0/SURSF is cleared to 0 Normal state is kept without transition to software standby mode Description Operation by software setting Automatic processing by hardware of the LSI Figure 20.21 Example Flow of Clearing and Transition to Software Standby Mode Rev. 1.00, 02/04, page 609 of 804 20.8.8 Main Clock Usage when Using Bus Password Function When the main clock of this LSI (usually input from EXTAL) is input using the RF chip for the bluetooth as is the clock for the bluetooth interface (usually input from RDI_REFCLK_IN), clock cannot be provided again on the recovery from the suspend state. Therefore, when using the buspowered function, a clock in active state should be used as the main clock. To hold down the power consumption in suspend state, the crystal oscillator should be connected to the EXTAL and XTAL pins, in order to provide main clock to the CPU. 20.8.9 Peripheral clock for USB When using USB Function Controller, the frequency of the peripheral clock (P) should be 12MHz or larger. With the clock frequency less than 12MHz, the USB Function Controller does not operate normally. Refer to section 11, Clock Pulse Generator (CPG) for a detailed setting of the clock. Rev. 1.00, 02/04, page 610 of 804 Section 21 Bluetooth Interface (BT) This LSI incorporates a Bluetooth interface (BT) as hardware for the baseband processing for the Bluetooth. This Bluetooth interface conforms to version 1.1 of the Bluetooth Specification, is configured by combination of hardware and firmware, and provides a lower protocol stack function to the host controller interface (HCI) layer. With this function, Bluetooth logo certification is acquired for a baseband layer (BB) and link management protocol layer (LMP). To configure the upper protocol stack, HCI commands which are defined by version 1.1 of the Bluetooth Specification and 53 types of test command interface (TCI) commands are supported. For communication between upper and lower protocol stacks, nine types of functions are prepared as an application interface (API). 21.1 Features * Conforms to version 1.1 of the Bluetooth Specification * Frequency hopping within 79 channels as a form of spread-spectrum modulation * Supports ACL (Asynchronous Connection-Less) and SCO (Synchronous ConnectionOriented) links * Controls the ACL and SCO from upper layer above HCI * Supports all types of packets: i.e., control packets for establishing links and connections, and packets for transmission and received packets * Supports point-to-point and point-to-multipoint connections (piconet) * Mutual conversion in Voice Codec between A-law and -law, CVSD and linear PCM, linear PCM and A/-law, or A/-law and CVSD * Encryption/decryption * Controls three power-down modes: the Hold, Sniff and Park modes * Supports a direct interface with the Renesas RF ICs, such as the HD157100NP and HD157102NP * Supports a direct interface with the STLC7550 (ST Microelectronics) or MC145483 (Motorola) Voice Codec IC without involving the CPU * Includes a frequency conversion function that allows the use of a 32.768-kHz crystal resonator to provide the low-frequency clock for power-down modes * Supports unique TCI commands (53 types) and API functions (9 types) in addition to the HCI commands IFBT000A_000020020800 Rev. 1.00, 02/04, page 611 of 804 Figure 21.1 shows a block diagram of the Bluetooth interface (BT). VCI_CODEC_PWRDWN* VCI_SCO_SYNC_OUT* RCI_SPI_TXRX RCI_SPI_ENB RCI_SPI_CLK VCI_SCO_RX* VCI_SCO_TX* VCI_HWC* VCI_SCO_CLK_OUT* BT RF-IC SPI interface Voice Codec interface RDI_CTRL2 RDI_TXTRDATA RDI_RXBDW_OUT RDI_CTRL3 RF-IC interface RDI_CTRL4 RDI_REFCLK_IN Power-on-reset/ clock-resume control circuit Internal reset signal 1 0 PSA1 RT CSEL Frequency conversion circuit Bus interface PSELA register Pin function controller (PFC) 1 0 Test circuit Oscillator RESETP RREF EXTAL2 XTAL2 RTCSEL0 Note: * These pins, i.e., the Voice Codec pins, can be used as I/O ports when a Voice Codec IC is not connected. Figure 21.1 Block Diagram of Bluetooth Interface (BT) Rev. 1.00, 02/04, page 612 of 804 Internal peripheral bus 21.2 Input/Output Pins Table 21.1 summarizes the input/output pins used by the BT. Table 21.1 Input/Output Pins Classification Name RF-IC interface RDI_CTRL2 RDI_TXTRDATA RDI_RXBDW_OUT RDI_REFCLK_IN RDI_CTRL3 RDI_CTRL4 I/O Function/Signal Output External power amplifier control output for supporting class 1 I/O Transmit/receive data I/O for the RF IC Output Packet-control output for the RF IC Input Data I/O clock for the RF IC or main clock input for the BT Output Strobe output to enable the oscillator in the RF IC Output Reset-control signal for the RF IC, power supply for the interface, or power-down control output signal I/O SPI serial data I/O SPI interface with RF IC RCI_SPI_TXRX RCI_SPI_CLK RCI_SPI_ENB Output Clock output for the SPI interface with the RF IC Output Enable output for the SPI interface with the RF IC Output Clock output for a Voice Codec IC*1 Voice Codec interface VCI_SCO_CLK_OUT VCI_SCO_SYNC_OUT Output Frame-synchronization signal output for a Voice Codec IC*1*3 VCI_SCO_RX VCI_SCO_TX VCI_HWC VCI_CODEC_ PWRDWN Output Receive data output to a Voice Codec IC*1 Input Transmit data input from a Voice Codec IC*1 Output Operation mode select output for a Voice Codec IC*1 Output Power-down control output for a Voice Codec IC*1 Input Input Input Input Test Pin*2 Test Pin*2 For connection to a crystal resonator For connection to a crystal resonator Clock select RTCSEL0 RREF EXTAL2 XTAL2 Notes: 1. The Voice-Codec interface pins are available for use as I/O ports (port E) when a Voice Codec IC is not connected. For details, refer to section 23, I/O Ports. 2. The RTCSEL0 pin should be fixed to low, and RREF pin should be pulled-up to Vcc. 3. As the VCI_SCO_SYNC_OUT pin is multiplexed with the BREQ pin, it should be pulledup for the normal power-up sequence. Rev. 1.00, 02/04, page 613 of 804 21.3 Register Description The BT registers are accessed via firmware that is provided rather than directly by the user. Therefore, no description is given here. For the functions of the firmware, refer to the separate manual. All registers in BT module are initialized only by the power-on reset input pin. They are not initialized by the power-on reset and manual reset generated from WDT. 21.4 RF-IC Interface The Bluetooth interface (BT) supports the direct connection with the Renesas RF ICs, such as HD157100NP and HD157102NP. 21.4.1 Connection with RF ICs Figure 21.2 shows an example of the connection of this LSI and a Renesas RF IC, such as the HD157100NP and HD157102NP. When a power-on reset signal is applied, the reset signal is sent to the BT power-on reset/clock-resume control circuit and is also sent to the RF IC via the RDI_CTRL4 pin. After the RDI_CTRL4 pin has fulfilled its function as a reset pin, the pin will function as a power-supply pin for the interface of the RF IC. Even after the external power-on reset signal has been negated, the reset state is maintained within this LSI. BT RF IC RDI_TXTRDATA RDI_RXBDW_OUT BDATA1 BPKTCTL BRCLK BXTLEN BnPWR RF-IC interface RDI_REFCLK_IN RDI_CTRL3 RDI_CTRL4 RF-IC SPI interface RCI_SPI_TXRX RCI_SPI_CLK RCI_SPI_ENB BDDATA BDCLK BnDEN CPG EXTAL A separate clock source may provide the clock input on the EXTAL pin. Figure 21.2 Example of Connection to RF IC Rev. 1.00, 02/04, page 614 of 804 After it has been initialized by a reset, the RF IC starts outputting a clock signal (RDI_REFCLK_IN). A counter in the BT power-on-reset/clock-resume control circuit starts counting the cycles of a clock signal from the RF IC. When the value in the counter matches the required value, the RF IC is released from the reset state. The clock signal (RDI_REFCLK_IN) received from the RF IC may be connected to the clockpulse generator's EXTAL pin for use as the LSI's main clock signal. This may reduce the number of crystal oscillators required to configure the overall Bluetooth system. In this case, 13 MHz is the only available main-clock frequency for this LSI, since the frequency on the RDI_REFCLK_IN pin will be 13 MHz. An independent clock can be input without connecting the output of the RDI_REFCLK_IN signal to the EXTAL pin*. In this case, the main clock may run at any frequency within the range guaranteed for use with this LSI. For details on this range, refer to section 28, Electrical Characteristics. For details on the EXTAL pin, refer to section 11, Clock Pulse Generator (CPG). Note: * When the on-chip USBF bus-powered function is used, make sure to input an independent clock from the RDI_REFCLK_IN input clock and set it to an active state. Rev. 1.00, 02/04, page 615 of 804 21.5 Voice Codec IC Interface This BT employs a function of the direct transfer of data with the RF IC over an SCO link without intervention of the CPU. As an external Voice Codec IC, this BT supports a direct interface with the STLC7550 (STMicroelectronics) or MC145483 (Motorola) Voice Codec IC. 21.5.1 Voice Codec (STLC7550) Interface Figure 21.3 shows an example of the connection of this BT and the Voice Codec (STLC7550). The SCLK pin of the STLC7550 is not used. The VCI_SCO_SYNC_OUT pin is multiplexed with the BREQ pin. This pin should be pulled-up for the normal power-up sequence. BT Voice codec IC (STLC7550) VCI_SCO_CLK_OUT VCI_SCO_SYNC_OUT VCI_SCO_RX VCI_SCO_TX VCI_HWC VCI_CODEC_PWRDWN MCLK FS DIN DOUT HCI PWRDWN Voice Codec interface MCM MS SCLK Figure 21.3 Example of Connection to Voice Codec (STLC7550) Rev. 1.00, 02/04, page 616 of 804 21.5.2 Voice Codec (MC145483) Interface Figure 21.4 (1) shows an example of the connection of this BT and the Voice Codec (MC145483). The VCI_SCO_SYNC_OUT pin is multiplexed with the BREQ pin. This pin should be pulled-up for the normal power-up sequence. BT Voice Codec IC (MC145483) VCI_SCO_CLK_OUT VCI_SCO_SYNC_OUT VCI_SCO_RX VCI_SCO_TX VCI_HWC VCI_CODEC_PWRDWN PDI MCLK BCLKT BCLKR FST/FSR DR DT Voice Codec interface Figure 21.4 (1) Example of Connection to Voice Codec (MC145483) Figure 21.4 (2) shows the timing chart. VCI_SCO_CLK_OUT (output) (fVCI_SCO_CLK_OUT = 256kHz) VCI_SCO_SYNC_OUT (output) (fVCI_SCO_SYNC_OUT = 8kHz) MSB LSB 2 3 4 5 6 7 8 9 10 11 12 13 LSB 2 3 4 5 6 7 8 9 10 11 12 13 VCI_SCO_RX (output) 1 MSB VCI_SCO_TX (input) 1 Figure 21.4 (2) Timing chart for connection to Voice Codec (MC145483) Rev. 1.00, 02/04, page 617 of 804 21.6 Low-Frequency Clock Oscillator Interface This BT has an interface to receive an external clock running at 32 kHz or 32.768 kHz to support Bluetooth's power-down modes (Sniff, Park, and Hold). There are four ways to supply this lowfrequency clock (described below). The method is specified by the value of the RTCSEL1 bit in the PSELA. For details on the PSELA, refer to section 24, Pin Function Controller (PFC). Here are the five possible ways to obtain the low-frequency clock signal; * connect the 32-kHz crystal resonator to the EXTAL2 and XTAL2 pins to make the on-chip oscillator circuit provide the clock; * connect the 32.768-kHz crystal resonator to the EXTAL2 and XTAL2 pins to make the onchip oscillation circuit provide the clock of 32.768kHz, and generate the pseudo 32-kHz clock in the frequency-conversion circuit; * directly input 32.0-kHz from the EXTAL2 pin; and * directly input 32.768-kHz from the EXTAL2 pin, and generate the pseudo 32-kHz clock in the frequency-conversion circuit. Table 21.2 is a list of the settings. Table 21.2 Settings and Functions RTCSEL1 Bit 1 Function The 32-kHz crystal resonator is connected to the EXTAL2 and XTAL2 pins to make the on-chip oscillation circuit provide a signal. If not, 32.0-kHz clock should be supplied at the EXTAL2 pin. The 32.768-kHz crystal resonator is connected to the EXTAL2 and XTAL2 pins to make the on-chip oscillation circuit provide a signal. If not, 32.768-kHz clock should be supplied at the EXTAL2 pin. 0 21.6.1 Using RTCSEL1 Bit to Select Clock Function The RTCSEL1 bit in the PSELA selects whether or not the frequency-conversion circuit is activated. The frequency-conversion circuit generates a pseudo-32-kHz clock signal from a 32.768-kHz signal. Activating the frequency-conversion circuit allows the use of the 32.768-kHz crystal resonator, as used with the RTC (Real Time Clock), instead of the connection of a 32.0kHz crystal resonator to the EXTAL2 and XTAL2 pins. Clearing the RTCSEL1 bit to 0 activates the frequency-conversion circuit. Setting the RTCSEL1 bit makes the circuit inactive and the 32.768-kHz frequency is passed through the circuit. When the RTCSEL0 pin is set to 1, the RTCSEL1 bit should always be set to 1. The initial value of the RTCSEL1 bit is 0. For details on the PSELA, refer to section 24, Pin Function Controller (PFC). Rev. 1.00, 02/04, page 618 of 804 21.6.2 Frequency-Conversion Circuit Operations 128 cycles of a 32.768-kHz signal are equal in duration to 125 cycles of a 32-kHz signal. This is used to convert the 32.768-kHz clock into a 32-kHz clock in the following way. Firstly, the 128 cycles are divided into three states by the counting of cycles, as shown in figure 21.5. State 0 is made up of the first 43 cycles, state 1 is made up of the next 42 cycles, and state 2 is made up of the remaining 43 cycles. Then, removing a single falling edge from each of these states leaves 125 cycles. This method realizes 125 cycles from a 32.768-kHz clock within the same period as 125 cycles of the 32-kHz clock. The resulting frequency is 32000 cycles per second. A 32-kHz clock signal has thus been generated from the converted clock. 32.768 kHz (A) State 0 43 cycles State 1 42 cycles State 2 43 cycles Stolen Stolen Stolen (B) 125 cycles Figure 21.5 Function of Frequency-Conversion Circuit The cumulative time differences between each cycle of a 32-kHz signal and the corresponding cycle of a pseudo-32-kHz signal are shown in figure 21.6. Since the total time for given numbers of cycles for the 32-kHz clock matches that of the pseudo 32-kHz clock every 125 cycles (see (A) and (B)), the maximum error is approximately 30 sec. Rev. 1.00, 02/04, page 619 of 804 [s] 35.0E-6 30.0E-6 25.0E-6 20.0E-0 15.0E-6 10.0E-6 5.0E-6 000.0E+0 1 -5.0E-6 44 87 130 173 216 Figure 21.6 Errors in Pseudo-32-kHz Clock Obtained by Conversion from 32.768-kHz Clock 21.6.3 Note on Connecting External Crystal Resonator Figure 21.7 shows a note when connecting an external crystal resonator to the EXTAL2 and XTAL2 pins. Rev. 1.00, 02/04, page 620 of 804 Rf RD Internal LSI EXTAL2 Crystal Cin resonator XTAL2 Cout Notes: 1. A variable capacitor for frequency adjustment may be placed in the Cin or Cout side according to the adjustment range, stability, and so on. 2. The value of the on-chip resistor is Rf = 10 M and RD = 400 k under the typical condition. 3. The values of the Cin and Cout include floating capacitance due to wiring. 4. Since the oscillation stabilization time of the crystal oscillation differs according to the constant of the mounting circuit, floating capacitance, and so on, it should be determined in consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitance (Cin and Cout) near this LSI (in order to prevent operation failure from occurring after a noise is externally inducted to the EXTAL2 and XTAL2 pins). Figure 21.7 Note on Using Crystal Resonator 21.7 Power-On Reset/Clock-Resume Control Circuit The BT of this LSI allows direct connection to the RF IC and thus minimizes the need for externally connected components. 21.7.1 Power-On Reset The clock, which is input from the HD157100NP RF IC or HD157102NP (Renesas) and is used for the interface with the RF IC, may be used as the main clock of this LSI (see figure 21.2). The RF IC (Renesas) starts outputting a clock signal after a certain period of time following the negation of a power-on reset. However, the input of a clock signal to this LSI is required to settle the oscillation of the on-chip oscillator during reset. For this reason, the LSI's internal reset signal is kept at a low level after negation of the external power-on reset signal. The internal reset signal is only negated after the required period from the application of an external clock signal has elapsed. The timing chart for this is shown in figure 21.8. There are two types of the internal reset signals for the USB and the other modules. The required period of the internal reset signal for the USB being asserted is different from that of the others. The timing chart is shown in figure 21.8. Rev. 1.00, 02/04, page 621 of 804 RESETP RF IC output clock 1312 cycles Internal reset signal Internal reset signal for USB 256 cycles Figure 21.8 Timing Chart of Reset Signal 21.7.2 Clock-Resume Control In the power-down modes, a command that stops the output of the clock from the RF IC may be sent to the RF IC. When the clock input from the RF IC is used as the main clock of this LSI, this LSI is also stopped and the BT is operated by a separately input clock running at 32-kHz or 32.768-kHz. The LSI is equipped with a clock-resume control function to allow it to leave this mode. The sequence of this clock-resume control is given below. 1. 2. 3. 4. The BT outputs an interrupt signal. The BT issues a wake-up command to the RF-IC. The INTC receives an interrupt. The CPU is activated. 21.8 Bluetooth HCI/TCI Commands and API To configure the upper protocol stack, this LSI supports host controller interface (HCI) and test control interface (TCI) commands which are defined by version 1.1 of the Bluetooth Specification, and 53 types of unique TCI commands. For details on the HCI and TCI commands, which correspond to version 1.1 of the Bluetooth Specification, refer to version 1.1 of the Bluetooth Specification. When detailed information on unique TCI commands is required, contact our sales department. The protocol stack firmware lower than the HCI is provided as a library in this LSI, and this enables the Bluetooth interface easily to be added to a developed program. In addition, as the application interface (API) of this library bases on H4 of the Bluetooth Specification, it is easy to be applied to this LSI. As the API function of this LSI, 9 types of functions are prepared. For details, contact our sales department. Rev. 1.00, 02/04, page 622 of 804 Section 22 D/A Converter (DAC) 22.1 Features This LSI incorporates a two-channel D/A converter (DAC) with the following features. * * * * 8-bit resolution Two output channels Conversion time: Min. 10 s (when load capacitance is 20 pF) Output voltage: 0 V to AVcc (analog power supply) Figure 22.1 shows the block diagram of the DAC. DA0 DA1 Analog I/O buffer DAO0 DAO1 DACR DAC0 DAC1 Control circuit Module data bus 8-bit D/A converter DADR_1 Bus interface AVcc AVss Vccaa Vssaa DADR_0 Peripheral data bus Internal peripheral clock (Po) [Legend] DACR: D/A control register DADR_0: D/A data register 0 DADR_1: D/A data register 1 AVcc: Analog power supply AVss: Analog ground DAO0: Analog output 0 DAO1: Analog output 1 D/A converter circuit Figure 22.1 Block Diagram of DAC Rev. 1.00, 02/04, page 623 of 804 22.2 Input/Output Pins Table 22.1 summarizes the input/output pins used by the DAC. Table 22.1 Pin Configuration Pin Name Avcc Avss DA0 DA1 I/O -- -- Output Output Function Analog block power supply and D/A conversion reference voltage Analog block ground Channel 0 analog output Channel 1 analog output 22.3 Register Descriptions The DAC has the following registers. Refer to section 27, List of Registers, for more details of the addresses of these registers and the state of these registers in each processor mode. * D/A data register 0 (DADR_0) * D/A data register 1 (DADR_1) * D/A control register (DACR) 22.3.1 D/A Data Registers 0 and 1 (DADR_0, DADR_1) DADR_0 and DADR_1 are 8-bit readable/writable registers that store data for D/A conversion. When the D/A output enable bits (DAOE1, DAOE0) of the DA control register (DACR) are set to 1, the contents of the D/A data register (DADR_0, DADR_1) are converted and output to analog output pins (DA0, DA1). The D/A data register (DADR_0, DADR_1) is initialized to H'00 at a reset. Note that DADR_0 and DADR_1 are not initialized in software standby or module standby. Bit 7 to 0 Bit Name Initial Value H'00 R/W R/W Description 8-bit registers that store data for D/A conversion. Rev. 1.00, 02/04, page 624 of 804 22.3.2 D/A Control Register (DACR) DACR is an 8-bit readable/writable register that controls the DAC operation. DACR is initialized to H'3F at a reset. Note that DACR is not initialized in software standby or module standby. Bit 7 Initial Bit Name Value DAOE1 0 R/W R/W Description Controls D/A conversion for channel 1 and analog output. 0: D/A conversion for channel 1 and analog output (DA1) are disabled 1: D/A conversion for channel 1 and analog output (DA1) are enabled 6 DAOE0 0 R/W Controls D/A conversion for channel 0 and analog output. 0: D/A conversion for channel 0 and analog output (DA0) are disabled 1: D/A conversion for channel 0 and analog output (DA0) are enabled 5 to 0 -- All 1 R Reserved These bits are always read as 1. The write value should always be 1. If 0 is written to these bits, correct operation cannot be guaranteed. 22.4 Operation The DAC incorporates two D/A channels that can operate individually. The DAC executes D/A conversion while analog output is enabled by the D/A control register (DACR). If the D/A data registers (DADR_0 and DADR_1) are modified, the D/A converter immediately initiates the new data conversion. When the DAOE1 and DAOE0 bits in the DACR register are set to 1, D/A conversion results are output. An example of D/A conversion for channel 0 is shown below. The operation timing is shown in figure 22.2. 1. Write conversion data to DADR_0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. The results are output after the conversion has ended. The output value will be (DADR_0 contents/256) x AVcc. The conversion results are output continuously until DADR_0 is modified or the DAOE0 bit is cleared to 0. Rev. 1.00, 02/04, page 625 of 804 3. When D/A data register 0 (DADR_0) is modified, the conversion starts again. The results are output after the conversion has ended. 4. When the DAOE0 in the DACR bit is cleared to 0, analog output is disabled (high-impedance state). DADR_0 DACR write cycle write cycle DADR_0 write cycle DACR write cycle P Address bus DADR_0 Conversion data (1) Conversion data (2) DAOE0 Conversion result (2) tDCONV DA0 High impedance state [Legend] tDCONV: D/A conversion time tDCONV Conversion result (1) Figure 22.2 D/A Converter Operation Example Rev. 1.00, 02/04, page 626 of 804 Section 23 I/O Ports This LSI has six I/O ports (ports A, B, D, E, G and H). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control). Each port has a data register which stores data for the pins. 23.1 Port A Port A is a 7-bit input/output port with the pin configuration shown in figure 23.1. Each pin has an input pull-up MOS, which is controlled by the port A control register (PACR) in the PFC. Port A PTA6 (input/output) / SIOF_SS2 (output) PTA5 (input/output) / SIOF_SS1 (output) PTA4 (input/output) / SIOF_SCK(SCK) (input/output) PTA3 (input/output) / SIOF_SYNC(SIOF_ SS0) (input/output) PTA2 (input/output) / SIOF_RXD(MISO) (input) PTA1 (input/output) / SIOF_TXD(MOSI) (output) PTA0 (input/output) / SIOF_MCLK (input) Figure 23.1 Port A 23.1.1 Register Description Port A has the following register. Refer to section 27, List of Registers, for the address of this register and state of this register in each processing mode. * Port A data register (PADR) Rev. 1.00, 02/04, page 627 of 804 23.1.2 Port A Data Register (PADR) PADR is a 7-bit readable/writable register that stores data for pins PTA6 to PTA0. Bits PA6DT to PA0DT correspond to pins PTA6 to PTA0. When the pin function is general output port, if the port is read, the value of the corresponding PADR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 6 5 4 3 2 1 0 PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Table 23.1 shows the function of PADR. Table 23.1 Port A Data Register (PADR) Read/Write Operations PACR State*1 PAnMD1*2 PAnMD0*2 Pin State 0 0 1 1 0 1 Other function Output Read PADR value PADR value Write Value is written to PADR, but does not affect pin state. Write value is output from pin. Value is written to PADR, but does not affect pin state. Value is written to PADR, but does not affect pin state. Input (Pull-up Pin state MOS on) Input (Pull-up Pin state MOS off) Notes: 1. For details on PACR, refer to section 24, Pin Function Controller (PFC). 2. n = 0 to 6 Rev. 1.00, 02/04, page 628 of 804 23.2 Port B Port B is an 8-bit input/output port with the pin configuration shown in figure 23.2. Each pin has an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC. PTB7 (input/output) / BS (output) PTB6 (input/output) / REFOUT (output) PTB5 (input/output) / RD/WR (output) Port B PTB4 (input/output) / RAS (output) PTB3 (input/output) / CAS (output) PTB2 (input/output) / CKE (output) PTB1 (input/output) / IRQ1 (input) PTB0 (input/output) / IRQ0 (input) Figure 23.2 Port B 23.2.1 Register Description Port B has the following register. Refer to section 27, List of Registers, for the address of this register and state of this register in each processing mode. * Port B data register (PBDR) 23.2.2 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores data for pin PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0. When the pin function is general output port, if the port is read, the value of the corresponding PBDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 23.2 shows the function of PBDR. Description Rev. 1.00, 02/04, page 629 of 804 Table 23.2 Port B Data Register (PBDR) Read/Write Operations PBCR State*1 PBnMD1*2 PBnMD0*2 Pin State 0 0 1 1 0 1 Other function Output Read Write PBDR value Value is written to PBDR, but does not affect pin state. PBDR value Write value is output from pin. Value is written to PBDR, but does not affect pin state. Value is written to PBDR, but does not affect pin state. Input (Pull-up Pin state MOS on) Input (Pull-up Pin state MOS off) Notes: 1. For details on PBCR, refer to section 24, Pin Function Controller (PFC). 2. n = 0 to 7 Rev. 1.00, 02/04, page 630 of 804 23.3 Port D Port D is a 6-bit input/output port with the pin configuration shown in figure 23.3. Each pin has an input pull-up MOS, which is controlled by the port D control register (PDCR) in the PFC. Port D PTD5 (input/output) / A23 (output) PTD4 (input/output) / A22 (output) PTD3 (input/output) / A21 (output) PTD2 (input/output) / A20 (output) PTD1 (input/output) / A19 (output) PTD0 (input/output) / A0 (output) Figure 23.3 Port D 23.3.1 Register Description Port D has the following register. Refer to section 27, List of Registers, for the address of this register and state of this register in each processing mode. * Port D data register (PDDR) 23.3.2 Port D Data Register (PDDR) PDDR is a 6-bit readable/writable register that stores data for pins PTD5 to PTD0. Bits PD5DT to PD0DT correspond to pins PTD5 to PTD0. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Bit 7, 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 5 4 3 2 1 0 PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Rev. 1.00, 02/04, page 631 of 804 Table 23.3 shows the function of PDDR. Table 23.3 Port D Data Register (PDDR) Read/Write Operations PDCR State*1 PDnMD1*2 PDnMD0*2 Pin State 0 0 1 1 0 1 Other function Output Read Write PDDR value Value is written to PDDR, but does not affect pin state. PDDR value Write value is output from pin. Value is written to PDDR, but does not affect pin state. Value is written to PDDR, but does not affect pin state. Input (Pull-up Pin state MOS on) Input (Pull-up Pin state MOS off) Notes: 1. For details on PDCR, refer to section 24, Pin Function Controller (PFC). 2. n = 0 to 5 Rev. 1.00, 02/04, page 632 of 804 23.4 Port E Port E is a 7-bit input/output port with the pin configuration shown in figure 23.4. Each pin has an input pull-up MOS, which is controlled by the port E control register (PECR) in the PFC. Port E PTE6 (input/output) / RDI_CRTRL2 (output) / IRQOUT (output) PTE5 (input/output) / VCI_HWC (output) PTE4 (input/output) / VCI_SCO_SYNC_OUT (output) / BREQ (input) PTE3 (input/output) / VCI_SCO_CLK_OUT (output) / BACK (output) PTE2 (input/output) / VCI_SCO_RX (output) / DREQ (input) PTE1 (input/output) / VCI_SCO_TX (input) / DACK (output) PTE0 (input/output) / VCI_CODEC_PWRDWN (output) / TEND (output) Figure 23.4 Port E 23.4.1 Register Description Port E has the following register. Refer to section 27, List of Registers, for the address of this register and state of this register in each processing mode. * Port E data register (PEDR) 23.4.2 Port E Data Register (PEDR) PEDR is a 7-bit readable/writable register that stores data for pins PTE6 to PTE0. Bits PE6DT to PE0DT correspond to pins PTE6 to PTE0. When the pin function is general output port, if the port is read, the value of the corresponding PEDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Rev. 1.00, 02/04, page 633 of 804 Bit 7 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 6 5 4 3 2 1 0 PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Table 23.4 shows the function of PEDR. Table 23.4 Port E Data Register (PEDR) Read/Write Operations PECR State*1 PEnMD1*2 PEnMD0*2 Pin State 0 0 1 1 0 1 Other function Output Read Write PEDR value Value is written to PEDR, but does not affect pin state. PEDR value Write value is output from pin. Value is written to PEDR, but does not affect pin state. Value is written to PEDR, but does not affect pin state. Input (Pull-up Pin state MOS on) Input (Pull-up Pin state MOS off) Notes: 1. For details on PECR, refer to section 24, Pin Function Controller (PFC). 2. n = 0 to 6 Rev. 1.00, 02/04, page 634 of 804 23.5 Port G Port G is a 5-bit input/output port with the pin configuration shown in figure 23.5. Each pin has an input pull-up MOS, which is controlled by the port G control register (PGCR) in the PFC. Port G PTG4 (input/output) / SCIF0_ CTS (input) PTG3 (input/output) / SCIF0_ RTS (output) PTG2 (input/output) / SCIF0_RxD (input) PTG1 (input/output) / SCIF0_ TxD (output) PTG0 (input/output) / SCIF0_SCK (input/output) / IRQ3 (input) Figure 23.5 Port G 23.5.1 Register Description Port G has the following register. Refer to section 27, List of Registers, for the address of this register and state of this register in each processing mode. * Port G data register (PGDR) Rev. 1.00, 02/04, page 635 of 804 23.5.2 Port G Data Register (PGDR) PGDR is a 5-bit readable/writable register that stores data for pins PTG4 to PTG0. Bits PG4DT to PG0DT correspond to pins PTG4 to PTG0. When the pin function is general output port, if the port is read, the value of the corresponding PGDR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. If the TE or RE bit is set to 1 in the serial control register _0 (SCSCR_0) of the serial communication interface with FIFO (SCIF), the SCIF0_TxD or SCIF0_RxD is selected regardless of the PGCR register setting. Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 4 3 2 1 0 PG4DT PG3DT PG2DT PG1DT PG0DT 0 0 0 0 0 R/W R/W R/W R/W R/W Table 23.5 shows the function of PGDR. Table 23.5 Port G Data Register (PGDR) Read/Write Operations PGCR State*1 PGnMD1*2 PGnMD0*2 Pin State 0 0 1 1 0 1 Other function Output Read Write PGDR value Value is written to PGDR, but does not affect pin state. PGDR value Write value is output from pin. Value is written to PGDR, but does not affect pin state. Value is written to PGDR, but does not affect pin state. Input (Pull-up Pin state 3 MOS on)* Input (Pull-up Pin state MOS off)*3 Notes: 1. For details on PGCR, refer to section 24, Pin Function Controller (PFC). 2. n = 0 to 4 3. When n = 1, pin state is a high impedance (output). Rev. 1.00, 02/04, page 636 of 804 23.6 Port H Port H is a 5-bit input/output port with the pin configuration shown in figure 23.6. Each pin has an input pull-up MOS, which is controlled by the port H control register (PHCR) in the PFC. Port H PTH4 (input/output) / SCIF1_ CTS (input) PTH3 (input/output) / SCIF1_ RTS (output) PTH2 (input/output) / SCIF1_RxD (input) PTH1 (input/output) / SCIF1_ TxD (output) PTH0 (input/output) / SCIF1_SCK (input/output) / IRQ4 (input) Figure 23.6 Port H 23.6.1 Register Description Port H has the following register. Refer to section 27, List of Registers, for the address of this register and state of this register in each processing mode. * Port H data register (PHDR) 23.6.2 Port H Data Register (PHDR) PHDR is a 5-bit readable/writable register that stores data for pins PTH4 to PTH0. Bits PH4DT to PH0DT correspond to pins PTH4 to PTH0. When the function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. If the TE or RE bit is set to 1 in the serial control register _1 (SCSCR_1) of the serial communication interface with FIFO (SCIF), the SCIF1_TxD or SCIF1_RxD is selected regardless of the PHCR register setting. Rev. 1.00, 02/04, page 637 of 804 Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 4 3 2 1 0 PH4DT PH3DT PH2DT PH1DT PH0DT 0 0 0 0 0 R/W R/W R/W R/W R/W Table 23.6 shows the function of PHDR. Table 23.6 Port H Data Register (PHDR) Read/Write Operations PHCR State*1 PHnMD1*2 PHnMD0*2 Pin State 0 0 1 1 0 1 Other function Output Read Write PHDR value Value is written to PHDR, but does not affect pin state. PHDR value Write value is output from pin. Value is written to PHDR, but does not affect pin state. Value is written to PHDR, but does not affect pin state. Input (Pull-up Pin state MOS on)*3 Input (Pull-up Pin state MOS off)*3 Notes: 1. For details on PHCR, refer to section 24, Pin Function Controller (PFC). 2. n = 0 to 4 3. When n = 1, pin state is a high impedance (output). Rev. 1.00, 02/04, page 638 of 804 Section 24 Pin Function Controller (PFC) 24.1 Overview Some pins in this LSI are multiplexed with I/O port functions (for details on this I/O port refer to section 23, I/O Ports). The pin function controller (PFC) consists of registers to select the pin functions and I/O directions of multiplex pins. Pin functions and I/O directions can be individually selected for every pin regardless of the LSI operating mode. Table 24.1 lists the multiplex pins of this LSI. In the table, pin functions in the shaded column can be used immediately after resetting. Table 24.1 Multiplex Pins Port A A A A A A A B B B B B B B B D D D D D D Function 1 (Related Module) PTA6 input/output (port) PTA5 input/output (port) PTA4 input/output (port) PTA3 input/output (port) PTA2 input/output (port) PTA1 input/output (port) PTA0 input/output (port) PTB7 input/output (port) PTB6 input/output (port) PTB5 input/output (port) PTB4 input/output (port) PTB3 input/output (port) PTB2 input/output (port) PTB1 input/output (port) PTB0 input/output (port) PTD5 input/output (port) PTD4 input/output (port) PTD3 input/output (port) PTD2 input/output (port) PTD1 input/output (port) PTD0 input/output (port) Function 2 (Related Module) SIOF_SS2 output (SIOF) SIOF_SS1 output (SIOF) Function 3 (Related Module) SIOF_SCK (SCK) input/output (SIOF) SIOF_SYNC (SIOF_SS0) input/output (SIOF) SIOF_RXD (MISO) input (SIOF) SIOF_TXD (MOSI) output (SIOF) SIOF_MCLK input (SIOF) BS output (BSC) REFOUT output (BSC) RD/WR output (BSC) RAS output (BSC) CAS output (BSC) CKE output (BSC) IRQ2 input (INTC) IRQ0 input (INTC) A23 output (BSC) A22 output (BSC) A21 output (BSC) A20 output (BSC) A19 output (BSC) A0 output (BSC) Rev. 1.00, 02/04, page 639 of 804 Port E E E E E E E G G G G G H H H H H Function 1 (Related Module) PTE6 input/output (port) PTE5 input/output (port) PTE4 input/output (port) PTE3 input/output (port) PTE2 input/output (port) PTE1 input/output (port) PTE0 input/output (port) PTG4 input/output (port) PTG3 input/output (port) PTG2 input/output (port) PTG1 input/output (port) PTG0 input/output (port) PTH4 input/output (port) PTH3 input/output (port) PTH2 input/output (port) PTH1 input/output (port) PTH0 input/output (port) Function 2 (Related Module) RDI_CTRL2 output (BT) VCI_HWC output (BT) VCI_SCO_SYNC_OUT output (BT) VCI_SCO_CLK_OUT output (BT) VCI_SCO_RX output (BT) VCI_SCO_TX input (BT) VCI_CODEC_PWRDWN output (BT) SCIF0_CTS input (SCIF0) SCIF0_RTS output (SCIF0) SCIF0_RxD input (SCIF0) SCIF0_TxD output (SCIF0) SCIF0_SCK input/output (SCIF0) SCIF1_CTS input (SCIF1) SCIF1_RTS output (SCIF1) SCIF1_RxD input (SCIF1) SCIF1_TxD output (SCIF1) SCIF1_SCK input/output (SCIF1) Function 3 (Related Module) IRQOUT output (INTC) BREQ input (BSC) BACK output (BSC) DREQ input (DMAC) DACK output (DMAC) TEND output (DMAC) IRQ3 input (INTC) IRQ4 input (INTC) Rev. 1.00, 02/04, page 640 of 804 24.2 Register Descriptions PFC has the following registers. For details on register addresses and register states in each operation mode, refer to section 27, List of Registers. * * * * * * * * * Port A control register (PACR) Port B control register (PBCR) Port D control register (PDCR) Port E control register (PECR) Port G control register (PGCR) Port H control register (PHCR) Pin select register A (PSELA) I/O buffer Hi-Z control register A (HIZCRA) Noise canceller control register (NCCR) Note: The PFC registers are not initialized by a manual reset and hold the contents. 24.2.1 Port A Control Register (PACR) PACR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Bit 15, 14 Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 13 12 PA6MD1 PA6MD0 1 0 R/W R/W PTA6 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 11 10 PA5MD1 PA0MD0 1 0 R/W R/W PTA5 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Rev. 1.00, 02/04, page 641 of 804 Bit 9 8 Bit Name PA4MD1 PA4MD0 Initial Value* 1 0 R/W R/W R/W Description PTA4 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 7 6 PA3MD1 PA3MD0 1 0 R/W R/W PTA3 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 5 4 PA2MD1 PA2MD0 1 0 R/W R/W PTA2 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 3 2 PA1MD1 PA1MD0 1 0 R/W R/W PTA1 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 1 0 PA0MD1 PA0MD0 1 0 R/W R/W PTA0 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Note: * This register is not initialized by a manual reset and holds the contents. Rev. 1.00, 02/04, page 642 of 804 24.2.2 Port B Control Register (PBCR) PBCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Bit 15 14 Bit Name PB7MD1 PB7MD0 Initial Value* 0 0 R/W R/W R/W Description PTB7 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 13 12 PB6MD1 PB6MD0 0 0 R/W R/W PTB6 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 11 10 PB5MD1 PB5MD0 0 0 R/W R/W PTB5 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 9 8 PB4MD1 PB4MD0 0 0 R/W R/W PTB4 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 7 6 PB3MD1 PB3MD0 0 0 R/W R/W PTB3 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 5 4 PB2MD1 PB2MD0 0 0 R/W R/W PTB2 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Rev. 1.00, 02/04, page 643 of 804 Bit 3 2 Bit Name PB1MD1 PB1MD0 Initial Value* 1 0 R/W R/W R/W Description PTB1 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 1 0 PB0MD1 PB0MD0 1 0 R/W R/W PTB0 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Note: * This register is not initialized by a manual reset and holds the contents. 24.2.3 Port D Control Register (PDCR) PDCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Bit 15 to 12 Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. PD5MD1 PD5MD0 0 0 R/W R/W PTD5 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 9 8 PD4MD1 PD4MD0 0 0 R/W R/W PTD4 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 11 10 Rev. 1.00, 02/04, page 644 of 804 Bit 7 6 Bit Name PD3MD1 PD3MD0 Initial Value* 0 0 R/W R/W R/W Description PTD3 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 5 4 PD2MD1 PD2MD0 0 0 R/W R/W PTD2 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 3 2 PD1MD1 PD1MD0 0 0 R/W R/W PTD1 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 1 0 PD0MD1 PD0MD0 0 0 R/W R/W PTD0 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Note: * This register is not initialized by a manual reset and holds the contents. Rev. 1.00, 02/04, page 645 of 804 24.2.4 Port E Control Register (PECR) PECR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Bit 15, 14 Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 13 12 PE6MD1 PE6MD0 1 0 R/W R/W PTE6 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 11 10 PE5MD1 PE5MD0 1 0 R/W R/W PTE5 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 9 8 PE4MD1 PE4MD0 0 0 R/W R/W PTE4 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 7 6 PE3MD1 PE3MD0 0 0 R/W R/W PTE3 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 5 4 PE2MD1 PE2MD0 1 0 R/W R/W PTE2 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Rev. 1.00, 02/04, page 646 of 804 Bit 3 2 Bit Name PE1MD1 PE1MD0 Initial Value* 1 0 R/W R/W R/W Description PTE1 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 1 0 PE0MD1 PE0MD0 1 0 R/W R/W PTE0 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Note: * This register is not initialized by a manual reset and holds the contents. 24.2.5 Port G Control Register (PGCR) PGCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Bit Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 9 8 PG4MD1 PG4MD0 1 0 R/W R/W PTG4 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 7 6 PG3MD1 PG3MD0 1 0 R/W R/W PTG3 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 15 to 10 Rev. 1.00, 02/04, page 647 of 804 Bit 5 4 Bit Name PG2MD1 PG2MD0 Initial Value* 1 0 R/W R/W R/W Description PTG2 Mode When the RE bit in the SCSCR_0 register is 0: 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) When the RE bit in the SCSCR_0 register is 1: Regardless of the PG2MD1 or PG2MD0 bit setting, other functions (SCIF0_RxD) is selected. 3 2 PG1MD1 PG1MD0 1 0 R/W R/W PTG1 Mode When the TE bit in the SCSCR_0 register is 0: 00: Other functions (see table 24.1) 01: Port output 10: Output high-impedance state 11: Output high-impedance state When the TE bit in the SCSCR_0 register is 1: Regardless of the PG1MD1 or PG1MD0 bit setting, other function (SCIF0_TxD) is selected. 1 0 PG0MD1 PG0MD0 1 0 R/W R/W PTG0 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Note: * This register is not initialized by a manual reset and holds the contents. Rev. 1.00, 02/04, page 648 of 804 24.2.6 Port H Control Register (PHCR) PHCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Bit Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 9 8 PH4MD1 PH4MD0 1 0 R/W R/W PTH4 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 7 6 PH3MD1 PH3MD0 1 0 R/W R/W PTH3 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 5 4 PH2MD1 PH2MD0 1 0 R/W R/W PTH2 Mode When the RE bit in the SCSCR_1 register is 0: 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) When the RE bit in the SCSCR_1 is 1: Regardless of the PH2MD1 or PH2MD0 bit setting, other functions (SCIF1_RxD) is selected. 15 to10 Rev. 1.00, 02/04, page 649 of 804 Bit 3 2 Bit Name PH1MD1 PH1MD0 Initial Value* 1 0 R/W R/W R/W Description PTH1 Mode When the TE bit in the SCSCR_1 register is 0: 00: Other functions (see table 24.1) 01: Port output 10: Output high-impedance state 11: Output high-impedance state When the TE bit in the SCSCR_1 register is 1: Regardless of the PH1MD1 or PH1MD0 bit setting, other function (SCIF1_TxD) is selected. 1 0 PH0MD1 PH0MD0 1 0 R/W R/W PTH0 Mode 00: Other functions (see table 24.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Note: * This register is not initialized by a manual reset and holds the contents. 24.2.7 Pin Select Register A (PSELA) PSELA is a 16-bit readable/writable register that has two purposes. Bit 0 (RTCSEL1) selects a frequency for the low-frequency clock source that is used in the Bluetooth interface (BT). When a 32.000kHz clock is selected, the clock is input to the BT. When 32.768-kHz clock is selected, the clock is converted into a pseudo 32.000kHz clock by the frequency conversion circuit. For details, refer to section 21, Bluetooth Interface (BT). Bits 1 to 8 select the function for a pin multiplexed with two or more other functions. When one of the other functions are used, the corresponding bit in the PSELA should be specified before the other function is specified by the port control register. Setting example: To use IRQOUT function in the PTE6/RDI_CTRL2/IRQOUT pin 1. Write 1 to the PSA8 bit in the PSELA register. 2. Set the PE6MD1 and PE6MD0 bits in the port E control register (PECR) to (0.0) (other functions). Rev. 1.00, 02/04, page 650 of 804 Bit Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 15 to 9 8 PSA8 0 R/W RDI_CTRL2/IRQOUT Select 0 : Selects RDI_CTRL2 1 : Selects IRQOUT 7 PSA7 1 R/W VCI_SCO_SYNC_OUT/BREQ Select 0 : Selects VCI_SCO_SYNC_OUT 1 : Selects BREQ 6 PSA6 1 R/W VCI_SCO_CLK_OUT/BACK Select 0 : Selects VCI_SCO_CLK_OUT 1 : Selects BACK 5 PSA5 0 R/W VCI_SCO_RX/DREQ Select 0: Selects VCI_SCO_RX 1: Selects DREQ 4 PSA4 0 R/W VCI_SCO_TX/DACK Select 0: Selects VCI_SCO_TX 1: Selects DACK 3 PSA3 0 R/W VCI_CODEC_PWRDWN/TEND Select 0 : Selects VCI_CODEC_PWRDWN 1 : Selects TEND 2 PSA2 0 R/W SCIF0_SCK/IRQ3 Select 0 : Selects SCIF0_SCK 1 : Selects IRQ3 1 PSA1 0 R/W SCIF1_SCK/IRQ4 Select 0 : Selects SCIF1_SCK 1 : Selects IRQ4 0 RTCSEL 1 0 R/W Low-frequency clock frequency Select 0 : Selects 32.768-kHz 1 : Selects 32.000-kHz Note: * This register is not initialized by a manual reset and holds the contents. Rev. 1.00, 02/04, page 651 of 804 24.2.8 I/O Buffer Hi-Z Control Register A (HIZCRA) HIZCRA is a 16-bit readable/writable register that controls Hi-Z and pull-up for pins for every function unit*. Note: * Even if the output Hi-Z state is specified in the HIZCRA, the pull-up MOS remains turned on when port input (pull-up MOS: On) is selected in the PnCR. Bit Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. When writing 1, the operation of this LSI is not guaranteed. 8 HIZA8 0 R/W Controls high impedance for pins multiplexed with SIOF related signals (SIOF_RXD(MISO)/SIOF_TXD(MOSI)/SIOF_SYNC(SIOF _SS0)/SIOF_SS1/SIOF_SS2). 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 7 HIZA7 0 R/W Controls high impedance for pins multiplexed with SIOF related signals (SIOF_MCLK/SIOF_SCK(SCK)) 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 6 HIZA6 0 R/W Controls high impedance for pins multiplexed with SCIF0 related signals(SCIF0_RxD/SCIF0_TxD/SCIF0_RTS/SCIF0_CTS) 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 5 HIZA5 0 R/W Controls high impedance for pins multiplexed with SCIF0 related signals (SCIF0_SCK) 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 15 to 9 Rev. 1.00, 02/04, page 652 of 804 Bit 4 Bit Name HIZA4 Initial Value* 0 R/W R/W Description Controls high impedance for pins multiplexed with SCIF1 related signals (SCIF1_RxD/SCIF1_TxD/SCIF1_RTS/SCIF1_CTS) 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 3 HIZA3 0 R/W Controls high impedance for pins multiplexed with SCIF1 related signals (SCIF1_SCK) 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 2 HIZA2 0 R/W Controls high impedance for pins multiplexed with RD/WR/RAS/CAS/CKE 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters output Hi-Z state. 1 HIZA1 0 R/W Controls high impedance for IRQ2 pins 0 : I/O buffer enters normal operation mode 1 : Input buffer is an OFF state, and I/O buffer enters 1 output Hi-Z state.* 0 HIZA0 0 R/W Controls high impedance for IRQ0 pins 0 : I/O buffer enters normal operation mode. 1 : Input buffer is an OFF state, and I/O buffer enters 2 output Hi-Z state.* Notes: 1. This register is not initialized by a manual reset and holds the contents. 2. With this setting Shmidt input is selected. Rev. 1.00, 02/04, page 653 of 804 24.2.9 Noise Canceller Control Register (NCCR) NCCR is a readable/writable 16-bit register that controls the Noise Canceller On/Off state. Bit 15 to 1 Bit Name Initial Value* All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 0 NCCR0 0 R/W Controls the Noise Canceller in the TRST, NMI and IRQ registers. 0 : Noise Canceller off 1 : Noise Canceller on Note: * This register is not initialized by a manual reset and holds the contents. Rev. 1.00, 02/04, page 654 of 804 Section 25 User Break Controller The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. 25.1 Features The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle). Address Comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc. One of the four address buses (L-bus address (LAB), I-bus address(IAB), X-memory address bus (XAB), and Y-memory address bus (YAB)) can be selected. Data Only on channel B, 32-bit maskable. One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB) and Y-memory data bus (YDB)) can be selected. Bus cycle Instruction fetch or data access Read/write Operand size Byte, word, and longword 2. A user-designed user-break condition exception processing routine can be run. 3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. 4. Maximum repeat times for the break condition (only for channel B): 212 - 1 times. 5. Eight pairs of branch source/destination buffers. Rev. 1.00, 02/04, page 655 of 804 Figure 25.1 shows a block diagram of the UBC. XAB/YAB IAB LAB Access comparator Internal bus Access control BBRA BARA Address comparator BAMRA Channel A Access comparator BBRB BARB Address comparator BAMRB Data comparator Channel B BDRB BDMRB BETR BRSR PC trace BRDR Control BRCR LDB/IDB/ XDB/YDB Legend BBRA BARA BAMRA BBRB BARB BAMRB CPU state signals User break request : Break bus cycle register A : Break address register A : Break address mask register A : Break bus cycle register B : Break address register B : Break address mask register B BDRB BDMRB BETR BRSR BRDR BRCR : Break data register B : Break data mask register B : Break execution times register : Branch source register : Branch destination register : Break control register Figure 25.1 Block Diagram of User Break Controller Rev. 1.00, 02/04, page 656 of 804 25.2 Register Descriptions The UBC has the following registers. For details on register addresses and access sizes, refer to section 27, List of Registers. * * * * * * * * * * * * Break address register A (BARA) Break address mask register A (BAMRA) Break bus cycle register A (BBRA) Break address register B (BARB) Break address mask register B (BAMRB) Break bus cycle register B (BBRB) Break data register B (BDRB) Break data mask register B (BDMRB) Break control register (BRCR) Execution times break register (BETR) Branch source register (BRSR) Branch destination register (BRDR) Break Address Register A (BARA) 25.2.1 BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit Bit Name Initial Value All 0 R/W Description R/W Break Address A Store the address on the LAB or IAB specifying break conditions of channel A. 31 to 0 BAA31 to BAA0 Rev. 1.00, 02/04, page 657 of 804 25.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit Bit Name Initial Value R/W Description R/W Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 31 to 0 BAMA31 to BAMA0 All 0 25.2.3 Break Bus Cycle Register A (BBRA) BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. Bit Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 7 6 CDA1 CDA0 0 0 R/W L Bus Cycle/I Bus Cycle Select A R/W Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle 15 to 8 Rev. 1.00, 02/04, page 658 of 804 Bit 5 4 Bit Name IDA1 IDA0 Initial Value 0 0 R/W Description R/W Instruction Fetch/Data Access Select A R/W Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R/W Read/Write Select A R/W Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZA1 SZA0 0 0 R/W Operand Size Select A R/W Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Rev. 1.00, 02/04, page 659 of 804 25.2.4 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address buses for break condition B. Bit Bit Name Initial Value R/W Description R/W Break Address B Stores an address which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0. If the X memory is selected in BBRB, the values in bits 15 to 1 in XAB are set in BAB31 to BAB17. In this case, the values in BAB16 to BAB0 are arbitrary. If the Y memory is selected in BBRB, the values in bits 15 to 1 in YAB are set in BAB15 to BAB1. In this case, the values in BAB31 to BAB16 are arbitrary. 31 to 0 BAB31 to BAB 0 All 0 Table 25.1 Specifying Break Address Register Bus Selection in BBRB L bus I bus X bus Y bus XAB15 to XAB1 Don't care BAB31 to BAB17 BAB16 BAB15 to BAB1 BAB0 LAB31 to LAB0 IAB31 to IAB0 Don't care Don't care Don't care YAB15 to YAB1 Don't care Don't care Rev. 1.00, 02/04, page 660 of 804 25.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit Bit Name Initial Value R/W Description R/W Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 31 to 0 BAMB31 to BAMB0 All 0 25.2.6 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. The control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four data buses for break condition B. Bit Bit Name Initial Value R/W Description All 0 R/W Break Data Bit B Stores data which specifies a break condition in channel B. If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. If the X memory is selected in BBRB, the break data in bits 15 to 0 in XDB is set in BDB31 to BDB16. In this case, the values in BDB15 to BDB0 are arbitrary. If the Y memory is selected in BBRB, the break data in bits 15 to 0 in YDB are set in BDB15 to BDB0. In this case, the values in BDB31 to BDB16 are arbitrary. 31 to 0 BDB31 to BDB0 Rev. 1.00, 02/04, page 661 of 804 Table 25.2 Specifying Break Data Register Bus Selection in BBRB L bus I bus X bus Y bus XDB15 to XDB0 Don't care BDB31 to BDB16 BDB15 to BDB0 LDB31 or LDB0 IDB31 to IDB0 Don't care YDB15 to YDB0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. 3. Set the data in bits 31 to 16 when including the value of the data bus as an L-bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction. 25.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit Bit Name Initial Value R/W Description R/W Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB. 3. Set the mask data in bits 31 to 16 when including the value of the data bus as an L-bus break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction. 31 to 0 BDMB31 to BDMB 0 All 0 Rev. 1.00, 02/04, page 662 of 804 25.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) X bus or Y bus, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 9 XYE 0 R/W Selects the X memory bus or Y memory bus as the channel B break condition. Note that this bit setting is enabled only when the L bus is selected with the CDB1 and CDB0 bits. Selection between the X memory bus and Y memory bus is done by the XYS bit. 0: Selects L bus for the channel B break condition unconditionally 1: Selects X/Y memory bus for the channel B break condition 8 XYS 0 R/W Selects the X bus or the Y bus as the bus of the channel B break condition. 0: Selects the X bus for the channel B break condition 1: Selects the Y bus for the channel B break condition 7 6 CDB1 CDB0 0 0 R/W R/W L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle 5 4 IDB1 IDB0 0 0 R/W R/W Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 15 to 10 Rev. 1.00, 02/04, page 663 of 804 Bit 3 2 Bit Name RWB1 RWB0 Initial Value 0 0 R/W R/W R/W Description Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZB1 SZB0 0 0 R/W R/W Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access 25.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Rev. 1.00, 02/04, page 664 of 804 Bit 31 to 16 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches 13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches 12 SCMFDB 0 R/W I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches 11 PCTE 0 R/W PC Trace Enable 0: Disables PC trace 1: Enables PC trace 10 PCBA 0 R/W PC Break Select A Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution Rev. 1.00, 02/04, page 665 of 804 Bit 9, 8 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 7 DBEB 0 R/W Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution 5, 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 3 SEQ 0 R/W Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2, 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 0 ETBE 0 R/W Number of Execution Times Break Enable Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B Rev. 1.00, 02/04, page 666 of 804 25.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 - 1 times. When a break condition is satisfied, it decreases BETR. A break is issued when the break condition is satisfied after BETR becomes H'0001. Bit Bit Name Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. If 1 is written to these bits, correct operation cannot be guaranteed. 11 to 0 BET11 to BET0 All 0 R/W Number of Execution Times 15 to 12 Note: If the break condition of channel B is a break condition of instruction fetch cycle and the break instructions correspond to the following instructions, the BETR is not decremented by 1 every time when a break is occurred. Refer to the following for the decremented value. Instruction RTE DMULS.L Rm, Rn DMULU.L Rm, Rn MAC.L @Rm+,@Rn+ MAC.W @Rm+,@Rn+ MUL.L Rm, Rn Countdown Value 4 2 2 2 2 3 3 3 3 3 3 4 4 Rev. 1.00, 02/04, page 667 of 804 AND.B #imm,@(R0, GBR) OR.B #imm,@(R0, GBR) TAS.B @Rn TST.B #imm,@(R0, GBR) XOR.B #imm,@(R0, GBR) LDC Rm,SR LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR LDC Rm,SPC LDC Rm,R0_BANK LDC Rm,R1_BANK LDC Rm,R2_BANK LDC Rm,R3_BANK LDC Rm,R4_BANK LDC Rm,R5_BANK LDC Rm,R6_BANK LDC Rm,R7_BANK LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+,R0_BANK LDC.L @Rm+,R1_BANK LDC.L @Rm+,R2_BANK LDC.L @Rm+,R3_BANK LDC.L @Rm+,R4_BANK LDC.L @Rm+,R5_BANK LDC.L @Rm+,R6_BANK LDC.L @Rm+,R7_BANK Rev. 1.00, 02/04, page 668 of 804 4 4 4 4 4 4 4 4 4 4 4 6 4 4 4 4 4 4 4 4 4 4 4 4 LDC.L @Rn+,MOD LDC.L @Rn+,RS LDC.L @Rn+,RE LDC Rn,MOD LDC Rn,RS LDC Rn,RE BRS label BSRF Rm JSR @Rm 4 4 4 4 4 4 2 2 2 25.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure and a stored register is shifted at every branch. Bit 31 Bit Name SVF Initial Value 0 R/W R Description BRSR Valid Flag Indicates whether the branch source address is stored. When a branch source address is fetched, this flag is set to 1. This flag is cleared to 0 by reading from BRSR. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 R Branch Source Address Store bits 27 to 0 of the branch source address. Rev. 1.00, 02/04, page 669 of 804 25.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers have a queue structure and a stored register is shifted at every branch. Bit 31 Bit Name DVF Initial Value 0 R/W Description R BRDR Valid Flag Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 by reading BRDR. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 R Branch Destination Address Store bits 27 to 0 of the branch destination address. Rev. 1.00, 02/04, page 670 of 804 25.3 25.3.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRB). The masked data is set in the break data mask register (BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with 00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. When the X/Y memory bus is specified for channel B, SCMFCB is used for the condition match flag. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. There is a chance that the break set in channel A and the break set in channel B occur around the same time. In this case, there will be only one break request to the CPU, but these two break channel match flags could be both set. 5. When selecting the I bus as the break condition, note the following: Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC monitors bus cycles generated by all bus masters, and determines the condition match. Physical addresses are used for the I bus. Set a physical address in break address registers (BARA and BARB). The bus cycles for logical addresses issued on the L bus by the CPU are converted to physical addresses before being output to the I bus. (If the address translation function is enabled, address translation by the MMU is carried out.) For data access cycles issued on the L bus by the CPU, if their logical addresses are not to be cached, they are issued with the data size specified on the L bus and their addresses are not rounded. For instruction fetch cycles issued on the L bus by the CPU, even though their logical addresses are not to be cached, they are issued in longwords and their addresses are rounded to match longword boundaries. Rev. 1.00, 02/04, page 671 of 804 If a logical address issued on the L bus by the CPU is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued in longwords and its address is rounded to match longword boundaries. However note that cache fill is not performed for a write miss in write through mode. In this case, the bus cycle is issued with the data size specified on the L bus and its address is not rounded. In write back mode, a write back cycle may be issued in addition to a read fill cycle. It is a longword bus cycle whose address is rounded to match longword boundaries. I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles. The DMAC only issues data access cycles for I bus cycles. If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the break is to be accepted cannot be clearly defined. 6. While the block bit (BL) in the CPU status register (SR) is set to 1, no breaks can be accepted. However, condition determination will be carried out, and if the condition matches, the corresponding condition match flag is set to 1. 25.3.2 Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A break cannot be generated as long as this bit is set to 1. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set for channel B, the break data register B (BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. Rev. 1.00, 02/04, page 672 of 804 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 25.3.1, Flow of the User Break Operation. 25.3.3 Break on Data Access Cycle 1. If the L bus is specified as a break condition for data access break, condition comparison is performed for the logical addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 25.3.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 25.3. Table 25.3 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Longword Word Byte Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on channel B: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register B (BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. Set the word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored). Rev. 1.00, 02/04, page 673 of 804 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the break will occur cannot be determined. When this kind of break occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. 25.3.4 Break on X/Y-Memory Bus Cycle 1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The break condition cannot include both X-memory and Y-memory at the same time. The break condition is applied to an X/Y-memory bus cycle by specifying L bus/data access cycle/read or write/word or no specified operand size (in bits 7 to 0) in the break bus cycle register B (BBRB). 2. When an X-memory address is selected as the break condition, specify an X-memory address in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for BDRB and BDMRB. 3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a data access break of the L bus. For details, see 5 in section 25.3.3, Break on Data Access Cycle. 25.3.5 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0. 2. In sequential break specification, the L/I/X/Y bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched. Rev. 1.00, 02/04, page 674 of 804 25.3.6 Value of Saved Program Counter When a break occurs, the address of the instruction from where execution is to be resumed is saved in the SPC, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the SPC. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the SPC. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the SPC. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the SPC. 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the SPC. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the SPC. 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the SPC. At which instruction the break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the SPC. If the instruction following the instruction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the SPC. Rev. 1.00, 02/04, page 675 of 804 25.3.7 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch. If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR. If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. When a repeat loop of the DSP extended function is used, control being transferred from the repeat end instruction to the repeat start instruction is not recognized as a branch, and the values are not stored in BRSR and BRDR. 3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. 25.3.8 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) * Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode Channel A Address: H'00000404, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Channel B Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) Rev. 1.00, 02/04, page 676 of 804 A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2) * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode Channel A Address: H'00037226, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Channel B Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed. (Example 1-3) * Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode Channel A Address: H'00027128, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Channel B Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. Rev. 1.00, 02/04, page 677 of 804 (Example 1-4) * Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode Channel A Address: H'00037226, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Channel B Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs. (Example 1-5) * Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode Channel A Address: H'00000500, Address mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword Channel B Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) On channel A, a user break occurs before an instruction of address H'00000500 is executed. On channel B, a user break occurs after the instruction of address H'00001000 are executed four times and before the fifth time. Rev. 1.00, 02/04, page 678 of 804 (Example 1-6) * Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode Channel A Address: H'00008404, Address mask: H'00000FFF Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Channel B Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. Break Condition Specified for L Bus Data Access Cycle: (Example 2-1) * Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Channel A Address: H'00123456, Address mask: H'00000000 Bus cycle: L bus/data access/read (operand size is not included in the condition) Channel B Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Rev. 1.00, 02/04, page 679 of 804 (Example 2-2) * Register specifications BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000, BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000, BRCR = H'00300080 Specified conditions: Channel A/channel B independent mode Channel A Address: H'01000000, Address mask: H'00000000 Bus cycle: L bus/data access/read/word Channel B Y Address: H'0000F000, Address mask: H'FFFF0000 Data: H'00004567, Data mask: H'00000000 Bus cycle: Y bus/data access/write/word On channel A, a user break occurs during word read from address H'01000000 in the memory space. On channel B, a user break occurs when word data H'4567 is written in address H'0000F000 in the Y memory space. The X/Y-memory space is changed by a mode setting. Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) * Register specifications BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Channel A Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition) Channel B Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314156 in the memory space. On channel B, a user break occurs when the I bus writes byte data H'7 in address H'00055555. Rev. 1.00, 02/04, page 680 of 804 25.4 Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 4.1 in section 4, Exception Handling. If an exception with higher priority occurs, the user break is not generated. Pre-execution break has the highest priority. When a post-execution break or data access break occurs simultaneously with a reexecution-type exception (including pre-execution break) that has higher priority, the reexecution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a break does not occur, the condition match flag is set. 5. Note the following exception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error by data access, the CPU address error is given priority to the break. Note that the UBC condition match flag is set in this case. 6. Note the following when a break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break does not occur until the branch destination of the RTE instruction. 7. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. 8. When the repeat loop of the DSP extended function is used, even though a break condition is satisfied during execution of the entire repeat loop or several instructions in the repeat loop, the break may be held. For details, see section 4, Exception Handling. Rev. 1.00, 02/04, page 681 of 804 Rev. 1.00, 02/04, page 682 of 804 Section 26 User Debugging Interface (H-UDI) This LSI incorporates a user debugging interface (H-UDI) and advanced user debugger (AUD) for a boundary scan function and emulator support. This section summarizes the boundary scan function for the H-UDI. For details on the JTAG function incorporated in this LSI, refer to the material separately handed, BSDL (Boundary-Scan Description Language). For details on the emulator functions such as the AUD, refer to the user's manual of each emulator. 26.1 Features The H-UDI is a serial I/O interface that conforms to JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture) specifications. The H-UDI in this LSI supports a boundary scan mode, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. When using the boundary scan function for the H-UDI, the ASEMD0 pin should be fixed to high level. For the method of connecting the emulator, refer to the emulator's user's manual. Figure 26.1 shows a block diagram of the H-UDI. TDI SDBPR Shift register SDBSR SDIR SDID TDO MUX TCK TMS TRST TAP controller Decoder Local bus Figure 26.1 Block Diagram of H-UDI Rev. 1.00, 02/04, page 683 of 804 26.2 Input/Output Pins Table 26.1 shows the pin configuration of the H-UDI. Table 26.1 Pin Configuration Pin Name TCK I/O Input Description Serial Data Input/Output Clock Pin Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. TMS Input Mode Select Input Pin The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol conforms to the JTAG standard (IEEE Std.1149.1). TRST Input Reset Input Pin Input is accepted asynchronously with respect to TCK, and when low, the H-UDI is reset. TRST must be low for a constant period when power is turned on regardless of using the H-UDI function. This is different from the JTAG standard. See section 26.4.2, Reset Configuration, for more information. TDI Input Serial Data Input Pin Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. TDO Output Serial Data Output Pin Data read from the H-UDI is executed by reading this pin in synchronization with TCK. The data output timing depends on the command type set in the SDIR. See section 26.3.2 Instruction Register (SDIR), for more information. ASEMD0 Input ASE Mode Select Pin If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered and the JTAG function can be used. In ASE mode, the dedicated emulator function can be used. The input to the ASEMD0 pin should be fixed to either high or low level. ASEBRKAK, AUDSYNC, AUDATA3 to AUDATA0, AUDCK Output Dedicated Emulator Pin Note: The ASEMD0 pin should be fixed to high level when using the boundary scan function. Rev. 1.00, 02/04, page 684 of 804 26.3 Register Descriptions The H-UDI has the following registers. For details on register addresses and register states in each processing state, see section 27, List of Registers*. * Bypass register (SDBPR) * Instruction register (SDIR) * Boundary scan register (SDBSR) * ID register (SDID) Note: * The H-UDI registers can be accessed from the CPU only when the emulator function is enabled in ASE mode. These registers function as part of the dedicated circuit for the JTAG function in normal mode (mode in which boundary scan function is used). Therefore, these registers should not be accessed from the CPU in normal mode. 26.3.1 Bypass Register (SDBPR) SDBPR is a 1-bit register that can be accessed only via the H-UDI pin. This register cannot be accessed from the CPU. When SDIR is set to bypass mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined. 26.3.2 Instruction Register (SDIR) SDIR is a 3-bit register in normal mode. This register can be written only via the H-UDI pin. This register cannot be accessed from the CPU. Undefined value is read even when this register is accessed from the CPU using the address which is listed in section 27, List of Registers. JTAG IDCODE is set in SDIR as the initial value. Operation is not guaranteed if a reserved command is set in SDIR. In ASE mode, SDIR is a 16-bit read-only register read from the CPU. The JTAG function is disabled. For details on the function of SDIR in ASE mode, refer to the emulator's user's manual. Bit 2 1 0 Bit Name TI2 TI1 TI0 Initial Value 1 0 0 R/W Description Test Instruction 2 to 0 The JTAG instruction is transferred to SDIR by a serial input from TDI. Cannot be accessed from the CPU for either read or write. For the commands, see table 26.2. Rev. 1.00, 02/04, page 685 of 804 Table 26.2 JTAG Commands Bits 2 to 0 TI2 0 0 0 0 1 1 1 1 TI1 0 0 1 1 0 0 1 1 TI0 0 1 0 1 0 1 0 1 Description JTAG EXTEST JTAG SAMPLE/PRELOAD Reserved Reserved JTAG IDCODE Reserved Reserved JTAG BYPASS (Initial value) 26.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register, located on the PAD, for controlling the input/output pins of this LSI. The initial value is undefined, and this register cannot be accessed from the CPU. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 26.3 gives the correspondence between the pins of the SH7660 and boundary scan register. Rev. 1.00, 02/04, page 686 of 804 Table 26.3 Correspondence between Pins of SH7660 and Boundary Scan Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTG3/SCIF0_RTS PTG2/SCIF0_RxD PTG1/SCIF0_TxD PTA6/SIOF_SS2 PTA5/SIOF_SS1 PTA4/SIOF_SCK PTA2/SIOF_RXD PTA1/SIOF_TXD PTA0/SIOF_MCLK Pin Name ASEBRKAK I/O IN Bit 33 Pin Name PTG4/SCIF0_CTS I/O IN Control OUT PTH1/SCIF1_TxD IN Control OUT PTH2/SCIF1_RxD IN Control OUT PTH3/SCIF1_RTS IN Control OUT PTH4/SCIF1_CTS IN Control OUT NMI PTH0/SCIF1_SCK/IRQ4 IN IN Control OUT PTG0/SCIF0_SCK/IRQ3 IN Control OUT PTB1/IRQ2 IN Control OUT PTB0/IRQ0 IN Control OUT RTCSEL0 USB_PWR_EN/USB_PULLUP IN IN Control OUT UCLK IN Rev. 1.00, 02/04, page 687 of 804 Control 34 OUT IN 35 36 Control 37 OUT IN 38 39 Control 40 OUT IN 41 42 Control 43 OUT PTA3/SIOF_SYNc (SIOF_SS0) IN 44 45 Control 46 OUT IN 47 48 Control 49 OUT IN 50 51 Control 52 OUT IN 53 54 Control 55 OUT IN 56 57 Control 58 OUT IN 59 60 Control 61 OUT IN 62 63 Control 64 OUT 65 Bit 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Pin Name UCLK I/O Bit Pin Name AUDSYNC AUDATA3 I/O OUT IN Control OUT Control 100 OUT 101 102 USB_OVR_CRNT/USB_VBUS IN Control 103 OUT CKIO IN 104 105 AUDATA2 IN Control OUT Control 106 OUT MD5 MD2 MD1 PTE6/RDI_CTRL2/IRQOUT IN IN IN IN 107 108 109 110 111 AUDATA0 AUDATA1 IN Control OUT IN Control OUT Control 112 OUT 113 AUDCK IN Control OUT PTE0/VCI_CODEC_PWRDWN IN 114 /TEND Control 115 OUT PTE1/VCI_SCO_TX/DACK IN 116 117 RD IN Control OUT Control 118 OUT PTE2/VCI_SCO_RX/DREQ IN 119 120 PTB7/BS IN Control OUT Control 121 OUT PTE3/VCI_SCO_CLK_OUT /BACK IN 122 123 WAIT WE1/DQM1 PTB6/REFOUT IN Control OUT IN IN Control OUT Control 124 OUT 125 126 PTE4/VCI_SCO_SYNC_OUT /BREQ IN Control 127 OUT 128 129 WE0/DQM0 PTE5/VCI_HWC IN IN Control OUT Control 130 OUT AUDSYNC IN 131 132 PTB2/CKE IN Control Control 133 Rev. 1.00, 02/04, page 688 of 804 Bit Pin Name I/O OUT IN Bit 168 169 Pin Name A14 A13 I/O Control OUT Control 134 PTB2/CKE 135 PTB3/CAS 136 137 138 PTB4/RAS 139 140 141 PTB5/RD/WR 142 143 144 PTD5/A23 145 146 147 PTD4/A22 148 149 150 PTD3/A21 151 152 153 PTD2/A20 154 155 156 PTD1/A19 157 158 159 A18 160 161 A17 162 163 A16 164 165 A15 166 167 A14 Control 170 OUT IN 171 172 A11 A12 OUT Control OUT Control Control 173 OUT IN 174 175 A10 OUT Control Control 176 OUT IN 177 178 A8 A9 OUT Control OUT Control Control 179 OUT IN 180 181 A7 OUT Control Control 182 OUT IN 183 184 A5 A6 OUT Control OUT Control Control 185 OUT IN 186 187 A4 OUT Control Control 188 OUT IN 189 190 A2 A3 OUT Control OUT Control Control 191 OUT 192 Control 193 OUT 194 A1 OUT Control Control 195 OUT OUT 196 197 PTD0/A0 IN Control OUT Control 198 OUT 199 D15 IN Control OUT Control 200 OUT 201 D14 IN Rev. 1.00, 02/04, page 689 of 804 Bit Pin Name I/O Bit Pin Name D5 I/O Control OUT 202 D14 203 204 D13 205 206 207 D12 208 209 210 D11 211 212 213 D10 214 215 216 D9 217 218 219 D8 220 221 222 D7 223 224 225 D6 226 227 228 D5 Control 229 OUT IN 230 231 D4 IN Control OUT Control 232 OUT IN 233 234 D3 IN Control OUT Control 235 OUT IN 236 237 D2 IN Control OUT Control 238 OUT IN 239 240 D1 IN Control OUT Control 241 OUT IN 242 243 D0 IN Control OUT Control 244 OUT IN 245 246 CS4 IN Control OUT Control 247 OUT IN 248 249 CS3 IN Control OUT Control 250 OUT IN 251 252 CS0 IN Control OUT Control 253 OUT IN 254 255 BOOT_E IN Rev. 1.00, 02/04, page 690 of 804 26.3.4 ID Register (SDID) SDID is a 32-bit register that consists of the version, parts number, manufacturer, and fixed code. SDID can be read from the CPU even in normal mode as two 16-bit registers, SDIDH and SDIDL. However, SDID cannot be written to. SDID cannot be accessed from the H-UDI pin. Bit Bit Name Initial Value R/W Description Device ID31 to ID0 Device ID register that is stipulated by JTAG. H0028200F (initial value) for this LSI. The upper four bits may be changed by the chip version. SDIDH corresponds to bits 31 to 16. SDIDL corresponds to bits 15 to 0. 31 to 0 DID31 to DID0 Refer to R description Rev. 1.00, 02/04, page 691 of 804 26.4 26.4.1 Operation TAP Controller Figure 26.2 shows the internal states of the TAP controller. State transitions basically conform to the JTAG standard. 1 Test-logic-reset 0 1 Select-DR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 Capture-IR 0 Shift-IR 1 0 1 1 1 0 Run-test/idle Select-IR-scan 0 0 Figure 26.2 TAP Controller State Transitions Rev. 1.00, 02/04, page 692 of 804 26.4.2 Reset Configuration Table 26.4 lists the reset configuration of this LSI. Table 26.4 Reset Configuration ASEMD0*1 H RESETP L TRST L H H L H L L L H H L H Chip State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation Reset hold*2 Normal reset H-UDI reset only Normal operation Notes: 1. Performs normal mode or ASE mode settings ASEMD0 = H, normal mode ASEMD0 = L, ASE mode 2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a constant cycle. In this state, the CPU does not start up, even if RESETP is driven high. When TRST is driven high, H-UDI operation is enabled, but the CPU does not start up. The reset hold state is cancelled by the following: * Another RESETP assert (power-on reset) * TRST reassert 26.4.3 TDO Output Timing The timing for switching data output from the TDO in normal mode changes at the TCK falling edge. This is a timing defined by the JTAG standard. This timing for switching data output from the TDO varies if the emulator function is used in ASE mode. For details on the timing, refer to the emulator's user's manual. TCK TDO (when the boundary scan command is set) tTDO Figure 26.3 H-UDI Data Transfer Timing Rev. 1.00, 02/04, page 693 of 804 26.5 Boundary Scan When ASEMD0 is driven high, the H-UDI pins are function as pins for the JTAG. All boundary scan cells on this LSI are connected as a single shift register with an input from the TDI pin and an output from the TDO pin to form the boundary scan register (SDBSR). The TDO and TDI pins of all LSIs that support the boundary scan function on the board are connected as a single shift register to form the boundary scan register. This allows wiring between the LSIs on the board and the mounted conditions of LSIs to be tested. 26.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and an optional instruction (IDCODE). 1. BYPASS The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other LSIs on the printed circuit board. This LSI's system circuits are not affected by execution of this instruction. The instruction code is B'111. 2. SAMPLE/PRELOAD The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The instruction code is B'001. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rising of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). Rev. 1.00, 02/04, page 694 of 804 3. EXTEST This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is B'000. 4. IDCODE The H-UDI pins can be entered in IDCODE mode which is defined by the JTAG by setting the command to SDIR from the H-UDI pins. When the H-UDI is initialized (when the TRST pin is asserted or the TAP controller is transited to the Test-Logic-Reset state), IDCODE mode is entered. The instruction code is B'100. 26.5.2 Cautions 1. Boundary scan mode does not cover clock-related signals: EXTAL2, XTAL2, EXTAL, XTAL. 2. Boundary scan mode does not cover the reset-related signal: RESETP. 3. Boundary scan mode does not cover H-UDI-related signals: TCK, TDI, TDO, TMS, TRST, ASEMD0. 4. Boundary scan mode does not cover some Bluetooth (BT) related signals: RDI_TXTRDATA, RDI_RXBDW_OUT, RDI_REFCLK_IN, RDI_CTRL3, RDI_CTRL4, RFSEL, RCI_SPI_TXRX, RCI_SPI_CLK, RCI_SPI_ENB, RREF. 5. Boundary scan mode does not cover the test-related signal: TEST_REG, TEST. 6. Boundary scan mode does not cover analog signals: USB_P, USB_N, DA0, DA1. 7. When the EXTEST command is set, fix the RESETP pin low. 8. While boundary scan is being executed, fix the ASEMD0 pin high. Rev. 1.00, 02/04, page 695 of 804 26.6 Usage Notes 1. An H-UDI command, once set, will not be modified as long as another command is not reissued from the H-UDI. If the same command is given continuously, the command must be set after a command (BYPASS, etc.) that does not affect chip operations is once set. 2. Because chip operations are suspended in standby mode, H-UDI commands are not accepted. To maintain the TAP controller state before and after standby mode, TCK must be kept high during the transition to standby mode. 3. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator. 4. Usage of the TRST pin as a boundary scan function is optional. In this LSI, the TAP controller must be initialized simultaneously by the TRST pin at a power-on reset. Note however that in other LSIs, a power-on reset function may be available instead of the TRST pin or initialization of the TAP controller at a power-on reset may not be required. Take the following points in consideration when applying a power-on reset signal to the TRST pin. A reset signal must always be applied when the power is turned on. The power-on reset circuit must be separated from the LSI so that the TRST signal of the board tester does not affect the LSI operation. Resetting the TAP controller during board testing may generate a TRST signal asynchronously. If the power-on reset circuit is not separated in this case, the generated TRST signal will likely affect LSI operation during board testing (e.g. system reset occurs asynchronously). Due to the opposite reason as described above, the power-on reset circuit must be separated from the LSI so that the LSI's system reset does not affect the TRST signal of the board tester. During board testing, the board tester controls the system reset signal via the boundary scans to examine the connection of the LSI system reset signal. If the power-on reset circuit is not separated in this case, the above operation resets the TAP controller, and testing may not be performed correctly. Figure 26.4 shows an example of circuit connection. LSI System_Reset Power-on reset circuit TRST RESETP ASEMD0 TRST Vcc Figure 26.4 Example of Connecting Reset Signals without Mutual Interference Rev. 1.00, 02/04, page 696 of 804 Section 27 List of Registers The address map gives information on the on-chip I/O registers and is configured as described below. Register Addresses (by functional module, in order of the corresponding section numbers) Descriptions by functional module, in order of the corresponding section numbers Access to reserved addresses which are not described in this list is disabled. When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the presumption of a big-endian system. 2. Register Bits Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). Reserved bits are indicated by in the bit name. No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. When registers consist of 16 or 32 bits, bits are described from the MSB side. The order in which bytes are described is on the presumption of a big-endian system 3. Register States in Each Operating Mode Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). For the initial state of each bit, refer to the description of the register in the corresponding section. The register states described are for the basic operating modes. If there is a specific reset for an on-chip module, refer to the section on that on-chip module. 1. Rev. 1.00, 02/04, page 697 of 804 27.1 Register Addresses (by functional module, in order of the corresponding section numbers) Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. Register Name Interrupt event register 2 TRAPA exception register Exception event register Exception address register Cache control register 1 Cache control register 2 Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 4 Interrupt mask register 5 Interrupt mask register 6 Interrupt mask register 9 Interrupt mask clear register 0 Interrupt mask clear register 1 Interrupt mask clear register 4 Interrupt mask clear register 5 Interrupt mask clear register 6 Interrupt mask clear register 9 Number Abbreviation of Bits Address INTEVT2 TRA EXPEVT TEA CCR1 CCR2 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IMR0 IMR1 IMR4 IMR5 IMR6 IMR9 IMCR0 IMCR1 IMCR4 IMCR5 IMCR6 IMCR9 32 32 32 32 32 32 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 H'A400 0000 H'FFFF FFD0 H'FFFF FFD4 H'FFFF FFFC H'FFFF FFEC H'A400 00B0 H'A414 FEE2 H'A414 FEE4 H'A414 0016 H'A414 0018 H'A414 001A H'A408 0000 H'A408 0002 H'A408 0004 H'A408 0040 H'A408 0042 H'A408 0048 H'A408 004A H'A408 004C H'A408 0052 H'A408 0060 H'A408 0062 H'A408 0068 H'A408 006A H'A408 006C H'A408 0072 Module Exception handling Access Size 32 32 32 32 Cache 32 32 INTC 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00, 02/04, page 698 of 804 Register Name Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt request register 0 Common control register Bus control register for CS0 space Bus control register for CS3 space Bus control register for CS4 space Wait control register for CS0 space Wait control register for CS3 space Wait control register for CS4 space SDRAM control register Refresh timer control/status register Refresh timer counter Refresh timer timer constant register Reset wait counter Number Abbreviation of Bits Address ICR0 ICR1 ICR2 IRR0 CMNCR CS0BCR CS3BCR CS4BCR CS0WCR CS3WCR CS4WCR SDCR RTCSR RTCNT RTCOR RWTCNT 16 16 16 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'A414 FEE0 H'A414 0010 H'A414 0012 H'A414 0004 H'A4FD 0000 H'A4FD 0004 H'A4FD 000C H'A4FD 0010 H'A4FD 0024 H'A4FD 002C H'A4FD 0030 H'A4FD 0044 H'A4FD 0048 H'A4FD 004C H'A4FD 0050 H'A4FD 0054 H'A4FD 5xxx* H'A401 0020 H'A401 0024 H'A401 0028 H'A401 002C H'A401 0000 H'A401 0030 H'A401 0034 H'A401 0038 H'A401 003C H'A401 0004 H'A401 0040 H'A401 0044 H'A401 0048 H'A401 004C H'A401 0008 H'A401 0050 1 Module INTC Access Size 16 16 16 8 BSC 32 32 32 32 32 32 32 32 32 32 32 32 16 SDRAM mode register for CS3 space SDMR3 DMA source address register_0 DMA destination address register_0 DMA transfer count register_0 DMA channel control register_0 DMA initial address register_0 DMA source address register_1 DMA destination address register_1 DMA transfer count register_1 DMA channel control register_1 DMA initial address register_1 DMA source address register_2 DMA destination address register_2 DMA transfer count register_2 DMA channel control register_2 DMA initial address register_2 DMA source address register_3 SAR_0 DAR_0 DMATCR_0 CHCR_0 IAR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 IAR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 IAR_2 SAR_3 DMAC 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 16/32 16/32 8/16/32 16/32 16/32 Rev. 1.00, 02/04, page 699 of 804 Register Name DMA destination address register_3 DMA transfer count register_3 DMA channel control register_3 DMA initial address register_3 DMA operation register DMA extended resource selector 0 DMA extended resource selector 1 Frequency control register* Watchdog timer counter 3 Number Abbreviation of Bits Address DAR_3 DMATCR_3 CHCR_3 IAR_3 DMAOR DMARS0 DMARS1 FRQCR WTCNT 32 32 32 32 32 16 16 16 8 8 8 8 8 8 8 8 32 32 16 32 32 16 32 32 16 16 16 16 16 16 16 16 16 H'A401 0054 H'A401 0058 H'A401 005C H'A401 000C H'A401 0060 H'A409 0000 H'A409 0004 H'A415 FF80 H'A415 FF84 H'A415 FF86 H'A415 FF82 H'A415 FF88 H'A40A 0000 H'A40A 0004 H'A40A0010 H'A412 FE92 H'A412 FE94 H'A412 FE98 H'A412 FE9C H'A412 FEA0 H'A412 FEA4 H'A412 FEA8 H'A412 FEAC H'A412 FEB0 H'A412 FEB4 H'A442 0000 H'A442 0002 H'A442 0004 H'A442 0006 H'A442 0008 H'A442 000C H'A442 0010 H'A442 0014 Module DMAC Access Size 16/32 16/32 8/16/32 16/32 8/16/32 16 16 CPG WDT 16 8/16* 8/16* 2 Watchdog timer control/status register WTCSR Standby control register* 3 2 STBCR STBCR2 STBCR3 STBCR4 MCCR TSTR TCOR_0 TCNT_0 TCR_0 TCOR_1 TCNT_1 TCR_1 TCOR_2 TCNT_2 TCR_2 SIMDR SISCR SITDAR SIRDAR SICDAR SICTR SIFCTR SISTR Power-down 8 modes 8 8 8 8 TMU 8 32 32 16 32 32 16 32 32 16 SIOF 16 16 16 16 16 16 16 16 Standby control register 2 Standby control register 3 Standby control register 4 Memory clock control register Timer start register Timer constant register_0 Timer counter_0 Timer control register_0 Timer constant register_1 Timer counter_1 Timer control register_1 Timer constant register_2 Timer counter_2 Timer control register_2 Mode register Clock select register Transmit data assign register Receive data assign register Control data assign register Control register FIFO control register Status register Rev. 1.00, 02/04, page 700 of 804 Register Name Interrupt enable register Transmit data register Receive data register Transmit control data register Receive control data register SPI control register Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data stop register_0 FIFO error count register_0 Serial status register_0 FIFO control register_0 FIFO data count register_0 Transmit FIFO data register_0 Receive FIFO data register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data stop register_1 FIFO error count register_1 Serial status register_1 FIFO control register_1 FIFO data count register_1 Transmit FIFO data register_1 Receive FIFO data register_1 EXCPG control register HcRevision register HcContorol register HcCommandStatus register HcInterruptStatus register HcInterruptEnable register HcInterruptDisable register Number Abbreviation of Bits Address SIIER SITDR SIRDR SITCR SIRCR SPICR SCSMR_0 SCBRR_0 SCSCR_0 SCTDSR_0 SCFER_0 SCSSR_0 SCFCR_0 SCFDR_0 SCFTDR_0 SCFRDR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCTDSR_1 SCFER_1 SCSSR_1 SCFCR_1 SCFDR_1 SCFTDR_1 SCFRDR_1 EXCPGCR HREVR HCTLR HCSR HISR HIER HIDR 16 32 32 32 32 16 16 8 16 8 16 16 16 16 8 8 16 8 16 8 16 16 16 16 8 8 8 32 32 32 32 32 32 H'A442 0016 H'A442 0020 H'A442 0024 H'A442 0028 H'A442 002C H'A4420030 H'A443 0000 H'A443 0004 H'A443 0008 H'A443 000C H'A443 0010 H'A443 0014 H'A443 0018 H'A443 001C H'A443 0020 H'A443 0024 H'A445 0000 H'A445 0004 H'A445 0008 H'A445 000C H'A445 0010 H'A445 0014 H'A445 0018 H'A445 001C H'A445 0020 H'A445 0024 H'A447 0000 H'A449 0000 H'A449 0004 H'A449 0008 H'A449 000C H'A449 0010 H'A449 0014 Module SIOF Access Size 16 32 32 32 32 16 SCIF_0 (Channel 0) 16 8 16 8 16 16 16 16 8 8 SCIF_1 (Channel 1) 16 8 16 8 16 16 16 16 8 8 USBPM USBH 8 32 32 32 32 32 32 Rev. 1.00, 02/04, page 701 of 804 Register Name HcHCCA register HcPeriodCurrentED register HcControlHeadED register HcControlCurrentED register HcBulkHeadED register HcBulkCurrentED register HcDoneHeadED register HcFmInterval register HcFmRemaining register HcFmNumber register HcPeriodicStart register HcLSThreshold register HcRhDescriptor A register HcRhDescriptor B register HcRhStatus register HcRhPortStatus1 register Interrupt flag register 0 Interrupt select register 0 Interrupt enable register 0 EP0i data register EP0o data register EP0s data register EP1 data register EP2i data register EP2o data register EP3i data register EP3o data register EP4 data register EP5 data register EP6 data register EP0o receive data size register EP2o receive data size register EP3o receive data size register Number Abbreviation of Bits Address HHCCAR HPCEDR HCHEDR HCCEDR HBHEDR HBCEDR HDHEDR HFIR HFRR HFNR HPSR HLSTR HRDRA HRDRB HRSR HRPSR IFR0 ISR0 IER0 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2i EPDR2o EPDR3i EPDR3o EPDR4 EPDR5 EPDR6 EPSZ0o EPSZ2o EPSZ3o 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 64B* 64B* 8B* 4 4 Module USBH Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'A449 0018 H'A449 001C H'A449 0020 H'A449 0024 H'A449 0028 H'A449 002C H'A449 0030 H'A449 0034 H'A449 0038 H'A449 003C H'A449 0040 H'A449 0044 H'A449 0048 H'A449 004C H'A449 0050 H'A449 0054 H'A448 0000 H'A448 0010 H'A448 0020 H'A448 0030 H'A448 0034 H'A448 0038 4 USBF 32 32 32 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 16B* H'A448 003C 4 128B* 128B* 128B* 120B* 16B* 64B* 64B* 8 8 8 4 H'A448 0040 H'A448 0044 H'A448 004C H'A448 0050 H'A448 0054 H'A448 0058 H'A448 005C H'A448 0080 H'A448 0084 H'A448 0088 4 4 4 4 4 Rev. 1.00, 02/04, page 702 of 804 Register Name EP6 receive data size register Trigger register Data status register FIFO clear register DMA transfer setting register Endpoint stall register Configuration value register Time stamp register Control register Endpoint information register D/A data register0 D/A data register1 D/A control register Port A data register Port B data register Port D data register Port E data register Port G data register Port H data register Port A control register Port B control register Port D control register Port E control register Port G control register Port H control register Pin select register A I/O buffer Hi-Z control register A Noise Canceller control register Break data register B Break data mask register B Break control register Execution count break register Break address register B Number Abbreviation of Bits Address EPSZ6 TRG DASTS FCLR DMA EPSTL CVR TSR CTLR EPIR DADR_0 DADR_1 DACR PADR PBDR PDDR PEDR PGDR PHDR PACR PBCR PDCR PECR PGCR PHCR PSELA HIZCRA NCCR BDRB BDMRB BRCR BETR BARB 8 16 8 16 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 32 32 32 16 32 H'A448 008C H'A448 00A0 H'A448 00A4 H'A448 00A8 H'A448 00AC H'A448 00B0 H'A448 00B4 H'A448 00B8 H'A448 00BC H'A448 00C0 H'A440 0000 H'A440 0001 H'A440 0002 H'A405 0120 H'A405 0122 H'A405 0126 H'A405 0128 H'A405 012C H'A405 012E H'A405 0100 H'A405 0102 H'A405 0106 H'A405 0108 H'A405 010C H'A405 010E H'A405 0140 H'A405 0146 H'A405 014C H'FFFF FF90 H'FFFF FF94 H'FFFF FF98 H'FFFF FF9C H'FFFF FFA0 Module USBF Access Size 8 16 8 16 8 32* 8 16 8 8 5 DAC 8 8 8 I/O port 8 8 8 8 8 8 PFC 16 16 16 16 16 16 16 16 16 UBC 32 32 32 16 32 Rev. 1.00, 02/04, page 703 of 804 Register Name Break address mask register B Break bus cycle register B Branch source register Break address register A Break address mask register A Break bus cycle register A Branch destination register Instruction register* ID register ID register 6 Number Abbreviation of Bits Address BAMRB BBRB BRSR BARA BAMRA BBRA BRDR SDIR SDID/SDIDH SDID/SDIDL 32 16 32 32 32 16 32 16 16 16 H'FFFF FFA4 H'FFFF FFA8 H'FFFF FFAC H'FFFF FFB0 H'FFFF FFB4 H'FFFF FFB8 H'FFFF FFBC H'A410 0200 H'A410 0214 H'A410 0216 Module UBC Access Size 32 16 32 32 32 16 32 H-UDI 16 16 16 Notes: 1. Controls accessing of the SDRAM mode register. XXX depends on the setting value. 2. 8 bits when reading and 16 bits when writing. 3. If the SLEEP instruction is issued immediately after data is written to, the register value may not be reflected correctly. Before executing the SLEEP instruction, read the register. 4. The number of bits of each endpoint data register in USBF indicates the max value of FIFO buffer. 5. The endpoint stall register (EPSTL) must be accessed in 32 bits and the lower 2 bytes become valid. 6. 3-bit register when accessing from H-UDI interface. Rev. 1.00, 02/04, page 704 of 804 27.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Bit 31/ Abbreviation 23/15/7 INTEVT2 Bit 30/ 22/14/6 INTEVT2 TRA EXPEVT TEA TEA TEA TEA IPR14 IPR6 Bit 29/ 21/13/5 INTEVT2 TRA EXPEVT TEA TEA TEA TEA IPR13 IPR5 Bit 28/ 20/12/4 INTEVT2 TRA EXPEVT TEA TEA TEA TEA IPR12 IPR4 Bit 27/ 19/11/3 INTEVT2 INTEVT2 TRA EXPEVT EXPEVT TEA TEA TEA TEA CF IPR11 Bit 26/ 18/10/2 INTEVT2 INTEVT2 TRA EXPEVT EXPEVT TEA TEA TEA TEA CB IPR10 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module Exception handling INTEVT2 INTEVT2 INTEVT2 INTEVT2 INTEVT2 TRA EXPEVT EXPEVT TEA TEA TEA TEA WT TRA EXPEVT EXPEVT TEA TEA TEA TEA CE Cache TRA TRA EXPEVT EXPEVT TEA TEA TEA TEA TEA CCR1 CCR2 W3LOAD W3LOCK W2LOAD W2LOCK IPR9 IPR8 INTC IPRA IPR15 IPR7 Rev. 1.00, 02/04, page 705 of 804 Register Bit 31/ Abbreviation 23/15/7 IPRB IPR15 IPRC IPR15 IPR7 IPRD IPR15 IPRE IPR15 IPRF IPR7 IPRG IPR15 IPRH IMR0 IMR1 IMR4 IMR5 IMR6 IMR9 IMCR0 IMCR1 IMCR4 IMCR5 IMCR6 IMCR9 ICR0 IM7 IMC7 NMIL ICR1 IRQ31S ICR2 IRR0 IRQ7R Bit 30/ 22/14/6 IPR14 IPR14 IPR6 IPR14 IPR14 IPR6 IPR14 IM6 IMC6 IRQE IRQ30S Bit 29/ 21/13/5 IPR13 IPR13 IPR5 IPR13 IPR13 IPR5 IPR13 IM5 IMC5 IRQ21S Bit 28/ 20/12/4 IPR12 IPR12 IPR4 IPR12 IPR12 IPR4 IPR12 IM4 IM4 IMC4 IMC4 IRQ20S IRQ4R Bit 27/ 19/11/3 IPR11 IPR3 IPR3 IPR3 IPR11 IPR11 IM3 IM3 IM3 IMC3 IMC3 IMC3 IRQ11S IRQ71S IRQ3R Bit 26/ 18/10/2 IPR10 IPR2 IPR2 IPR2 IPR10 IPR10 IM2 IM2 IM2 IMC2 IMC2 IMC2 IRQ10S IRQ70S IRQ2R Bit 25/ 17/9/1 IPR9 IPR1 IPR1 IPR1 IPR9 IPR9 IM1 IM1 IM1 IM1 IM1 IMC1 IMC1 IMC1 IMC1 IMC1 IRQ41S IRQ01S IRQ1R Bit 24/ 16/8/0 IPR8 IPR0 IPR0 IPR0 IPR8 IPR8 IM0 IM0 IM0 IM0 IMC0 IMC0 IMC0 IMC0 NMIE IRQ40S IRQ00S IRQ0R Module INTC Rev. 1.00, 02/04, page 706 of 804 Register Bit 31/ Abbreviation 23/15/7 CMNCR DMAIW1 CS0BCR IWRWS1 CS3BCR IWRWS1 CS4BCR IWRWS1 CS0WCR (Other than burst ROM) WR0 CS0WCR (Burst ROM) W0 CS3WCR (Other than SDRAM) WR0 CS3WCR (SDRAM) A3CL0 Bit 30/ 22/14/6 DMAIW0 IWRWS0 TYPE2 IWRWS0 TYPE2 IWRWS0 TYPE2 WM WM WM TRP1 Bit 29/ 21/13/5 DMAIWA IWW1 TYPE1 IWW1 TYPE1 IWW1 TYPE1 TRP0 Bit 28/ 20/12/4 IWW0 IWRRD1 TYPE0 IWW0 IWRRD1 TYPE0 IWW0 IWRRD1 TYPE0 SW1 BAS TRWL1 Bit 27/ 19/11/3 ENDIAN IWRRD0 IWRRD0 IWRRD0 SW0 TRCD1 TRWL0 Bit 26/ 18/10/2 IWRWD1 BSZ1 IWRWD1 BSZ1 IWRWD1 BSZ1 WR3 W3 WR3 TRCD0 Bit 25/ 17/9/1 HIZMEM Bit 24/ 16/8/0 HIZCNT Module BSC IWRWD0 IWRRS1 BSZ0 IWRRS0 IWRWD0 IWRRS1 BSZ0 IWRRS0 IWRWD0 IWRRS1 BSZ0 WR2 HW1 BW1 W2 WR2 BW1 TRC1 IWRRS0 WR1 HW0 BW0 W1 WR1 BW0 A3CL1 TRC0 Rev. 1.00, 02/04, page 707 of 804 Register Bit 31/ Abbreviation 23/15/7 CS4WCR (Other than burst ROM) WR0 CS4WCR (Burst ROM) W0 SDCR RTCSR CMF RTCNT Bit 30/ 22/14/6 WM WM Bit 29/ 21/13/5 CKS2 Bit 28/ 20/12/4 BAS SW1 SW1 SLOW A3ROW1 CKS1 Bit 27/ 19/11/3 SW0 SW0 RFSH A3ROW0 CKS0 Bit 26/ 18/10/2 WW2 WR3 W3 RMODE RRC2 Bit 25/ 17/9/1 WW1 WR2 HW1 BW1 W2 HW1 PDOWN A3COL1 RRC1 Bit 24/ 16/8/0 WW0 WR1 HW0 BW0 W1 HW0 BACTV A3COL0 RRC0 Module BSC RTCOR RWTCNT SDMR3 Rev. 1.00, 02/04, page 708 of 804 Register Bit 31/ Abbreviation 23/15/7 SAR0 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module DMAC DAR0 DMATCR0 CHCR0 DO DM1 DL TL DM0 DS SM1 TB SM0 TS1 RS3 TS0 RPT RS2 IE RAS AM RS1 TE DA AL RS0 DE IAR_0 SAR_1 DAR_1 DMATCR_1 Rev. 1.00, 02/04, page 709 of 804 Register Bit 31/ Abbreviation 23/15/7 CHCR_1 DO DM1 DL IAR_1 Bit 30/ 22/14/6 TL DM0 DS Bit 29/ 21/13/5 SM1 TB Bit 28/ 20/12/4 SM0 TS1 Bit 27/ 19/11/3 RS3 TS0 Bit 26/ 18/10/2 RPT RS2 IE Bit 25/ 17/9/1 RAS AM RS1 TE Bit 24/ 16/8/0 DA AL RS0 DE Module DMAC SAR_2 DAR_2 DMATCR_2 CHCR_2 DO DM1 DL TL DM0 DS SM1 TB SM0 TS1 RS3 TS0 RPT RS2 IE RAS AM RS1 TE DA AL RS0 DE IAR_2 SAR_3 Rev. 1.00, 02/04, page 710 of 804 Register Bit 31/ Abbreviation 23/15/7 DAR_3 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module DMAC DMATCR_3 CHCR_3 DO DM1 DL TL DM0 DS SM1 TB SM0 TS1 RS3 TS0 RPT RS2 IE RAS AM RS1 TE DA AL RS0 DE IAR_3 DMAOR C1MID4 C0MID4 C3MID4 C2MID4 IFC2 CMS1 C1MID3 C0MID3 C3MID3 C2MID3 IFC1 CMS0 C1MID2 C0MID2 C3MID2 C2MID2 CKOEN IFC0 C1MID1 C0MID1 C3MID1 C2MID1 AE C1MID0 C0MID0 C3MID0 C2MID0 STC2 PFC2 PR1 NMIF C1RID1 C0RID1 C3RID1 C2RID1 STC1 PFC1 PR0 DME C1RID0 C0RID0 C3RID0 C2RID0 STC0 PFC0 WDT CPG DMARS0 C1MID5 C0MID5 DMARS1 C3MID5 C2MID5 FRQCR WTCNT WTCSR STBCR STBCR2 STBCR3 STBCR4 MCCR TME STBY MSTP10 MSTP37 WT/IT MSTP9 MSTP46 RSTS MSTP8 WOVF STBXTL MSTP7 IOVF MSTP43 CKS2 MSTP2 MSTP5 MSTP42 UMCLKC CKS1 MSTP4 MSTP41 CKS0 MSTP3 MSTP40 Powerdown mode XYMCLKC Rev. 1.00, 02/04, page 711 of 804 Register Bit 31/ Abbreviation 23/15/7 TSTR TCOR_0 Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 STR2 Bit 25/ 17/9/1 STR1 Bit 24/ 16/8/0 STR0 Module TMU TCNT_0 TCR_0 UNIE TPSC1 UNF TPSC0 TCOR_1 TCNT_1 TCR_1 UNIE TPSC1 UNF TPSC0 TCOR_2 TCNT_2 TCR_2 UNIE TPSC1 UNF TPSC0 Rev. 1.00, 02/04, page 712 of 804 Register Bit 31/ Abbreviation 23/15/7 SIMDR TRMD1 TXDIZ SISCR MSSEL SITDAR TDLE TDRE SIRDAR RDLE RDRE SICDAR CD0E CD1E SICTR SCKE SIFCTR TFWM2 RFWM2 SISTR SIIER TDMAE SITDR SITDL15 SITDL7 SITDR15 SITDR7 SIRDR SIRDL15 SIRDL7 SIRDR15 SIRDR7 SITCR SITC015 SITC07 SITC115 SITC17 Bit 30/ 22/14/6 TRMD0 RCIM MSIMM TLREP FSE TFWM1 RFWM1 TCRDY TCRDYE SITDL14 SITDL6 SITDR14 SITDR6 SIRDL14 SIRDL6 SIRDR14 SIRDR6 SITC014 SITC06 SITC114 SITC16 Bit 29/ 21/13/5 SYNCAT SYNCAC TFWM0 RFWM0 TFEMP SAERR TFEMPE SAERRE SITDL13 SITDL5 SITDR13 SITDR5 SIRDL13 SIRDL5 Bit 28/ 20/12/4 REDG SYNCDL BRPS4 TFUA4 RFUA4 TDREQ FSERR TDREQE FSERRE SITDL12 SITDL4 SITDR12 SITDR4 SIRDL12 SIRDL4 Bit 27/ 19/11/3 FL3 BRPS3 TDLA3 TDRA3 RDLA3 RDRA3 CD0A3 CD1A3 TFUA3 RFUA3 TFOVF RDMAE TFOVFE SITDL11 SITDL3 SITDR11 SITDR3 SIRDL11 SIRDL3 SIRDR11 SIRDR3 SITC011 SITC03 SITC111 SITC13 Bit 26/ 18/10/2 FL2 BRPS2 BRDV2 TDLA2 TDRA2 RDLA2 RDRA2 CD0A2 CD1A2 TFUA2 RFUA2 RCRDY TFUDF RCRDYE TFUDFE SITDL10 SITDL2 SITDR10 SITDR2 SIRDL10 SIRDL2 SIRDR10 SIRDR2 SITC010 SITC02 SITC110 SITC12 Bit 25/ 17/9/1 FL1 BRPS1 BRDV1 TDLA1 TDRA1 RDLA1 RDRA1 CD0A1 CD1A1 TXE TXRST TFUA1 RFUA1 RFFUL RFUDF RFFULE RFUDFE SITDL9 SITDL1 SITDR9 SITDR1 SIRDL9 SIRDL1 SIRDR9 SIRDR1 SITC09 SITC01 SITC19 SITC11 Bit 24/ 16/8/0 FL0 BRPS0 BRDV0 TDLA0 TDRA0 RDLA0 RDRA0 CD0A0 CD1A0 RXE RXRST TFUA0 RFUA0 RDREQ RFOVF RDREQE RFOVFE SITDL8 SITDL0 SITDR8 SITDR0 SIRDL8 SIRDL0 SIRDR8 SIRDR0 SITC08 SITC00 SITC18 SITC10 Module SIOF SIRDR13 SIRDR12 SIRDR5 SITC013 SITC05 SITC113 SITC15 SIRDR4 SITC012 SITC04 SITC112 SITC14 Rev. 1.00, 02/04, page 713 of 804 Register Bit 31/ Abbreviation 23/15/7 SIRCR SIRC015 SIRC07 SIRC115 SIRC17 SPICR SPIM SCSMR_0 C/A SCBRR_0 SCSCR_0 SCBRD7 TDRQE TIE SCTDSR_0 SCFER_0 SCSSR_0 ER SCFCR_0 TSE RTRG1 SCFDR_0 SCFTDR_0 SCFRDR_0 SCSMR_1 SCFTD7 SCFRD7 C/A SCBRR_1 SCSCR_1 SCBRD7 TDRQE TIE SCTDSR_1 SCFER_1 SCSSR_1 ER Bit 30/ 22/14/6 SIRC014 SIRC06 SIRC114 SIRC16 CHR SCBRD6 RDRQE RIE Bit 29/ 21/13/5 SIRC013 SIRC05 SIRC113 SIRC15 CPHA SSAST1 PE SCBRD5 TE Bit 28/ 20/12/4 SIRC012 SIRC04 SIRC112 SIRC14 CPOL SSAST0 O/E SCBRD4 RE Bit 27/ 19/11/3 SIRC011 SIRC03 SIRC111 SIRC13 STOP SCBRD3 TSIE Bit 26/ 18/10/2 SIRC010 SIRC02 SIRC110 SIRC12 SS2E SRC2 SCBRD2 ERIE Bit 25/ 17/9/1 SIRC09 SIRC01 SIRC19 SIRC11 SS1E FLD1 SRC1 CKS1 SCBRD1 BRIE CKE1 Bit 24/ 16/8/0 SIRC08 SIRC00 SIRC18 SIRC10 SS0E FLD0 SRC0 CKS0 SCBRD0 DRIE CKE0 Module SIOF SCIF_0 TEND TCRST RTRG0 T6 R6 SCFTD6 SCFRD6 CHR SCBRD6 RDRQE RIE PER5 FER5 TDFE TTRG1 T5 R5 SCFTD5 SCFRD5 PE SCBRD5 TE PER4 FER4 BRK TTRG0 T4 R4 SCFTD4 SCFRD4 O/E SCBRD4 RE PER3 FER3 FER MCE T3 R3 SCFTD3 SCFRD3 STOP SCBRD3 TSIE PER2 FER2 PER RSTRG2 TFRST T2 R2 SCFTD2 SCFRD2 SRC2 SCBRD2 ERIE PER1 FER1 ORER RDF RSTRG1 RFRST T1 R1 SCFTD1 SCFRD1 SRC1 CKS1 SCBRD1 BRIE CKE1 PER0 FER0 TSF DR RSTRG0 LOOP T0 R0 SCFTD0 SCFRD0 SRC0 CKS0 SCBRD0 DRIE CKE0 SCIF_1 TEND PER5 FER5 TDFE PER4 FER4 BRK PER3 FER3 FER PER2 FER2 PER PER1 FER1 ORER RDF PER0 FER0 TSF DR Rev. 1.00, 02/04, page 714 of 804 Register Bit 31/ Bit 30/ Abbreviation 23/15/7 22/14/6 SCFCR_1 TSE RTRG1 SCFDR_1 SCFTDR_1 SCFRDR_1 EXCPGCR HREVR SCFTD7 TCRST RTRG0 T6 R6 SCFTD6 Bit 29/ Bit 28/ 21/13/5 20/12/4 TTRG1 T5 R5 TTRG0 T4 R4 Bit 27/ 19/11/3 MCE T3 R3 SCFTD3 SCFRD3 Bit 26/ 18/10/2 RSTRG2 TFRST T2 R2 SCFTD2 SCFRD2 Bit 25/ 17/9/1 RSTRG1 RFRST T1 R1 SCFTD1 SCFRD1 Bit 24/ 16/8/0 RSTRG0 LOOP T0 R0 SCFTD0 SCFRD0 Module SCIF_1 SCFTD5 SCFTD4 SCFRD5 SCFRD4 REV5 BLE FNO FNO FNO SCFRD7 SCFRD6 REV7 REV6 HCFS0 OC RHSC OC RHSC OC RHSC USBVALID USBRESET USBHSTP USBFSTP USBCLKSEL USBPM REV4 CLE UE UE UE REV3 IE OCR RD RD RD REV2 PLE BLF SF SF SF REV1 CBSR1 SOC1 CLF WDH WDH WDH REV0 IR CBSR0 SOC0 HCR SO SO SO USBH HCTLR HCFS1 HCSR HISR HIER MIE HIDR MIE Rev. 1.00, 02/04, page 715 of 804 Register Bit 31/ Abbreviation 23/15/7 HHCCAR Bit 30/ 22/14/6 Bit 29/ 21/13/5 Bit 28/ 20/12/4 Bit 27/ 19/11/3 Bit 26/ 18/10/2 Bit 25/ 17/9/1 Bit 24/ 16/8/0 Module USBH HPCEDR HCHEDR HCCEDR HBHEDR HBCEDR HDHEDR HFIR FIT FSMPS7 FI7 FSMPS14 FSMPS13 FSMPS12 FSMPS11 FSMPS6 FI6 FSMPS5 FI13 FI5 FSMPS4 FI12 FI4 FSMPS3 FI11 FI3 FSMPS8 FSMPS0 FI8 FI0 FSMPS10 FSMPS9 FSMPS2 FI10 FI2 FSMPS1 FI9 FI1 Rev. 1.00, 02/04, page 716 of 804 Register Bit 31/ Abbreviation 23/15/7 HFRR FRT FR7 HFNR FN15 FN7 HPSR PS7 HLSTR LST7 HRDRA Bit 30/ 22/14/6 FR6 FN14 FN6 PS6 LST6 Bit 29/ 21/13/5 FR13 FR5 FN13 FN5 PS13 PS5 LST5 Bit 28/ 20/12/4 FR12 FR4 FN12 FN4 PS12 PS4 LST4 Bit 27/ 19/11/3 FR11 FR3 FN11 FN3 PS11 PS3 LST11 LST3 Bit 26/ 18/10/2 FR10 FR2 FN10 FN2 PS10 PS2 LST10 LST2 Bit 25/ 17/9/1 FR9 FR1 FN9 FN1 PS9 PS1 LST9 LST1 Bit 24/ 16/8/0 FR8 FR0 FN8 FN0 PS8 PS0 LST8 LST0 Module USBH POTPGT7 POTPGT6 POTPGT5 POTPGT4 POTPGT3 NDP7 NDP6 NDP5 NOCP NDP4 PRSC PRS OCPM NDP3 OCIC POCI POTPGT2 POTPGT1 POTPGT0 DT NDP2 PSSC PSS NPS NDP1 PPCM DR OCIC OCI PESC LSDA PES PSM NDP0 LPSC LPS CSC PPS CCS HRDRB HRSR CRWE DRWE HRPSR Rev. 1.00, 02/04, page 717 of 804 Register Bit 31/ Abbreviation 23/15/7 IFR0 Bit 30/ 22/14/6 BSRT Bit 29/ 21/13/5 SETUP TS Bit 28/ 20/12/4 VBUSMN Bit 27/ 19/11/3 VBUSF Bit 26/ 18/10/2 SURSS Bit 25/ 17/9/1 SURES Bit 24/ 16/8/0 CFDN Module USBF SOF SETC SETI EP6 FULL EP5 EMPTY EP5 TR EP4 TR EP4 TS EP2o FULL ISR0 EP2i EMPTY BSRT IS EP3o TF EP2I TR EP3o TS EP1 TR EP3I TR EP1 TS EP3I TS EP0o TS EP0I TR EP0I TS SETUP TS IS VBUSF IS SURES IS CFDN IS SOF IS SETC IS SETI IS EP6 FULL IS EP5 EMPTY IS EP5TR IS EP4TR IS EP4TS IS EP3o TF IS EP3o TS IS EP3I TR IS EP3I TS IS EP2o FULL IS IER0 EP2I EP2I EP1 TR IS EP1 TS IS EP0o TS IS EP0I TR IS EP0I TS IS EMPTY IS TR IS BSRT IE SETUP TS IE VBUSF IE SURES IE CFDN IE SOF IE SETC IE SETI IE EP6 FULL IE EP5 EMPTY IE EP3I TR IE EP5 TR IE EP4 TR IE EP4 TS IE EP3o TF IE EP3o TS IE EP3I TS IE EP2o FULL IE EPDR0i EPDR0o EPDR0s EPDR1 EPDR2i EPDR2o EPDR3i EPDR3o EPDR4 EPDR5 EPDR6 EPSZ0o EPSZ2o D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 EP2I EP2I EP1 TR IE EP1 TS IE EP0o TS IE EP0i TR IE D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 EP0i TS IE D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 EMPTY IE TR IE D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 Rev. 1.00, 02/04, page 718 of 804 Register Bit 31/ Abbreviation 23/15/7 EPSZ3o EPSZ6 TRG D7 D7 DMA EP6 DMAE EPSTL CVR TSR CNFV D7 CTLR EPIR DADR_0 DADR_1 DACR PADR PBDR PDDR PEDR PGDR PHDR PACR DAOE1 PB7DT PA3MD1 PBCR PB7MD1 PB3MD1 PDCR PD3MD1 D7 Bit 30/ 22/14/6 D6 D6 EP6 RDFN EP2o RDFN Bit 29/ 21/13/5 D5 D5 EP5 PKTE EP2i PKTE EP4 DE EP5 CLR Bit 28/ 20/12/4 D4 D4 EP4 PKTE EP1 PKTE EP4 CLR Bit 27/ 19/11/3 D3 D3 Bit 26/ 18/10/2 D2 D2 Bit 25/ 17/9/1 D1 D1 Bit 24/ 16/8/0 D0 D0 Module USBF EP0s RDFN EP0o RDFN EP0i PKTE EP0i DE DASTS FCLR EP5 DE EP6 CLR EP2i DE EP2o DMAE EP2o STL INTV0 D3 RSME D3 EP1 DE EP3o CLR EP3i CLR EP2o DMAS EP6STL EP2i STL ALTV2 D10 D2 PWMD D2 EP2o CLR EP2i CLR EP1 CLR EP6 DMAS EP5 DMAE EP5 DMAS EP0o CLR EP0i CLR EP2i DMAE EP5STL EP1 STL ALTV1 D9 D1 ASCE D1 EP2i DMAS EP4STL EP0 STL ALTV0 D8 D0 SOFME D0 DAC EP3o STL EP3i STL INTV3 D6 D6 INTV2 D5 PULLPE D5 INTV1 D4 RWUPS D4 DAOE0 PA6DT PB6DT PE6DT PA3MD0 PB7MD0 PB3MD0 PD3MD0 PA5DT PB5DT PD5DT PE5DT PA6MD1 PA2MD1 PB6MD1 PB2MD1 PD2MD1 PA4DT PB4DT PD4DT PE4DT PG4DT PH4DT PA6MD0 PA2MD0 PB6MD0 PB2MD0 PD2MD0 PA3DT PB3DT PD3DT PE3DT PG3DT PH3DT PA5MD1 PA1MD1 PB5MD1 PB1MD1 PD5MD1 PD1MD1 PA2DT PB2DT PD2DT PE2DT PG2DT PH2DT PA5MD0 PA1MD0 PB5MD0 PB1MD0 PD5MD0 PD1MD0 PA1DT PB1DT PD1DT PE1DT PG1DT PH1DT PA4MD1 PA0MD1 PB4MD1 PB0MD1 PD4MD1 PD0MD1 PA0DT PB0DT PD0DT PE0DT PG0DT PH0DT PA4MD0 PA0MD0 PB4MD0 PB0MD0 PD4MD0 PD0MD0 PFC I/O port Rev. 1.00, 02/04, page 719 of 804 Register Bit 31/ Abbreviation 23/15/7 PECR PE3MD1 PGCR PG3MD1 PHCR PH3MD1 PSELA PSA7 HIZCRA HIZA7 NCCR BDRB BDB31 BDB23 BDB15 BDB7 BDMRB BDMB31 BDMB23 BDMB15 BDMB7 BRCR SCMFCA DBEB BETR BET7 BARB BAB31 BAB23 BAB15 BAB7 Bit 30/ 22/14/6 PE3MD0 PG3MD0 PH3MD0 PSA6 HIZA6 BDB30 BDB22 BDB14 BDB6 BDMB30 BDMB22 BDMB14 BDMB6 SCMFCB PCBB BET6 BAB30 BAB22 BAB14 BAB6 Bit 29/ 21/13/5 PE6MD1 PE2MD1 PG2MD1 PH2MD1 PSA5 HIZA5 BDB29 BDB21 BDB13 BDB5 BDMB29 BDMB21 BDMB13 BDMB5 SCMFDA BET5 BAB29 BAB21 BAB13 BAB5 Bit 28/ 20/12/4 PE6MD0 PE2MD0 PG2MD0 PH2MD0 PSA4 HIZA4 BDB28 BDB20 BDB12 BDB4 BDMB28 BDMB20 BDMB12 BDMB4 SCMFDB BET4 BAB28 BAB20 BAB12 BAB4 Bit 27/ 19/11/3 PE5MD1 PE1MD1 PG1MD1 PH1MD1 PSA3 HIZA3 BDB27 BDB19 BDB11 BDB3 BDMB27 BDMB19 BDMB11 BDMB3 PCTE SEQ BET11 BET3 BAB27 BAB19 BAB11 BAB3 Bit 26/ 18/10/2 PE5MD0 PE1MD0 PG1MD0 PH1MD0 PSA2 HIZA2 BDB26 BDB18 BDB10 BDB2 BDMB26 BDMB18 BDMB10 BDMB2 PCBA BET10 BET2 BAB26 BAB18 BAB10 BAB2 Bit 25/ 17/9/1 PE4MD1 PE0MD1 PG4MD1 PG0MD1 PH4MD1 PH0MD1 PSA1 HIZA1 BDB25 BDB17 BDB9 BDB1 BDMB25 BDMB17 BDMB9 BDMB1 BET9 BET1 BAB25 BAB17 BAB9 BAB1 Bit 24/ 16/8/0 PE4MD0 PE0MD0 PG4MD0 PG0MD0 PH4MD0 PH0MD0 PSA8 RTCSEL1 HIZA8 HIZA0 NCCR0 BDB24 BDB16 BDB8 BDB0 BDMB24 BDMB16 BDMB8 BDMB0 ETBE BET8 BET0 BAB24 BAB16 BAB8 BAB0 Module PFC UBC Rev. 1.00, 02/04, page 720 of 804 Register Bit 31/ Abbreviation 23/15/7 BAMRB BAMB31 BAMB23 BAMB15 BAMB7 BBRB CDB1 BRSR SVF BSA23 BSA15 BSA7 BARA BAA31 BAA23 BAA15 BAA7 BAMRA BAMA31 BAMA23 BAMA15 BAMA7 BBRA CDA1 BRDR DVF BDA23 BDA15 BDA7 SDIR* SDID/SDIDH DID31 DID23 SDID/SDIDL DID15 DID7 Bit 30/ 22/14/6 BAMB30 BAMB22 BAMB14 BAMB6 CDB0 BSA22 BSA14 BSA6 BAA30 BAA22 BAA14 BAA6 BAMA30 BAMA22 BAMA14 BAMA6 CDA0 BDA22 BDA14 BDA6 DID30 DID22 DID14 DID6 Bit 29/ 21/13/5 BAMB29 BAMB21 BAMB13 BAMB5 IDB1 BSA21 BSA13 BSA5 BAA29 BAA21 BAA13 BAA5 BAMA29 BAMA21 BAMA13 BAMA5 IDA1 BDA21 BDA13 BDA5 DID29 DID21 DID13 DID5 Bit 28/ 20/12/4 BAMB28 BAMB20 BAMB12 BAMB4 IDB0 BSA20 BSA12 BSA4 BAA28 BAA20 BAA12 BAA4 BAMA28 BAMA20 BAMA12 BAMA4 IDA0 BDA20 BDA12 BDA4 DID28 DID20 DID12 DID4 Bit 27/ 19/11/3 BAMB27 BAMB19 BAMB11 BAMB3 RWB1 BSA27 BSA19 BSA11 BSA3 BAA27 BAA19 BAA11 BAA3 BAMA27 BAMA19 BAMA11 BAMA3 RWA1 BDA27 BDA19 BDA11 BDA3 DID27 DID19 DID11 DID3 Bit 26/ 18/10/2 BAMB26 BAMB18 BAMB10 BAMB2 RWB0 BSA26 BSA18 BSA10 BSA2 BAA26 BAA18 BAA10 BAA2 BAMA26 BAMA18 BAMA10 BAMA2 RWA0 BDA26 BDA18 BDA10 BDA2 TI2 DID26 DID18 DID10 DID2 Bit 25/ 17/9/1 BAMB25 BAMB17 BAMB9 BAMB1 XYE SZB1 BSA25 BSA17 BSA9 BSA1 BAA25 BAA17 BAA9 BAA1 BAMA25 BAMA17 BAMA9 BAMA1 SZA1 BDA25 BDA17 BDA9 BDA1 TI1 DID25 DID17 DID9 DID1 Bit 24/ 16/8/0 BAMB24 BAMB16 BAMB8 BAMB0 XYS SZB0 BSA24 BSA16 BSA8 BSA0 BAA24 BAA16 BAA8 BAA0 BAMA24 BAMA16 BAMA8 BAMA0 SZA0 BDA24 BDA16 BDA8 BDA0 TI0 DID24 DID16 DID8 DID0 Module UBC H-UDI Note: * H-UDI pin can write only. Rev. 1.00, 02/04, page 721 of 804 27.3 Register States in Each Operating Mode Power-on Reset *1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Register Abbreviation INTEVT2 TRA EXPEVT TEA CCR1 CCR2 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IMR0 IMR1 IMR4 IMR5 IMR6 IMR9 IMCR0 IMCR1 IMCR4 IMCR5 IMCR6 IMCR9 ICR0 ICR1 ICR2 IRR0 Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Exception handling Cache INTC Rev. 1.00, 02/04, page 722 of 804 Register Abbreviation CMNCR CS0BCR CS3BCR CS4BCR CS0WCR CS3WCR CS4WCR SDCR RTCSR RWTCNT RTCNT RTCOR SDMR3 SAR_0 DAR_0 DMATCR_0 CHCR_0 IAR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 IAR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 IAR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 IAR_3 Power-on 1 Reset * Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Undefined Initialized Undefined Undefined Undefined Undefined Initialized Undefined Undefined Undefined Undefined Initialized Undefined Undefined Undefined Undefined Initialized Undefined Manual Reset*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Undefined Undefined Undefined Initialized Undefined Undefined Undefined Undefined Initialized Undefined Undefined Undefined Undefined Initialized Undefined Undefined Undefined Undefined Initialized Undefined Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module BSC DMAC Rev. 1.00, 02/04, page 723 of 804 Register Abbreviation DMAOR DMARS0 DMARS1 DMARS2 FRQCR WTCNT WTCSR STBCR STBCR2 STBCR3 STBCR4 MCCR TSTR TCOR_0 TCNT_0 TCR_0 TCOR_1 TCNT_1 TCR_1 TCOR_2 TCNT_2 TCR_2 SIMDR SISCR SITDAR SIRDAR SICDAR SICTR SIFCTR SISTR SIIER SITDR SIRDR Power-on 1 Reset * Initialized Initialized Initialized Initialized Initialized* Initialized* Initialized* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized 2 Manual Reset*1 Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained* Retained Initialized Retained Initialized Retained 3 Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module DMAC CPG WDT 2 2 Power-down mode TMU SIOF Rev. 1.00, 02/04, page 724 of 804 Register Abbreviation SITCR SIRCR SPICR SCSMR_0 SCBRR_0 SCSCR_0 SCTDSR_0 SCFER_0 SCSSR_0 SCFCR_0 SCFDR_0 SCFTDR_0 SCFRDR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCTDSR_1 SCFER_1 SCSSR_1 SCFCR_1 SCFDR_1 SCFTDR_1 SCFRDR_1 EXCPGCR HREVR HCTLR HCSR HISR HIER HIDR HHCCAR HPCEDR HCHEDR Power-on 1 Reset * Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module SIOF SCIF_0 SCIF_1 USBPM USBH Rev. 1.00, 02/04, page 725 of 804 Register Abbreviation HCCEDR HBHEDR HBCEDR HDHEDR HFIR HFRR HFNR HPSR HLSTR HRDRA HRDRB HRSR HRPSR IFR0 ISR0 IER0 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2i EPDR2o EPDR3i EPDR3o EPDR4 EPDR5 EPDR6 EPSZ0o EPSZ2o EPSZ3o EPSZ6 TRG DASTS Power-on 1 Reset * Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module USBH USBF Rev. 1.00, 02/04, page 726 of 804 Register Abbreviation FCLR DMA EPSTL CVR TSR CTLR EPIR All registers DADR_0 DADR_1 DACR PADR PBDR PDDR PEDR PGDR PHDR PACR PBCR PDCR PECR PGDR PHDR PSELA HIZCRA NCCR BDRB BDMRB BRCR BETR BARB BAMRB Power-on 1 Reset * Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized/ 4 Retained* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset*1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module USBF BT DAC I/O port PFC UBC Rev. 1.00, 02/04, page 727 of 804 Register Abbreviation BBRB BRSR BARA BAMRA BBRA BRDR SDIR SDID/SDIDH* SDID/SDIDL* U memory X/Y memory 5 Power-on 1 Reset * Initialized Initialized Initialized Initialized Initialized Initialized Retained Undefined Undefined Manual Reset*1 Retained Retained Retained Retained Retained Retained Retained Undefined Undefined Software standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby*1 Retained Retained Retained Retained Retained Retained Retained Retained Retained Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Module UBC H-UDI 5 U memory X/Y memory Notes: 1. For details on initial values, please refer to the various sections related to the modules. In addition, registers whose initial values are undefined are also indicated as initialized. 2. Initialized by a reset signal from the RESETP pin, and retained by a reset signal from other pin. 3. Some bits are initialized. 4. All registers in BT module are initialized only by the power-on reset input from pin. They are not initialized by the power-on reset and manual reset generated from WDT. 5. Fixed value. Rev. 1.00, 02/04, page 728 of 804 Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 shows the absolute maximum ratings. Table 28.1 Absolute Maximum Ratings Item Power supply voltage (except VCC_28) Symbol VCC(I/O) VCC(internal) VCC(PLL) VCC(DLL) VCC(SREG) VCC_28 VDD Vin Vin AVCC (DAC) AVCC (USB) VIN Topr Tstg Rating -0.3 to 4.2 Unit V Power supply voltage (VCC_28) Power supply voltage (VDD): (using external power supply) Input voltage (except VCC_28) Input voltage (VCC_28) Analog power supply voltage (DAC) Analog power supply voltage (USB) Analog input voltage (USB) Operating temperature Storage temperature -0.3 to 4.2 -0.3 to 2.1 -0.3 to VCC + 0.3 -0.3 to VCC_28 + 0.3 -0.3 to 4.2 -0.3 to 4.2 -0.3 to AVCC (USB) + 0.3 -40 to 85 -55 to 125 V V V V V V V C C Usage Notes: 1. Operating the chip in excess of the absolute maximum rating may result in permanent damage. 2. Order of turning on VCC_28 and other 3.3 V power supplies (VCC, AVCC) Though there are no strict requirements, the following points are recommended since a cutoff of either power supply will cause unstable operation. First turn on the 3.3 V power supplies except for the VCC_28 power, then turn on the VCC_28 power. This interval should be as short as possible. Rev. 1.00, 02/04, page 729 of 804 Until voltage is applied to all power supplies and a low level is input to the RESETP pin, internal circuits remain unsettled, and so pin states are also undefined. The system design must ensure that these undefined states do not cause erroneous system operation. Waveforms at power-on are shown in the figure below. The power supply voltage of VCC_28 should be within the range of the absolute maximum ratings above and also equal to the power supply voltage of the RF IC to be connected. This period should be as short as possible. 3.3 V Vcc 2.8 V Vcc_28 Turn on power while RESETP is low in advance RESETP All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence 3. Order of turning off power Though there are no strict requirements, the following points are recommended since a cutoff of either power supply will cause unstable operation. In the reverse order of powering-on, first turn off the VCC_28 power, then turn off the 3.3 V power supplies. This interval should be as short as possible. Pin states are undefined while only the VCC_28 power is off. The system design must ensure that these undefined states do not cause erroneous system operation. 4. When the built-in power supply regulator is used, each VDD pin should be connected to the capacitor to reduce noise of power supply. 5. When the built-in power supply regulator is used, each VDD pin should not be applied voltage from outside. Also, the VDD pins cannot be used to supply current to the other devices. Rev. 1.00, 02/04, page 730 of 804 28.2 DC Characteristics Tables 28.2 and 28.3 list the DC characteristics. Table 28.2 DC Characteristics (1) Common Items Condition: Ta = -40 to 85C Item Current consumption Input leak current Three-state leak current Normal operation All input pins I/O, all output pins (off condition) Port pin All digital pins* Symbol ICC Min. -- Typ. -- Max. 350 Unit mA Test Conditions VCC = 3.3 V I = 120 MHz B = 60 MHz Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Iin ISTI -- -- -- -- 1.0 1.0 A A Pull-up resistance Pin capacity Ppull C 30 -- 60 -- 3.3 3.3 1.5 120 10 3.6 3.6 1.6 k pF V V V When external power supply is used. Analog power supply voltage (DAC) Analog power supply voltage (USB) Internal power supply voltage (VDD) Note: * AVCC(DAC) 2.7 AVCC(USB) 3.0 VDD 1.4 Power supply pins, analog pins, VBB, USB_N, USB_P, RDI_CTRL4, DA0, DA1, EXTAL, XTAL, EXTAL2, XTAL2, RREF, and NC are excluded. Rev. 1.00, 02/04, page 731 of 804 Table 28.2 DC Characteristics (2-a) Except DAC and USB Related Pins Condition: Ta = -40 to 85C Item Power supply voltage Symbol VCC VCC_28 Input high NMI, MD1, MD2, voltage MD5, ASEMD0, IRQ0, IRQ2 to IRQ4 TRST EXTAL, EXTAL2 RESETP RDI_TXTRDATA, RDI_REFCLK_IN, RCI_SPI_TXRX Other input pins Input low voltage NMI, IRQ0, VIL IRQ2 to IRQ4, MD1, MD2, MD5, ASEMD0, TRST EXTAL, EXTAL2 RESETP, RDI_TXTRDATA, RDI_REFCLK_IN, RCI_SPI_TXRX Other input pins Output high voltage RDI_CTRL4 VOH VIH Min. 2.7 2.7 2.7 VCC x 0.9 Typ. 3.3 2.8 3.3 -- Max. 3.6 3.0 3.6 VCC + 0.3 V Unit V *1 * 2 Test Conditions VCC x 0.75 VCC - 0.6 VCC_28 x 0.9 2.0 -- -- -- -- VCC + 0.3 VCC + 0.3 VCC_28 + 0.3 VCC_28 + 0.3 VCC + 0.3 VCC x 0.1 V 2.0 -0.3 -- -- -0.3 -0.3 -- -- VCC x 0.2 VCC_28 x 0.1 -0.3 2.25 -- -- VCC x 0.2 -- V VCC_28, VCC = 2.7 V, IOH = -3 mA VCC_28, VCC = 2.7 V, IOH = -2 mA Other output pins 2.0 -- -- Rev. 1.00, 02/04, page 732 of 804 Item Symbol Min. -- Typ. -- Max. 0.55 Unit V Test Conditions VCC_28 = 3.0 V, IOL = 2.0 mA Output low RDI_TXTRDATA, VOL RDI_RXBDW_OUT, voltage RCI_SPI_CLK, RCI_SPI_ENB, RCI_SPI_TXRX RDI_CTRL4 VOL -- -- -- -- 0.25 0.55 V V VCC = 3.6 V, IOL = 0.5 mA VCC = 3.6 V, IOL = 2.0 mA Other output pins VOL Notes: *1 When Renesas Technology RF-IC (HD157100NP or HD157102NP) is connected. *2 Connect these pins to Vcc when RF-IC is not used. Notes: 1. AVCC conditions must be: VCC - 0.2 V AVCC (DAC) VCC + 0.2 V. Even if the D/A converter is not used, do not leave the AVCC (DAC) and AVSS (DAC) pins open. Connect AVCC (DAC) to VCC, and connect AVSS (DAC) to VSS. 2. Current consumption values shown are for VIH (Min.) = VCC - 0.5 V and VIL(Max.) = 0.5 V with all output pins unloaded. Table 28.2 DC Characteristics (2-b) USB Related Pins* Condition: Ta = -40 to 85C Item Power supply voltage Input high voltage Input low voltage Input high voltage (UCLK) Input low voltage (UCLK) Output high voltage Symbol VCC VIH VIL Min. 2.7 2.0 -0.3 Typ. 3.3 -- -- -- -- -- -- -- Max. 3.6 VCC + 0.3 VCC x 0.2 VCC + 0.3 VCC x 0.2 -- -- 0.55 V Unit V V V V V V VCC = 2.7 V, IOH = -200 A VCC = 2.7 V, IOH = -2 mA VCC = 3.6 V, IOL = 2.0 mA Test Conditions VIH(UCLK) VCC - 0.3 VIL(UCLK) -0.3 VOH 2.4 2.0 Output low voltage Note: * VOL -- The UCLK, USB_PWR_EN/USB_PULLUP, and USB_OVR_CRNT/USB_VBUS pins. Rev. 1.00, 02/04, page 733 of 804 Table 28.2 DC Characteristics (2-c) USB Transceiver Related Pins* Condition: Ta = -40 to 85C Item Power supply voltage Differential input sensitivity Differential common mode range Single ended receiver threshold voltage Output high voltage Output low voltage Tri-state leak current Note: * Symbol Min. Typ. 3.3 -- -- -- -- -- -- Max. 3.6 -- 2.5 2.0 Test Unit Conditions V V V V |(USB_P) - (USB_N)| AVCC(USB) 3.0 VDI VCM VSE VOH VOL ILO 0.2 0.8 0.8 2.8 -- -10 AVCC(USB) V 0.3 10 V A 0 V < VIN < 3.3 V The USB_P and USB_N pins. Table 28.3 Permissible Output Current Values Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, Ta = -40 to 85C Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL IOL -IOH (-IOH) Min. -- -- -- -- Typ. -- -- -- -- Max. 2 50 2 50 Unit mA mA mA mA Note: To ensure chip reliability, do not exceed the output current values given in table 28.3. Rev. 1.00, 02/04, page 734 of 804 28.3 AC Characteristics The input of this LSI is basically a synchronous input. The setup and hold time of each input signal should be kept unless any notice. Table 28.4 Operating Frequencies Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Operating frequency CPU, cache (I) External bus (B) Peripheral module (P) Symbol f Min 20 20 4 Typ -- -- -- Max 120 60 30 Unit MHz Remarks Rev. 1.00, 02/04, page 735 of 804 28.3.1 Clock Timing Table 28.5 Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C, maximum external bus operating frequency: 60 MHz Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time RESETP assert time (when Renesas RF-IC is connected) Power-On Oscillation Settling Time Oscillation Settling Time on Return from Standby 1 Oscillation Settling Time on Return from Standby 2 PLL synchronization settling time Symbol fEX tEXcyc tEXL tEXH tEXr tEXf fCKI tCKICYC tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOr tCKOf tRESPW tSOC1 tSOC2 tSOC3 tPLL Min 10 33.3 15 15 -- -- 20 16.6 4 4 -- -- 20 16.7 5 5 -- -- 100 Max 30 100 -- -- 4 4 60 50 -- -- 2 2 60 50 -- -- 6 6 -- Unit MHz ns ns ns ns ns MHz ns ns ns ns ns MHz ns ns ns ns ns s ms ms ms s 28.4, 28.5 28.3 28.2 Figure 28.1 10 10 10 100 -- -- -- -- 28.4 28.5 28.6 28.7, 28.8 Rev. 1.00, 02/04, page 736 of 804 tEXcyc EXTAL* (input) 1/2 VCC tEXH tEXL VIH 1/2 VCC tEXr VIH VIH VIL tEXf VIL Note: * When clock is input from EXTAL pin Figure 28.1 EXTAL Clock Input Timing tCKICYC CKIO (input) 1/2 VCC tCKIH tCKIL VIH 1/2 VCC tCKIR VIH VIH VIL tCKIF VIL Figure 28.2 CKIO Clock Input Timing tcyc tCKOH CKIO (output) 1/2VCC tCKOL VOH VOH VOL tCKOf VOH VOL 1/2VCC tCKOr Figure 28.3 CKIO Clock Output Timing Stable oscillation CKIO, internal clock VCC VCC min tSOC1 RESETP tRESPW Note: Oscillation settling time when on-chip oscillator is used Figure 28.4 Power-On Oscillation Settling Time Rev. 1.00, 02/04, page 737 of 804 Standby CKIO, internal clock Stable oscillation tSOC2 RESETP tRESPW Note: Oscillation settling time when on-chip oscillator is used Figure 28.5 Oscillation Settling Time on Return from Standby (Return by Reset) Standby CKIO, internal clock tSOC3 Stable oscillation NMI, IRQ4 to IRQ2, IRQ0 Note: Oscillation settling time when on-chip oscillator is used Figure 28.6 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ) Stable input clock EXTAL input VCC tRESPW RESETP tPLL PLL synchronization Internal reset signal CKIO output, PLL output Internal clock Figure 28.7 PLL Synchronization Settling Time at Power-On Reset Rev. 1.00, 02/04, page 738 of 804 Stable input clock Stable input clock EXTAL input PLL synchronization tPLL PLL synchronization CKIO output, PLL output Internal clock Figure 28.8 PLL Synchronization Settling Time in Case of Reset or NMI Interrupt Rev. 1.00, 02/04, page 739 of 804 28.3.2 Control Signal Timing Table 28.6 Control Signal Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C*2 Item RESETP pulse width RESETP setup time*1 RESETP hold time BOOT-E setup time* BREQ setup time BREQ hold time NMI setup time* NMI hold time IRQ4 to IRQ2, IRQ0 setup time* IRQ4 to IRQ2, IRQ0 hold time IRQOUT delay time REFOUT delay time BACK delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 1 1 4 Symbol tRESPW tRESPS tRESPH tBOOTS tBREQS tBREQH tNMIS tNMIH tIRQS tIRQH tIRQOD tREFOD tBACKD tBOFF1 tBOFF2 tBON1 tBON2 Min 100 30 4 50 1/2tcyc* + 7 1/2tcyc + 3 20 4 20 4 -- -- 1/2tcyc 0 0 0 0 3 Max -- -- -- -- -- -- -- -- -- -- 13 13 Unit s ns ns s ns ns ns ns ns ns ns ns Figure 28.9, 28.10 28.9 28.13 28.10 28.11 28.12 28.13, 28.14 1/2tcyc + 13 ns 30 30 30 30 ns ns ns ns 28.13, 28.14 Notes: 1. RESETP, NMI, IRQ4 to IRQ2, and IRQ0 are asynchronous. Changes are detected at the clock rise when the setup time shown is used. If the setup time cannot be used, detection may be delayed until the next clock rises. The pulse width of two cycles or more in peripheral module clock (P) is necessary for NMI and IRQ4 to IRQ2 and IRQ0 at the edge detection. 2. The upper limit of the external bus clock is 60 MHz. 3. tcyc means the external bus clock cycle (B clock cycle) 4. The BOOT-E signal should not be changed excluding for the period when RESETP asserts low (during the reset period). If the BOOT-E signal is changed excluding the reset period, operation cannot be guaranteed. Rev. 1.00, 02/04, page 740 of 804 CKIO tRESPS tRESPW RESETP tRESPS tBOOTS BOOT_E Figure 28.9 Reset and BOOT-E Input Timing CKIO tRESPH RESETP tNMIH NMI tIRQH IRQ4 to IRQ2, IRQ0 VIL tRESPS VIH VIL tNMIS VIH VIL tIRQS VIH Figure 28.10 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD IRQOUT Figure 28.11 IRQOUT Timing Rev. 1.00, 02/04, page 741 of 804 CKIO tREFOD tREFOD REFOUT Figure 28.12 REFOUT Timing tBOFF2 CKIO (HIZCNT=0) CKIO (HIZCNT=1) tBREQH tBREQS BREQ tBACKD BACK tBOFF1 A23 to A0, D15 to D0 RD, RD/WR, CSn, WEn, BS, CKE, RAS, CAS tBON1 tBACKD tBREQH tBREQS tBON2 tBOFF2 tBON2 Figure 28.13 Bus Release Timing Normal mode Standby mode Normal mode CKIO tBOFF2 tBON2 RD, RD/WR, CSn, WEn, BS, CKE, RAS, CAS tBOFF1 A23 to A0, D15 to D0 tBON1 Figure 28.14 Pin Drive Timing at Standby Rev. 1.00, 02/04, page 742 of 804 28.3.3 AC Bus Timing Table 28.7 Bus Timing Conditions: Clock modes 5, 6, 7*, VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C 60 MHz Item Address delay time 1 Address delay time 2 Address delay time 3 Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 Read/write delay time 1 Read/write delay time 2 Read strobe delay time Read data setup time 1 Read data setup time 2 Read data setup time 3 Read data setup time 4 Read data hold time 1 Read data hold time 2 Read data hold time 3 Read data hold time 4 Symbol Min tAD1 tAD2 tAD3 tAS tAH tBSD tCSD1 tCSD2 tRWD1 tRWD2 tRSD tRDS1 tRDS2 tRDS3 tRDS4 tRDH1 tRDH2 tRDH3 tRDH4 1 1/2tcyc 1/2tcyc 0 0 -- 1 1/2tcyc 1 1/2tcyc 1/2tcyc 7 Max 13 Unit Figure ns 28.15 to 28.45 28.22 28.40 to 28.42 28.15 to 28.22 28.15 to 28.21 28.15 to 28.39, 28.44, 28.45 28.15 to 28.39, 28.44, 28.45 28.40 to 28.42 28.15 to 28.39, 28.44, 28.45 28.40 to 28.42 28.15 to 28.22 28.15 to 28.21 28.23 to 28.26, 28.31 to 28.33, 28.44, 28.45 28.22 28.40 28.14 to 28.21 28.23 to 28.26, 28.31 to 28.33, 28.44, 28.45 28.22 28.40 28.15 to 28.21 28.21 28.15 to 28.21 28.27 to 28.30, 28.34 to 28.36, 28.44, 28.45 28.40 28.15 to 28.21 28.27 to 28.30, 28.34 to 28.36, 28.44, 28.45 Rev. 1.00, 02/04, page 743 of 804 1/2tcyc + 13 ns 1/2tcyc + 13 ns -- -- 13 13 ns ns ns ns 1/2tcyc + 13 ns 13 ns 1/2tcyc + 13 ns 1/2tcyc + 13 ns ns ns ns ns ns ns ns ns ns ns ns -- 1/2tcyc + 10 -- 1/2tcyc + 10 -- 1/2tcyc + 10 -- 0 2 0 0 1/2tcyc -- -- -- -- 1 1 -- -- -- -- 13 13 13 Write enable delay time 1 tWED1 Write enable delay time 2 tWED2 Write data delay time 1 Write data delay time 2 Write data delay time 3 Write data hold time 1 Write data hold time 2 tWDD1 tWDD2 tWDD3 tWDH1 tWDH2 1/2tcyc + 13 ns 1/2tcyc + 13 ns -- -- ns ns 66 MHz Item Write data hold time 3 WAIT setup time WAIT hold time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 DQM delay time 1 DQM delay time 2 CKE delay time 1 CKE delay time 2 Note: * Symbol tWDH3 tWTS1 tWTH1 tRASD1 tRASD2 tCASD1 tCASD2 tDQMD1 tDQMD2 tCKED1 tCKED2 Min 1/2tcyc 1/2tcyc + 7 1/2tcyc + 3 1 1/2tcyc 1 1/2tcyc 1 1/2tcyc 1 1/2tcyc Max -- -- -- 13 Unit ns ns ns ns Figure 28.40 28.15 to 28.22 28.15 to 28.22 28.23 to 28.39, 28.44, 28.45 28.40 to 28.43 28.23 to 28.39, 28.44, 28.45 28.40 to 28.43 28.23 to 28.39, 28.44, 28.45 28.40 to 28.43 28.38, 28.39, 28.44, 28.45 28.42 1/2tcyc + 13 ns 13 ns 1/2tcyc + 13 ns 13 13 ns ns 1/2tcyc + 13 ns 1/2tcyc + 13 ns The timing of SDRAM interface is in clock mode 7. It is recommended that the SDRAM interface be operated in clock 7. Rev. 1.00, 02/04, page 744 of 804 28.3.4 Basic Timing T1 CKIO tAD1 A23 to A0 tAS tCSD1 CSn tRWD1 RD/WR tRSD RD Read D15 to D0 tWED1 WEn Write D15 to D0 tBSD BS tBSD tWDD1 tWDH1 tWED1 tAH tRDS1 tRSD tAH tRDH1 tRWD1 tCSD1 tAD1 T2 tWTH1 WAIT tWTS1 Figure 28.15 Basic Bus Cycle in Normal Space (No Wait) Rev. 1.00, 02/04, page 745 of 804 T1 CKIO tAD1 A23 to A0 tAS tCSD1 CSn tRWD1 RD/WR tRSD RD Read D15 to D0 tWED1 WEn Write D15 to D0 tBSD BS tBSD tWDD1 Tw T2 tAD1 tCSD1 tRWD1 tRSD tAH tRDH1 tRDS1 tWED1 tAH tWDH1 tWTH tWTS WAIT Figure 28.16 Basic Bus Cycle in Normal Space (Software Wait 1) Rev. 1.00, 02/04, page 746 of 804 T1 Twx T2 CKIO tAD1 A23 to A0 tCSD1 tAS CSn tRWD1 RD/WR tRSD RD Read tAD1 tCSD1 tRWD1 tRSD tAH tRDH1 tRDS1 D15 to D0 tWED1 WEn Write tWED1 tAH tWDD1 D15 to D0 tBSD BS tWTH1 WAIT tWTS1 tWTS1 tWTH1 tBSD tWDH1 Figure 28.17 Basic Bus Cycle in Normal Space (Asynchronous External Wait 1 Input) Rev. 1.00, 02/04, page 747 of 804 T1 Tw T2 Taw T1 Tw T2 CKIO tAD1 A23 to A0 tCSD1 tAS CSn tRWD1 RD/WR tRSD RD tRSD tAH tRDH1 tRDS1 D15 to D0 tWED1 WEn tWED1 tAH tWED1 tWED1 tAH tRSD tRSD tAH tRDH1 tRDS1 tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tAS tCSD1 tAD1 tAD1 tAD1 Write Read tWDD1 D15 to D0 tBSD BS tWTH1 WAIT tWTS1 tBSD tWDH1 tWDD1 tWDH1 tBSD tBSD tWTH1 tWTS1 Figure 28.18 Basic Bus Cycle in Normal Space (Software Wait 1, Asynchronous External Wait Valid (WM Bit = 0), No Idle Cycle) Rev. 1.00, 02/04, page 748 of 804 Th T1 Twx T2 Tf CKIO tAD1 A23 to A0 tCSD1 CSn tRWD1 RD/WR tRSD RD tRSD tRDH1 tRDS1 D15 to D0 tWED1 WEn tWED1 tAH tAH tRWD1 tCSD1 tAD1 Write Read tWDD1 D15 to D0 tBSD BS tWTH1 WAIT tWTS1 tWTS1 tWTH1 tBSD tWDH1 Figure 28.19 CS Extended Bus Cycle in Normal Space (SW = 1 Cycle, HW = 1 Cycle, Asynchronous External Wait 1 Input) Rev. 1.00, 02/04, page 749 of 804 Th T1 Twx T2 Tf CKIO tAD1 tAD1 A23 to A0 tCSD1 CSn tWED1 WEn tRWD1 RD/WR tRSD Read tCSD1 tWED1 tAH tRWD1 tRSD tAH RD tRDH1 tRDS1 D15 to D0 tRWD1 RD/WR tRWD1 Write tWDD1 D15 to D0 tBSD BS tBSD tWDH1 tWTH1 WAIT tWTH1 tWTS1 tWTS1 Figure 28.20 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, Asynchronous External Wait 1 Input, BAS = 0 (UB and LB in Write Cycle Controlled)) Rev. 1.00, 02/04, page 750 of 804 Th T1 Twx T2 Tf CKIO tAD1 tAD1 A23 to A0 tCSD1 CSn tWED2 WEn tRWD1 RD/WR tRSD tRSD tAH tWED2 tCSD1 tAH Read RD tRDH1 tRDS1 D15 to D0 tRWD1 RD/WR tRWD1 tRWD1 Write tWDD1 D15 to D0 tBSD BS tWTH1 WAIT tWTH1 tBSD tWDH1 tWTS1 tWTS1 Figure 28.21 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, Asynchronous External Wait 1 Input, BAS = 1 (WE in Write Cycle Controlled)) Rev. 1.00, 02/04, page 751 of 804 28.3.5 Burst ROM Timing T1 Tw Twx T2B Twb T2B CKIO tAD1 tAD2 tAD2 tAD2 A23 to A0 tCSD1 CSn tRWD1 tRWD1 tAS tCSD1 RD/WR tRSD RD tRDS3 D15 to D0 tRDH3 tRDS3 tRDH3 tRSD WEn tBSD BS tWTH1 WAIT tWTH1 tBSD tWTS1 tWTS1 Figure 28.22 Read Bus Cycle of Burst ROM (Software Wait 1, Asynchronous External Wait 1 Input, Burst Wait 1, Number of Burst 2) Rev. 1.00, 02/04, page 752 of 804 28.3.6 Synchronous DRAM Timing Tr Tc Tcw Td1 Tde CKIO tAD1 tAD1 Row Address tAD1 tAD1 Column Address tAD1 READA Command tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tBSD BS (High) CKE tBSD tRDH2 tBSD tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tCSD1 tAD1 tAD1 A23 to A0 A11* Note: * Address pin that is connected to A10 of SDRAM Figure 28.23 Single Read Bus Cycle of Synchronous DRAM (Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 1 Cycle) Rev. 1.00, 02/04, page 753 of 804 Tr Trw Tc Tcw Td1 Tde Tap CKIO tAD1 Row Address tAD1 tAD1 tAD1 Column Address tAD1 READA Command tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tRDH2 tBSD BS (High) CKE tBSD tBSD tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tCSD1 tAD1 tAD1 A23 to A0 A11* Note: * Address pin that is connected to A10 of SDRAM Figure 28.24 Single Read Bus Cycle of Synchronous DRAM (Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycle, TRP = 2 Cycle) Rev. 1.00, 02/04, page 754 of 804 Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde Tap CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tRDH2 tBSD BS (High) CKE tRDH2 tBSD tRDH2 tRDH2 tRDS2 tRDS2 tRDS2 tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tAD1 Row Address tAD1 READ Command tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 Column Address4 tAD1 READA Command tCSD1 tAD1 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.25 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 2 Cycle) Rev. 1.00, 02/04, page 755 of 804 Tr Trw Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde Tap CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tRDH2 tBSD BS (High) CKE tRDH2 tBSD tRDH2 tRDH2 tRDS2 tRDS2 tRDS2 tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 Row Address tAD1 READ Command tAD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 Column Address4 tAD1 READA Command tCSD1 tAD1 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.26 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycle, TRP = 1 Cycle) Rev. 1.00, 02/04, page 756 of 804 Tr Tc Trwl CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tDQMD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tRWD1 tAD1 Row Address tAD1 tAD1 Column Address tAD1 WRITA Command tCSD1 tBSD BS (High) CKE tBSD Note: * Address pin that is connected to A10 of SDRAM Figure 28.27 Single Write Bus Cycle of Synchronous DRAM (Auto Precharge Mode, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 757 of 804 Tr Trw Trw Tc Trwl CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tDQMD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tRWD1 Row Address tAD1 tAD1 tAD1 Column Address tAD1 WRITA Command tCSD1 tBSD BS (High) CKE tBSD Note: * Address pin that is connected to A10 of SDRAM Figure 28.28 Single Write Bus Cycle of Synchronous DRAM (Auto Precharge Mode, TRCD = 3 Cycle, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 758 of 804 Tr Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tBSD BS (High) CKE tWDH2 tWDH2 tWDH2 tBSD tWDD2 tWDD2 tWDD2 tDQMD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tRWD1 tAD1 Row Address tAD1 WRIT Command tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 tAD1 Column Address4 tAD1 WRITA Command tCSD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.29 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 759 of 804 Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tBSD BS (High) CKE tWDH2 tWDH2 tWDH2 tBSD tWDD2 tWDD2 tWDD2 tDQMD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tRWD1 Row Address tAD1 WRIT Command tAD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 tAD1 Column Address4 tAD1 WRITA Command tCSD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.30 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 760 of 804 Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tRDH2 tBSD BS (High) CKE tRDH2 tBSD tRDH2 tRDH2 tRDS2 tRDS2 tRDS2 tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tAD1 Row Address tAD1 READ Command tCSD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 Column Address4 tAD1 tAD1 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.31 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Bank Active Mode: ACTV + READ Command, CAS Latency 2, TRCD = 1 Cycle) Rev. 1.00, 02/04, page 761 of 804 Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tRDH2 tBSD BS (High) CKE tRDH2 tBSD tRDH2 tRDH2 tRDS2 tRDS2 tRDS2 tDQMD1 tCASD1 tCASD1 tRASD1 tRWD1 READ Command tCSD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 Column Address4 tAD1 tAD1 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.32 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, TRCD = 1 Cycle) Rev. 1.00, 02/04, page 762 of 804 Tp Tpw Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 D15 to D0 tRDH2 tBSD BS (High) CKE tRDH2 tBSD tRDH2 tRDH2 tRDS2 tRDS2 tRDS2 tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tAD1 Row Address tAD1 READ Command tCSD1 tAD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 Column Address4 tAD1 tAD1 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.33 Burst Read Bus Cycle of Synchronous DRAM (Single Read x 4) (Bank Active Mode: PRE + ACTV + READ Command, Different Row Address, CAS Latency 2, TRCD = 1 Cycle) Rev. 1.00, 02/04, page 763 of 804 Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tBSD BS (High) CKE tWDH2 tWDH2 tWDH2 tBSD tWDD2 tWDD2 tWDD2 tDQMD1 tCASD1 tCASD1 tRASD1 tRASD1 tRWD1 tRWD1 tAD1 Row Address tAD1 WRIT Command tCSD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 Column Address4 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.34 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) Rev. 1.00, 02/04, page 764 of 804 Tnop Tc1 Tc2 Tc3 Tc4 CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tBSD BS (High) CKE tWDH2 tWDH2 tWDH2 tBSD tWDD2 tWDD2 tWDD2 tDQMD1 tCASD1 tCASD1 tRWD1 tRWD1 tAD1 WRIT Command tCSD1 tAD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 Column Address4 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.35 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) Rev. 1.00, 02/04, page 765 of 804 Tp Tpw Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tWDH2 tBSD BS (High) CKE tWDH2 tWDH2 tWDH2 tBSD tWDD2 tWDD2 tWDD2 tDQMD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tRWD1 tAD1 Row Address tAD1 WRIT Command tCSD1 tAD1 tAD1 Column Address1 tAD1 Column Address2 tAD1 Column Address3 tAD1 Column Address4 tAD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.36 Burst Write Bus Cycle of Synchronous DRAM (Single Write x 4) (Bank Active Mode: PRE + ACTV + WRIT Command, TRCD = 1 Cycle) Rev. 1.00, 02/04, page 766 of 804 Tp Tpw Trr Trc Trc Trc Trc CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tCSD1 tAD1 tAD1 tAD1 tAD1 D15 to D0 (High-Z) tBSD BS (High) CKE Note: * Address pin that is connected to A10 of SDRAM Figure 28.37 Auto Refresh Timing of Synchronous DRAM (TRP = 2 Cycle) Rev. 1.00, 02/04, page 767 of 804 Tp Tpw Trr Trc Trc Trc Trc Trc CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tDQMD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tCSD1 tAD1 tAD1 tAD1 tAD1 D15 to D0 (High-Z) tBSD BS tCKED 1 CKE tCKED 1 tCKED 1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.38 Self Refresh Timing of Synchronous DRAM (TRP = 2 Cycle) Rev. 1.00, 02/04, page 768 of 804 Tp Tpw Trr Trc Trr Trc Trc Tmw Tde CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tDQMD1 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 D15 to D0 (High-Z) tBSD BS tCKED (High) CKE 1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.39 Power-On Sequence of Synchronous DRAM (Mode Write Timing, TRP = 2 Cycle) Rev. 1.00, 02/04, page 769 of 804 Tr Tc Td1 Tde Tap Tr Tc Tnop Trwl Tap CKIO tAD3 A23 to A0 tAD3 A11* tCSD2 CS3 tRWD2 RD/WR tRASD2 RAS tCASD2 CAS tDQMD2 DQMn tRDS4 tRDH4 tWDD3 D15 to D0 tBSD BS (High) CKE (High) tBSD tBSD tBSD tWDH3 tDQMD2 tDQMD2 tDQMD2 tCASD2 tCASD2 tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tRWD2 tRWD2 tAD3 Row Address tAD3 tAD3 Column Address tAD3 READA Command tCSD2 tCSD2 tAD3 tAD3 tAD3 Row Address tAD3 Column Address tAD3 WRITA Command tCSD2 tAD3 tAD3 Note: * Address pin that is connected to A10 of SDRAM Figure 28.40 Access Timing in Low-Frequency Mode of Synchronous DRAM (Auto Precharge Mode, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 770 of 804 Tp Tpw Trr Trc Trc Trc Trc CKIO tAD3 A23 to A0 tAD3 A11* tCSD2 CS3 tRWD2 RD/WR tRASD2 RAS tCASD2 CAS tDQMD2 DQMn tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tRWD2 tCSD2 tCSD2 tCSD2 tAD3 tAD3 D15 to D0 (High-Z) BS (High) CKE Note: * Address pin that is connected to A10 of SDRAM Figure 28.41 Auto Refresh Timing in Low-Frequency Mode of Synchronous DRAM (TRP = 2 Cycle) Rev. 1.00, 02/04, page 771 of 804 Tp Tpw Trr Trc Trc Trc Trc Trc CKIO tAD3 A23 to A0 tAD3 A11* tCSD2 CS3 tRWD2 RD/WR tRASD2 RAS tCASD2 CAS tDQMD2 DQMn tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tRWD2 tCSD2 tCSD2 tCSD2 tAD3 tAD3 (Hi-Z) D15 to D0 BS tCKED2 CKE tCKED2 Note: * Address pin that is connected to A10 of SDRAM Figure 28.42 Self Refresh Timing in Low-Frequency Mode of Synchronous DRAM (TRP = 2 Cycle) Rev. 1.00, 02/04, page 772 of 804 Tp Tpw Trr Trc Trr Trc Trc Tmw Tde CKIO tAD3 A23 to A0 tAD3 A11* tCSD2 CS3 tRWD2 RD/WR tRASD2 RAS tCASD2 CAS tDQMD2 DQMn tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRASD2 tRWD2 tRWD2 tRWD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tAD3 tAD3 tAD3 tAD3 D15 to D0 (High-Z) BS (High) CKE Note: * Address pin that is connected to A10 of SDRAM Figure 28.43 Power-On Sequence in Low-Frequency Mode of Synchronous DRAM (Mode Write Timing, TRP = 2 Cycle) Rev. 1.00, 02/04, page 773 of 804 Tr Tc Trwl Tr Tc Tcw Td1 Tde CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tWDD2 D15 to D0 tBSD BS tCKED1 CKE tCKED1 tBSD tBSD tBSD tBSD tWDH2 tRDS2 tRDH2 tDQMD1 tDQMD1 tDQMD1 tCASD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tAD1 Row Address tAD1 Column Address tAD1 tAD1 Row Address Column Address tAD1 tAD1 tAD1 WRITA Command tAD1 tAD1 tAD1 READA Command tAD1 tCSD1 tCSD1 tCSD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.44 Write to Read Bus Cycle in Power-Down Mode of Synchronous DRAM (Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 774 of 804 Tr Tc Tcw Td1 Tde Tr Tc Trwl CKIO tAD1 A23 to A0 tAD1 A11* tCSD1 CS3 tRWD1 RD/WR tRASD1 RAS tCASD1 CAS tDQMD1 DQMn tRDS2 tRDH2 D15 to D0 tBSD BS tCKED1 CKE tCKED1 tBSD tBSD tBSD tBSD tWDD2 tWDH2 tDQMD1 tDQMD1 tDQMD1 tCASD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tRASD1 tRASD1 tRWD1 tRWD1 tAD1 Row Address Column Address tAD1 tAD1 Row Address Column Address tAD1 tAD1 tAD1 tAD1 READA Command tAD1 tAD1 tAD1 WRITA Command tAD1 tCSD1 tCSD1 tCSD1 Note: * Address pin that is connected to A10 of SDRAM Figure 28.45 Read to Write Bus Cycle in Power-Down Mode of Synchronous DRAM (Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle) Rev. 1.00, 02/04, page 775 of 804 28.3.7 Peripheral Module Signal Timing Table 28.8 Peripheral Module Signal Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Module I/O Port Item Output data delay time Input data setup time Input data hold time DMAC DREQ setup time DREQ hold time DACK delay time TEND delay time Symbol tPORTD tPORTS tPORTH tDREQS tDREQH tDACKD tTENDD Min -- 17 10 8 8 -- Max 17 -- -- -- -- 14 14 28.48 ns 28.47 Unit ns Figure 28.46 CKIO tPORTS tPORTH Ports A, B, D, E, G and H (read) tPORTD Ports A, B, D, E, G and H (write) Figure 28.46 I/O Port Timing CKIO tDREQS tDREQH DREQn Figure 28.47 DREQ Input Timing (DREQ Low Level is Detected) CKIO tDACKD, tTENDD DACKn, TEND tDACKD, tTENDD Figure 28.48 DACK and TEND Output Timing Rev. 1.00, 02/04, page 776 of 804 28.3.8 SIOF Module Signal Timing Table 28.9 SIOF Module Signal Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Symbol tMCYC tMWH tMWL tSICYC tSWHO tSWLO tFSD tSWHI tSWLI tFSS tFSH tSTDD tSRDS tSRDH tSSS tSSH Min tPCYC 0.4 x tMCYC 0.4 x tMCYC tpcyc 0.4 x tSICYC 0.4 x tSICYC -- 0.4 x tSICYC 0.4 x tSICYC 20 20 -- 20 10 2 Item SIOF_MCLK clock input cycle time SIOF_MCLK input high level width SIOF_MCLK input low level width SIOF_SCK clock cycle time SIOF_SCK output high level width SIOF_SCK output low level width SIOF_SYNC output delay time SIOF_SCK input high level width SIOF_SCK input low level width SIOF_SYNC input setup time SIOF_SYNC input hold time SIOF_TXD output delay time SIOF_RXD input setup time SIOF_RXD input hold time Slave select setup time Slave select hold time Max -- -- -- -- -- -- 20 -- -- -- -- 20 -- -- 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 28.49 28.49 28.49 28.50 to 28.54 28.50 to 28.53 28.50 to 28.53 28.50 to 28.53 28.54 28.54 28.54 28.54 28.50 to 28.54 28.50 to 28.54 28.50 to 28.54 28.55 to 28.56 28.55 to 28.56 tSICYC/2 x n* -20 tSICYC/2 x n* Notes: 1. tPCYC is a cycle time of a peripheral clock (P). 2. tSICYC/2 x n is defined according to the SSAST1 and SSAST0 bits in SPICR. tMCYC SIOF_MCLK tMWH tMWL Figure 28.49 SIOF_MCLK Input Timing Rev. 1.00, 02/04, page 777 of 804 tSICYC tSWHO SIOF_SCK (output) tSWLO tFSD SIOF_SYNC (output) tFSD tSTDD SIOF_TXD tSTDD tSRDS SIOF_RXD tSRDH Figure 28.50 SIOF Transmission/Reception Timing (Master Mode 1, Falling Edge Sampling) tSICYC tSWLO SIOF_SCK (output) tSWHO tFSD tFSD SIOF_SYNC (output) tSTDD SIOF_TXD tSTDD tSRDS SIOF_RXD tSRDH Figure 28.51 SIOF Transmission/Reception Timing (Master Mode 1, Rising Edge Sampling) Rev. 1.00, 02/04, page 778 of 804 tSICYC tSWHO SIOF_SCK (output) tSWLO tFSD tFSD SIOF_SYNC (output) tSTDD SIOF_TXD tSTDD tSTDD tSTDD tSRDS SIOF_RXD tSRDH Figure 28.52 SIOF Transmission/Reception Timing (Master Mode 2, Falling Edge Sampling) tSICYC tSWLO SIOF_SCK (output) tSWHO tFSD tFSD SIOF_SYNC (output) tSTDD SIOF_TXD tSTDD tSTDD tSTDD tSRDS SIOF_RXD tSRDH Figure 28.53 SIOF Transmission/Reception Timing (Master Mode 2, Rising Edge Sampling) Rev. 1.00, 02/04, page 779 of 804 tSICYC tSWHI SIOF_SCK (input) tSWLI tFSS SIOF_SYNC (input) tFSH tSTDD SIOF_TXD tSTDD tSRDS SIOF_RXD tSRDH Figure 28.54 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) SCK (CPOL=0) SCK (CPOL=1) tSTDD MOSI MSB tSRDS MISO tSSS SSn MSB tSRDH LSB tSSH LSB Figure 28.55 SIOF Transmission/Reception Timing (SPI Mode, CPHA = 0, SSAST1 and SSAST0 = 01) Rev. 1.00, 02/04, page 780 of 804 SCK (CPOL=0) SCK (CPOL=1) tSTDD MOSI MSB tSRDS MISO tSSS SSn MSB tSRDH LSB tSSH LSB Figure 28.56 SIOF Transmission/Reception Timing (SPI Mode, CPHA = 1, SSAST1 and SSAST0 = 01) 28.3.9 SCIF Module Signal Timing Table 28.10 SCIF Module Signal Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC = 2.7 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Symbol Asynchronous Synchronous tSCWH tSCWL tTXD tRXS tRXH tSCYC Min 4 x tPCYC 12 x tPCYC 0.4 x tPCYC 0.4 x tPCYC -- 2 x tPCYC 2 x tPCYC Max -- -- -- -- 3tPCYC + 50 -- -- Unit ns ns ns ns ns ns ns 28.58 Figure 28.57, 28.58 28.57 Item SCIF input clock cycle SCIF input clock high level width SCIF input clock low level width SCIF transmit data delay time SCIF transmit data setup time (synchronous) SCIF transmit data hold time (synchronous) Note: tpcyc is a cycle time of a peripheral clock (P). Rev. 1.00, 02/04, page 781 of 804 tSCWH SCIF0_SCK SCIF1_SCK tSCWL tSCYC Figure 28.57 SCIF Input Clock Cycle tSCYC SCIF0_SCK SCIF1_SCK SCIF0_TxD SCIF1_TxD tTXD tRXS tRXH SCIF0_RxD SCIF1_RxD Figure 28.58 Input/Output Timing in SCIF Synchronous Mode 28.3.10 USB Module Signal Timing Table 28.11 USB Module Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC(USB) = 3.0 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Symbol tR48 tF48 tHIGH/tLOW Min. -- -- 90 Max. 4 4 110 Unit ns ns % Figure 28.59 Item Clock rise time Clock fall time Duty Table 28.12 USB Module Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28= 2.7 to 3.0 V, AVCC(USB) = 3.0 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Symbol 1/tFREQ Frequency 48.0 ( 500 ppm) 48.0 ( 2500 ppm) Unit MHz MHz Condition USB Host is used USB Function is used Item Frequency Rev. 1.00, 02/04, page 782 of 804 Note: When USB is operated by a clock which is supplied from an external device to the UCLK pin without using the on-chip multiplier circuit, the clock should be in conformance with the USB specifications Ver. 1.1. tFREQ tHIGH 90% 10% tLOW tR48 tF48 Figure 28.59 USB Clock Timing 28.3.11 USB Transceiver Timing Table 28.13 USB Transceiver Timing (Full-Speed) Conditions: VCC = 2.7 to 3.6 V, AVCC(USB) = 3.0 to 3.6 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Rise time Fall time Rise/fall time ratio Output signal crossover voltage Output driver resistance* Symbol tr tf tr/tf VCRS ZDRU Min. 4 4 80 1.3 28 Typ. -- -- -- -- -- Max. 20 20 120 2.0 44 Unit ns ns % V -- Test Conditions CL = 50 pF CL = 50 pF Note: Includes an externally connected series resistance, RS = 27 1 %. Table 28.14 USB Transceiver Timing (Low-Speed) Conditions: VCC = 2.7 to 3.6 V, AVCC(USB) = 3.0 to 3.5 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Rise time Symbol tr tf tr/tf VCRS Min. 75 -- Fall time 75 -- Rise/fall time ratio Output signal crossover voltage 80 1.3 Typ. -- -- -- -- -- -- Max. -- 300 -- 300 125 2.0 Unit ns ns ns ns % V -- Test Conditions CL = 200 pF CL = 600 pF CL = 200 pF CL = 600 pF Rev. 1.00, 02/04, page 783 of 804 tr USB_P tf 90% USB_N 10% VCRS Figure 28.60 USB Transceiver Timing Testing Circuits: USB_P RS = 27 Device under test USB_N RS = 27 CL CL Figure 28.61 USB Transceiver Characteristics Testing Circuit (Full-Speed) Vcc 1.5 k USB_P RS = 27 Device under test USB_N RS = 27 15 k CL CL Figure 28.62 USB Transceiver Characteristics Testing Circuit (Low-Speed) Rev. 1.00, 02/04, page 784 of 804 28.3.12 Bluetooth Interface (BT) Timing Table 28.15 Bluetooth Interface Module Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Rise time Fall time Duty Symbol tR tF tHIGH/tLOW Min. 90 Typ. 100 Max. 4 4 110 Unit ns ns % Figure 28.63 Table 28.16 Bluetooth Interface Module Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Frequency Note: * Symbol 1/tFREQ Frequency 13.0 ( 20 ppm) Unit MHz Condition When Renesas RF-IC is connected.* When Renesas Technology RF-IC (HD157100NP or HD157102NP) is connected. tFREQ tHIGH RDI_REFCLK_IN 90% 10% tLOW tR tF Figure 28.63 Bluetooth Module Clock Timing Table 28.17 Bluetooth Interface Module Low Power Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Rise time Fall time Duty Symbol tR tF tHIGH/tLOW Min. 90 Typ. 100 Max. 4 4 110 Unit ns ns % Figure 28.64 Rev. 1.00, 02/04, page 785 of 804 Table 28.18 Bluetooth Interface Module Low Power Clock Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Frequency Symbol 1/tFREQ Frequency 32.0 ( 250 ppm) 32.768 ( 250 ppm) Unit kHz kHz Condition Frequency conversion circuit is bypassed Frequency conversion circuit is used (maximum error is about 30 s) tFREQ tHIGH EXTAL2 (When RTCSEL0 = 0) 90% 10% tLOW tR tF Figure 28.64 Bluetooth Interface Module Low Power Clock Timing Table 28.19 Bluetooth Interface (BT) Voice CODEC Interface Signal Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item VCI_SCO_CLK_OUT clock output frequency VCI_SCO_SYNC_OUT output delay time VCI_SCO_RX output delay time VCI_SCO_TX setup time VCI_SCO_TX hold time VCI_HWC output delay time* Note: * Symbol fVCI_CLK tSYNCD tRXD tTXS tTXH tHWCD Min. 0.2 100 100 Typ. Max. 1 200 200 200 Unit MHz ns ns ns ns ns Figure 28.65, 28.66 28.65, 28.66 28.65, 28.66 28.65, 28.66 28.65, 28.66 28.65 In case that the STLC7550 is connected as the external Voice CODEC IC. Rev. 1.00, 02/04, page 786 of 804 1/fVCI_CLK VCI_SCO_CLK_OUT tSYNCD VCI_SCO_SYNC_OUT tRXD VCI_SCO_RX tTXS VCI_SCO_TX tHWCD VCI_HWC tTXH Figure 28.65 Bluetooth Interface (BT) Voice CODEC (STLC7550) Interface Signal Timing 1/fVCI_CLK VCI_SCO_CLK_OUT tSYNCD VCI_SCO_SYNC_OUT tRXD VCI_SCO_RX tTXS VCI_SCO_TX tTXH Figure 28.66 Bluetooth Interface (BT) Voice CODEC (MC145483) Interface Signal Timing Table 28.20 SPI Interface Signal Timing for Bluetooth Interface (BT) RF Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item RCI_SPI_CLK clock output frequency* RCI_SPI_CLK duty RCI_SPI_TXRX output delay time RCI_SPI_TXRX setup time RCI_SPI_TXRX hold time Note: * tDELAY tSETUP tHOLD Symbol fSPI_CLK Min. 45 40 45 Typ. 6.5 50 Max. 55 30 Unit MHz % ns ns ns Figure 28.67 28.67 28.67 28.67 28.67 When Renesas Technology RF-IC (HD157100NP or HD157102NP) is connected. Rev. 1.00, 02/04, page 787 of 804 1/fSPI_CLK RCI_SPI_CLK tDELAY RCI_SPI_TXRX tSETUP tHOLD RCI_SPI_TXRX Figure 28.67 SPI Interface Signal Timing for Bluetooth Interface (BT) RF Table 28.21 Receive Data Timing Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item RDI_TXTRDATA Symbol tTXTRDATA Min. 0.7 Typ. 1 Max. 1.3 Unit s Figure 28.68 tTXTRDATA RDI_TXTRDATA Figure 28.68 Bluetooth Interface (BT) Receive Data Timing Rev. 1.00, 02/04, page 788 of 804 28.3.13 AC Characteristic Test Conditions * I/O signal reference level: 1.5 V (VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V) * Input pulse level: VSS to 3.3 V (where RESETP, RDI_TXTRDATA, RDI_RXBDW_OUT, RDI_CTRL4, RDI_REFCLK_IN, RCI_SPI_CLK, RCI_SPI_ENB, and RCI_SPI_TXRX are within VSS to 2.8 V) * Input rise and fall times: 1 ns IOL LSI output pin Reference voltage of output load switch CL VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30pF: CKIO, CS0, CS3, CS4 50pF: All other pins IOL = 0.2mA, IOH = -0.2mA 2. Figure 28.69 Output Load Circuit Rev. 1.00, 02/04, page 789 of 804 28.4 D/A Converter Characteristics Table 28.22 lists the D/A converter characteristics. Table 28.22 D/A Converter Characteristics Conditions: VCC = 2.7 to 3.6 V, VCC_28 = 2.7 to 3.0 V, VDD = 1.4 to 1.6 V, Ta = -40 to 85C Item Resolution Conversion time (20pF load capacitance) Absolute accuracy (2M load resistance) Min. 8 -- -- Typ. 8 -- -- Max. 8 10 4.0 Unit bits s LSB Rev. 1.00, 02/04, page 790 of 804 Appendix A. Pin States The initial values differ in each operating mode (reset, power-down mode, bus-released state). The following symbols are used in the table. Legend O : Output I : Input IP : Input (Pull-up MOS on) H : High-level output L : Low-level output Z1 : High impedance (I/O buffer off, and pull-up MOS off) Z2 : High impedance (Output buffer off) P : I or O, depending on register setting K : Input pins are high-impedance, and output pins retain their state. V : I/O buffer off, and pull-up MOS on Table A.1 Reset Power-On Manual Reset Reset I O I, O* I I IP I Z1 I V V 1 Power-Down Mode BusSoftware Module Released Standby Standby Sleep State I O 1 Type Clock Pin Name EXTAL XTAL CKIO I O I, O* I I IP I O I I I I O 12 I O 1 Z, I, O* * I I IP I O I I O I, O* I I IP I O I I O Z, I, O* * I I IP I O I I O 12 Operation mode Control MD5, MD2, MD1 System control RESETP BOOT_E BREQ BACK Interrupt NMI IRQ4 to IRQ2, IRQ0 IRQOUT Rev. 1.00, 02/04, page 791 of 804 Reset Power-Down Mode Type Address bus Pin Name A23 to A19, A0 A18 to A1 BusPower-On Manual Software Module Released Reset Reset Standby Standby Sleep State Z1 O Z1 H H H H H H H H H O IP V V V V V V V O O Z1 O O O O O O O O O O I I O O O I O I O O O Z1 Z1 Z1 O I Z, O * Z, O * Z1 Z, O* Z, O* 3 3 O O I, O O O O O O O O O O O IP I O O O I I, O I I, O O O O I I, O O I Z1 Z2 Z1 Z2 Z2 Z2 Z2 Z2 Z2 Z, O* Z, O* Z, O* O IP I O O O I I, O I I, O O O O I I, O O I 4 3 Data bus Bus control D15 to D0 CS0, CS3, CS4 RD RD/WR BS WE1/DQM1 WE0/DQM0 CAS RAS CKE REFOUT WAIT 3 Z, O* Z, O* Z, O* Z, O* Z, O* Z, O* Z, O* O IP Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 3 3 3 3 3 3 4 3 4 Direct Memory DREQ Access DACK Controller TEND (DMAC) Serial I/O with FIFO (SIOF) SIOF_TXD(MOSI) SIOF_RXD(MISO) SIOF_SCK(SCK) SIOF_MCLK SIOF_SYNC(SIOF_SS0) V SIOF_SS1 SIOF_SS2 Serial communication interface with FIFO (SCIF0, 1) V V SCIF0_TxD, SCIF1_TxD Z1 SCIF0_RxD, SCIF1_RxD V SCIF0_SCK, SCIF1_SCK SCIF0_RTS, SCIF1_RTS SCIF0_CTS, SCIF1_CTS V V V Rev. 1.00, 02/04, page 792 of 804 Reset Power-Down Mode Type USB Pin Name UCLK USB_PWR_EN/ USB_PULLUP USB_OVR_CRNT/ USB_VBUS USB_N USB_P BusPower-On Manual Software Module Released Reset Reset Standby Standby Sleep State I O I I, O I, O O O I O O O O O O Z1 Z1 V V V I O I I, O I, O O O I O O O O O O O O I O O O I I I O O P P P P I O I I, O I, O O O I O O O O O O O O I O O O I I I O O K K K K I O I I, O I, O O O I O O O O O O O O I O O O I I I O O P P P P I O I I, O I, O O O I O O O O O O O O I O O O I I I O O P P P P Bluetooth interface (BT) RDI_TXTRDATA RDI_RXBDW_OUT RDI_REFCLK_IN RDI_CTRL2 RDI_CTRL3 RDI_CTRL4 RCI_SPI_CLK RCI_SPI_TXRX RCI_SPI_ENB VCI_SCO_CLK_OUT VCI_SCO_SYNC_OUT VCI_SCO_TX VCI_SCO_RX VCI_HWC VCI_CODEC_PWRDWN V RTCSEL0 RREF EXTAL2 XTAL2 D/A converter (DAC) I/O port DA1, DA0 PTA6 to PTA0 PTB7 to PTB0* 5 I I I O Z2 V V V V PTD5 to PTD0* PTE6 to PTE0* 5 5 Rev. 1.00, 02/04, page 793 of 804 Reset Power-Down Mode Type I/O port Pin Name PTG4 to PTG2, PTG0 PTG1 PTH4 to PTH2, PTH0 PTH1 BusPower-On Manual Software Module Released Reset Reset Standby Standby Sleep State V Z1 V Z1 I IP IP Z2 IP O O H O I P P P P I IP IP Z2 IP O O H O I K K K K I IP IP Z2 IP O O H O I P P P P I IP IP Z2 IP O O H O I P P P P I IP IP Z2 IP O O H O I User debugging interface (H-UDI) TCK TMS TDI TDO TRST Advanced user AUDATA3 to AUDATA0 debugger AUDCK (AUD) AUDSYNC E10A interface ASEBRKAK ASEMD0 Notes: 1. Depends on clock operating mode. 2. I, O, or Z, depending on register setting. I or O, depending on clock operating mode. 3. O or Z, depending on register setting in software standby mode. 4. O or Z, depending on register setting in bus released state. 5. These pins are multiplexed with the BSC function, and there are some pins which initial becomes a bus controller function. Please refer to table 24.1 for details. Rev. 1.00, 02/04, page 794 of 804 B. Usage Notes for Oscillator circuit with External Crystal Resonator On a design of the oscillator circuit with the external crystal resonator, values of external component should be chosen from the evaluation results examined with the crystal resonator manufacturer. The evaluation result examples by Kinseki,Limited are shown below. B.1 Recommended Oscillator Circuit This LSI EXTAL XTAL Rf Crystal resonator specifications Rd Rx Part number Package size CX-53G 5.0 x 3.2 x 1.3mm x-tal C1 C2 Evaluation results: Crystal resonator part number Oscillating frequency (kHz) Overtone number Shunt capacitance (pF) Recommended Rf external circuit Rd parameters Rx C1 C2 CX-53G 11289.6 fundamental oscillation 8.0 No connect. 0 0 7pF 7pF -5442 7.93 +1.1 83 CX-53G 18432 fundamental oscillation 8.0 No connect. 0 0 7pF 7pF -2826 7.91 +1.5 125 CX-53G 30000 fundamental oscillation 8.0 No connect. 0 0 8pF 8pF -943 8.07 -1.7 65 Characteristics Negative resistance () under Load capacitance (pF) recommended Frequency deviation ( x 10-6) parameters Drive level (W) Note: The characteristics of the oscillator circuit vary with the external circuit parameters and the PCB layout. After an evaluation of the matching between the crystal resonator and the oscillator circuit sufficiently, choose the circuit parameter and PCB layout. The recommended external circuit parameters and characteristics are only guideline and recommendations. They are not guaranteed on the user application systems. For the designing the PCB layout, refer to section B2 Note for PCB design. Rev. 1.00, 02/04, page 795 of 804 B.2 Note on PCB design Following items should be considered for the PCB design. The external oscillator circuit should be placed as near from oscillator IC as possible. Ground plane should not be placed under the oscillator circuit area. Signal line length should be shorter ( shorter than 2cm ). Keep spacing between two signal lines connected to the crystal resonator. Do not place them close to each other. * If a shield is required for oscillator circuit, the shield area should be as small as necessary. Board Crystal oscillator circuit No wiring area ( no ground plane and signal line ) * * * * Inner layer Note: Thick lines are the ground plane and signal lines except the oscillator circuit. If the shield plane connected to the ground is required for oscillation circuit, the farthest layer from the oscillator circuit should be used. PCB cross section (multi-layer board) IC Feedback resistor x-tal shorter than 2cm Capacitor GND Top view of PCB For further information on Appendix B, please contact: Kinseki,Limited (Headquarter) 1-8-1, Izumihon-cho, Komae-shi, Tokyo, 201-8648 Japan http://www.kinseki.co.jp/ E-mail:kanriks@kinseki.co.jp Oversea sales TEL +81-3-5497-3111 FAX +81-3-5497-3209 Rev. 1.00, 02/04, page 796 of 804 C. Package Dimensions For package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority. As of January, 2003 Unit: mm 0.20 C B 12.00 0.65 0.20 C A 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 A C E B D F H K M P T B 12.00 G J L N R U A 0.80 0.65 4x 0.15 0.80 208 x 0.40 0.05 0.08 M C A B 0.2 C C 0.31 0.05 1.20Max 0.10 C Package Code JEDEC JEITA Mass (reference value) TBP-208A - - 0.26 g Figure C.1 Package Dimensions (TBP-208A) Rev. 1.00, 02/04, page 797 of 804 Rev. 1.00, 02/04, page 798 of 804 Index 16-Bit/32-bit displacement ....................... 48 Absolute addresses ................................... 48 Access wait control................................. 256 Address array.................................. 178, 186 Address-array read.................................. 186 Address-array write (associative operation) ................................................................ 186 Address-array write (non-associative operation)................................................ 186 Addressing modes..................................... 49 Area division........................................... 221 Asynchronous mode ............................... 462 AUD ....................................................... 683 Auto-reload count operation ................... 378 Auto-request mode ................................. 315 Baud rate generator................................. 410 Big endian......................................... 45, 248 Bluetooth HCI/TCI commands............... 622 Bluetooth interface ................................. 611 Boot function .......................................... 491 Bulk-in transfer....................................... 594 Bulk-out transfer..................................... 595 Burst mode.............................................. 326 Burst ROM interface............................... 285 Bus arbitration ........................................ 291 Bus clock ................................................ 333 Bus state controller ................................. 217 Byte-selection SRAM interface .............. 287 Cache ...................................................... 177 Canceling software standby.................... 352 Clock operating modes ........................... 337 Clock pulse generator ............................. 333 Clock synchronous mode................ 457, 475 Clock-resume control.............................. 622 Control registers ................................. 36, 41 Control transfer....................................... 587 CPU .......................................................... 29 CPU extended instructions ....................... 81 Cycle-steal mode .................................... 325 D/A converter ......................................... 623 Data alignment ........................................ 248 Data array........................................ 178, 187 Data-array read........................................ 187 Data-array write ...................................... 187 Delayed branching .................................... 47 Direct memory access controller............. 297 Double data transfer instructions .............. 97 DSP data operation instructions.............. 107 DSP data transfer instructions................... 96 DSP instructions...................................... 111 DSP operating unit.................................... 73 DSP registers..................................... 80, 107 DSP repeat control .................................... 81 DSP status register .................................. 109 Dual address mode.................................. 321 Effective address....................................... 49 Effective addresses.................................... 49 Exception code........................................ 158 Exception codes ...................................... 159 Exception handling ................................. 155 Exception handling state ........................... 29 Exception vector addresses ..................... 159 External address space .............................. 34 External request mode............................. 315 General exceptions.................................. 165 General registers ................................. 36, 38 Global base register................................... 44 I/O ports .................................................. 627 Instruction formats .................................... 53 Intermittent mode.................................... 325 Internal clock .......................................... 333 Interrupt controller .................................. 199 Interrupt-in transfer................................. 593 Interval timer mode................................. 353 IRQ interrupts ......................................... 211 Isochronous out transfer.......................... 599 Isochronous-in transfer ........................... 597 JTAG....................................................... 683 Rev. 1.00, 02/04, page 799 of 804 Literal constant ......................................... 48 Little endian...................................... 46, 248 Load/store architecture ............................. 47 Logical address space ............................... 31 LRU ........................................................ 178 Manual reset ........................................... 164 Module standby ...................................... 368 Modulo addressing ................................. 103 Modulo register ........................................ 78 Multiple interrupts .................................. 216 Multiply and accumulate registers............ 39 NMI interrupt.......................................... 211 Notes on board design ............................ 344 On-chip peripheral module interrupts..... 212 On-chip peripheral module request ........ 316 P0 area ...................................................... 32 P1 area ...................................................... 32 P2 area ...................................................... 32 P3 area ...................................................... 32 P4 area ...................................................... 32 PC trace .................................................. 676 Peripheral clock ...................................... 333 Physical address space.............................. 33 Pin function controller ............................ 639 Power-down modes ................................ 355 Power-down state ..................................... 29 Power-on reset ........................................ 164 Prefetch hit.............................................. 184 Prefetch miss .......................................... 184 Privileged mode........................................ 30 Procedure register ..................................... 39 Processing modes ..................................... 30 Program counter ................................. 36, 40 Read hit................................................... 184 Read miss ............................................... 184 Receive margin....................................... 488 Refreshing............................................... 277 Registers All registers ........................................ 727 BAMRA ......................658, 704, 721, 728 BAMRB.......................661, 704, 721, 727 BARA..........................657, 704, 721, 728 BARB ..........................660, 703, 720, 727 Rev. 1.00, 02/04, page 800 of 804 BBRA ......................... 658, 704, 721, 728 BBRB.......................... 663, 704, 721, 728 BDMRB...................... 662, 703, 720, 727 BDRB ......................... 661, 703, 720, 727 BETR .......................... 667, 703, 720, 727 BRCR.......................... 664, 703, 720, 727 BRDR ......................... 670, 704, 721, 728 BRSR .......................... 669, 704, 721, 728 CCR1 .......................... 179, 698, 705, 722 CCR2 .......................... 180, 698, 705, 722 CHCR ................................................. 302 CHCR_0 ..................................... 699, 723 CHCR_1 ............................. 699, 710, 723 CHCR_2 ............................. 699, 710, 723 CHCR_3 ............................. 700, 711, 723 CHCR0 ............................................... 709 CLTR .................................................. 576 CMNCR...................... 225, 699, 707, 723 CS0BCR ................................ 699, 707, 723 CS0WCR................................ 699, 707, 723 CS3BCR ............................. 699, 707, 723 CS3WCR ............................ 699, 707, 723 CS4BCR ............................. 699, 707, 723 CS4WCR ............................ 699, 708, 723 CSnBCR ............................................. 227 CSnWCR ............................................ 231 CTLR .................................. 703, 719, 727 CVR ............................ 575, 703, 719, 727 DACR ......................... 625, 703, 719, 727 DADR ................................................. 624 DADR_0 ............................. 703, 719, 727 DADR_1 ............................. 703, 719, 727 DAR.................................................... 301 DAR_0........................................ 699, 723 DAR_1................................ 699, 709, 723 DAR_2................................ 699, 710, 723 DAR_3................................ 700, 711, 723 DAR0.................................................. 709 DASTS........................ 572, 703, 719, 726 DMA ........................... 573, 703, 719, 727 DMAOR ..................... 308, 700, 711, 724 DMARS .............................................. 310 DMARS0 ............................ 700, 711, 724 DMARS1 ............................ 700, 711, 724 DMARS2 ............................................ 724 DMATCR ........................................... 301 DMATCR_0 ............................... 699, 723 DMATCR_1 ....................... 699, 709, 723 DMATCR_2 ....................... 699, 710, 723 DMATCR_3 ....................... 700, 711, 723 DMATCR0 ......................................... 709 EPDR0i....................... 566, 702, 718, 726 EPDR0o...................... 567, 702, 718, 726 EPDR0s ...................... 567, 702, 718, 726 EPDR1........................ 567, 702, 718, 726 EPDR2i....................... 568, 702, 718, 726 EPDR2o...................... 568, 702, 718, 726 EPDR3i....................... 568, 702, 718, 726 EPDR3o...................... 569, 702, 718, 726 EPDR4........................ 569, 702, 718, 726 EPDR5........................ 569, 702, 718, 726 EPDR6........................ 570, 702, 718, 726 EPIR ................................... 703, 719, 727 EPIRn ................................................. 578 EPSTL ........................ 574, 703, 719, 727 EPSZ0o....................... 570, 702, 718, 726 EPSZ2o....................... 570, 702, 718, 726 EPSZ3o....................... 570, 702, 719, 726 EPSZ6......................... 571, 703, 719, 726 EXCPGCR.................. 502, 701, 715, 725 EXPEVT..............157, 159, 698, 705, 722 FCLR .......................... 572, 703, 719, 727 FRQCR ....................... 340, 700, 711, 724 HBCEDR.................... 528, 702, 716, 726 HBHEDR.................... 528, 702, 716, 726 HCCEDR.................... 527, 702, 716, 726 HCHEDR.................... 527, 702, 716, 725 HCSR.......................... 516, 701, 715, 725 HCTLR ....................... 513, 701, 715, 725 HDHEDR.................... 528, 702, 716, 726 HFIR ........................... 529, 702, 716, 726 HFNR ......................... 532, 702, 717, 726 HFRR.......................... 531, 702, 717, 726 HHCCAR.................... 526, 702, 716, 725 HIDR .......................... 524, 701, 715, 725 HIER........................... 521, 701, 715, 725 HISR ........................... 518, 701, 715, 725 HIZCRA...................... 652, 703, 720, 727 HLSTR........................ 534, 702, 717, 726 HPCEDR..................... 527, 702, 716, 725 HPSR .......................... 533, 702, 717, 726 HRDRA ...................... 535, 702, 717, 726 HRDRB....................... 537, 702, 717, 726 HREVR....................... 512, 701, 715, 725 HRPSR........................ 540, 702, 717, 726 HRSR .......................... 538, 702, 717, 726 IAR ..................................................... 308 IAR_0.................................. 699, 709, 723 IAR_1.................................. 699, 710, 723 IAR_2.................................. 699, 710, 723 IAR_3.................................. 700, 711, 723 ICR0............................ 204, 699, 706, 722 ICR1............................ 205, 699, 706, 722 ICR2............................ 207, 699, 706, 722 IER0 ............................ 563, 702, 718, 726 IFR0 ............................ 551, 702, 718, 726 IMCR .................................................. 210 IMCR0 ................................ 698, 706, 722 IMCR1 ................................ 698, 706, 722 IMCR4 ................................ 698, 706, 722 IMCR5 ................................ 698, 706, 722 IMCR6 ................................ 698, 706, 722 IMCR9 ................................ 698, 706, 722 IMR..................................................... 208 IMR0................................... 698, 706, 722 IMR1................................... 698, 706, 722 IMR4................................... 698, 706, 722 IMR5................................... 698, 706, 722 IMR6................................... 698, 706, 722 IMR9................................... 698, 706, 722 INTEVT2 ............ 157, 159, 698, 705, 722 IPR ...................................................... 202 IPRA ................................... 698, 705, 722 IPRB.................................... 698, 706, 722 IPRC.................................... 698, 706, 722 IPRD ................................... 698, 706, 722 IPRE.................................... 698, 706, 722 IPRF .................................... 698, 706, 722 IPRG ................................... 698, 706, 722 Rev. 1.00, 02/04, page 801 of 804 IPRH................................... 698, 706, 722 IRR0 ............................208, 699, 706, 722 ISR0.............................558, 702, 718, 726 MCCR .........................365, 700, 711, 724 NCCR ..........................654, 703, 720, 727 PACR...........................641, 703, 719, 727 PADR ..........................628, 703, 719, 727 PBCR...........................643, 703, 719, 727 PBDR...........................629, 703, 719, 727 PDCR...........................644, 703, 719, 727 PDDR ..........................631, 703, 719, 727 PECR ...........................646, 703, 720, 727 PEDR...........................633, 703, 719, 727 PGCR...........................647, 703, 720, 727 PGDR ..........................636, 703, 719, 727 PHCR...........................649, 703, 720, 727 PHDR ..........................637, 703, 719, 727 PSELA.........................650, 703, 720, 727 RTCNT ........................246, 699, 708, 723 RTCOR........................247, 699, 708, 723 RTCSR ........................245, 699, 708, 723 RWTCNT ....................247, 699, 708, 723 SAR .................................................... 301 SAR_0 ........................................ 699, 723 SAR_1 ................................ 699, 709, 723 SAR_2 ................................ 699, 710, 723 SAR_3 ................................ 699, 710, 723 SAR0 .................................................. 709 SCBRR ............................................... 456 SCBRR_0 ........................... 701, 714, 725 SCBRR_1 ........................... 701, 714, 725 SCFCR................................................ 458 SCFCR_0............................ 701, 714, 725 SCFCR_1............................ 701, 715, 725 SCFDR ............................................... 461 SCFDR_0 ........................... 701, 714, 725 SCFDR_1 ........................... 701, 715, 725 SCFER................................................ 449 SCFER_0............................ 701, 714, 725 SCFER_1............................ 701, 714, 725 SCFRDR............................................. 440 SCFRDR_0......................... 701, 714, 725 SCFRDR_1......................... 701, 715, 725 Rev. 1.00, 02/04, page 802 of 804 SCFTDR ............................................. 441 SCFTDR_0 ......................... 701, 714, 725 SCFTDR_1 ......................... 701, 715, 725 SCRSR................................................ 440 SCSCR................................................ 445 SCSCR_0............................ 701, 714, 725 SCSCR_1............................ 701, 714, 725 SCSMR ............................................... 442 SCSMR_0 ........................... 701, 714, 725 SCSMR_1 ........................... 701, 714, 725 SCSSR ................................................ 450 SCSSR_0 ............................ 701, 714, 725 SCSSR_1 ............................ 701, 714, 725 SCTDSR ............................................. 461 SCTDSR_0 ......................... 701, 714, 725 SCTDSR_1 ......................... 701, 714, 725 SCTSR ................................................ 440 SDBPR................................................ 685 SDBSR................................................ 686 SDCR.......................... 242, 699, 708, 723 SDID ................................................... 691 SDID/SDIDH .......................... 704, 721, 728 SDID/SDIDL ...................... 704, 721, 728 SDIR ........................... 685, 704, 721, 728 SDMR3 ............................... 699, 708, 723 SICDAR...................... 406, 700, 713, 724 SICTR ......................... 387, 700, 713, 724 SIFCTR....................... 401, 700, 713, 724 SIIER .......................... 399, 701, 713, 724 SIMDR........................ 384, 700, 713, 724 SIRCR......................... 393, 701, 714, 725 SIRDAR...................... 405, 700, 713, 724 SIRDR......................... 391, 701, 713, 724 SISCR ......................... 403, 700, 713, 724 SISTR ......................... 394, 700, 713, 724 SITCR ......................... 392, 701, 713, 725 SITDAR...................... 404, 700, 713, 724 SITDR......................... 390, 701, 713, 724 SPICR ......................... 408, 701, 714, 725 STBCR........................ 360, 700, 711, 724 STBCR2...................... 361, 700, 711, 724 STBCR3...................... 362, 700, 711, 724 STBCR4...................... 363, 700, 711, 724 TCNT.................................................. 376 TCNT_0.............................. 700, 712, 724 TCNT_1.............................. 700, 712, 724 TCNT_2.............................. 700, 712, 724 TCOR ................................................. 376 TCOR_0 ............................. 700, 712, 724 TCOR_1 ............................. 700, 712, 724 TCOR_2 ............................. 700, 712, 724 TCR .................................................... 374 TCR_0 ................................ 700, 712, 724 TCR_1 ................................ 700, 712, 724 TCR_2 ................................ 700, 712, 724 TEA ............................ 157, 698, 705, 722 TRA ............................ 156, 698, 705, 722 TRG ............................ 571, 703, 719, 726 TSR............................. 576, 703, 719, 727 TSTR .......................... 374, 700, 712, 724 U memory ........................................... 728 WTCNT ...................... 349, 700, 711, 724 WTCSR ...................... 349, 700, 711, 724 X/Y memory ....................................... 728 Repeat end register ................................... 78 Repeat mode transfer .............................. 315 Repeat start register .................................. 78 Reset state ................................................. 29 Resets...................................................... 164 RF-IC...................................................... 614 Round-robin mode.................................. 318 Save program counter ............................... 43 Save status register ................................... 43 SDRAM interface ................................... 259 Sequential break ..................................... 674 Serial clocks............................................ 410 Serial communication interface with FIFO ................................................................ 435 Serial I/O with FIFO ............................... 381 Shadow area............................................ 222 Single address mode ............................... 323 Single data transfer instructions ................ 98 Sleep mode.............................................. 366 Software standby mode........................... 366 SPI mode................................................. 430 Stall operations ....................................... 602 State transitions....................................... 369 Status register................................ 36, 41, 77 System registers .................................. 36, 39 T bit........................................................... 47 TAP controller ........................................ 692 Timer unit ............................................... 371 U memory ............................................... 195 U0 area...................................................... 32 USB function controller .......................... 547 USB host controller................................. 509 USB pin multiplex controller.................. 499 USB standard commands ........................ 601 User break controller............................... 655 User debugging interface ........................ 683 User mode ................................................. 30 Uxy area.................................................... 33 Vector base register................................... 44 Voice codec IC........................................ 616 Watchdog timer....................................... 347 Watchdog timer mode............................. 353 Write hit .................................................. 184 Write miss ............................................... 184 X/Y memory ........................................... 191 Rev. 1.00, 02/04, page 803 of 804 Rev. 1.00, 02/04, page 804 of 804 SH7660 Hardware Manual Publication Date: Rev. 1.00, February 6, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2004 Renesas Technology Corp. All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com Colophon 1.0 SH7660 Hardware Manual REJ09B0032-0100Z |
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